Review
Progress in the developments of (Ba,Sr)TiO
3
(BST)
thin films for Gigabit era DRAMs
S. Ezhilvalavan, Tseung-Yuen Tseng
Department of Electronics Engineering and Institute of Electronics, National Chiao-Tung University, 1001 Ta Hsueh Rd, Hsinchu-300, Taiwan Received 8 July 1999; received in revised form 19 February 2000; accepted 25 February 2000
Abstract
This paper reviews the recent developments of (Ba,Sr)TiO3(BST) thin films for future Gbit era dynamic random access memory (DRAM) applications. The trends of DRAM capacitors in the last decade are briefly described first. Then the technological aspects of BST films such as deposition techniques, post-annealing, physical, electrical and dielectric characteristics of the films, effects of electrode materials, dielectric relaxation and defect analysis and the reliability phenomena associated with the films are briefly reviewed with specific examples from recent literature. The basic mechanisms that control the bulk electrical conduction and the origin of leakage currents in BST films are also discussed. Finally, possible developments of gigabit era DRAM technology are summarized. © 2000 Elsevier Science S.A. All rights reserved.
Keywords: BST; Thin films; Dielectrics; DRAM capacitors; Leakage current density; Dielectric constant; Reliability
1. Introduction
Previous and today’s dynamic random access memories (DRAMs) have been advanced by mainly focussing on how to make memory cells small to realize high density DRAMs. The continuous ‘shrink technology’ up to Gbit density ex-poses many challenges. The most critical challenges in gi-gabit density DRAMs are yield loss due to large die size and small feature size, standby current failure caused by large chip size and small data retention times owing to reduced charge packet in the memory cell. Narrowing the bandwidth mismatch between fast processors and slower memories and achieving low-power consumption together with aforemen-tioned challenges drive DRAM technologies toward smaller cell size, faster memory cell operation, less power consump-tion and longer data retenconsump-tion time. In addiconsump-tion, a tight con-trol of increasingly complicated wafer processing requires DRAM process technology to be simpler and less sensitive to processing variation. Thus, DRAM technology in Gbit era should solve the challenges imposed by the shrink tech-nology system application requirement and manufacturing technology [1–5].
One of the most critical challenges which Gbit density DRAMs face will be memory cell capacitance. Memory cell
E-mail address: [email protected] (T.-Y. Tseng)
capacitance is the crucial parameter which determine the sensing signal voltage, sensing speed, data retention times and endurance against the soft error event. It is generally accepted that the minimum cell capacitance is more than 25 fF per cell regardless of density. However, lower supply voltage and increased junction leakage current due to high doping density drive memory cell capacitance toward higher value more than 25 fF per cell in the Gbit density DRAMs. The strategy to increase memory cell capacitance has been focussed on the increase of the memory cell capacitor area and decrease of the dielectric thickness up to now.
In the memory cell capacitor which is the most important technology in the Gbit era, high dielectric constant capacitor seems to be the only solution [6–8]. In the recent years thin film perovskite materials with high dielectric constant such as PZT, SrTiO3 and (Ba,Sr)TiO3 (BST) [9–25] have been investigated as dielectric materials for future DRAMs. The best suited dielectric material would have a low leakage current and a high dielectric constant and would also be in paraelectric phase to avoid fatigue from ferroelectric domain switching. SrTiO3has a smaller dielectric constant than BST and PZT is in ferroelectric phase at room temperature. Thus, BST is very appealing for DRAM capacitors.
Barium strontium titanate (Ba,Sr)TiO3 (BST) thin films are being widely investigated as alternative dielectrics for ultra large scale integrated circuits (ULSIs) DRAM storage 0254-0584/00/$ – see front matter © 2000 Elsevier Science S.A. All rights reserved.
capacitors due to its (1) high dielectric constant (εr>200), (2) low leakage current, (3) low temperature coefficient of electrical properties, (4) small dielectric loss, (5) lack of fatigue or aging problems, (6) high compatibility with device processes, (7) linear relation of electric field and polarization and (8) low Curie temperature [11–13,26–31]. However, whether or not BST thin film can be successfully applied largely depends on more thorough understanding the material’s properties. The deposition techniques and electrical properties of BST films have received increasing interest. According to those investigations the electrical and dielectric properties and reliability of BST films heavily de-pend upon the deposition process, post-annealing process, composition, base electrodes, microstructure, film thickness, surface roughness, oxygen content and film homogeneity.
Successful applications of any thin film material require the development of sophisticated synthesis and process-ing techniques, the understandprocess-ing of structure–property relationships and the implementation of various novel de-vices. The purpose of this paper is to present an overview of BST film production methods, electrode selection, microstructure–property relationships, leakage current re-duction and reliability of the film and its applicability to the processing of the next generation of ultra-large-scale integrated (ULSI) DRAMs.
In this review, we first describe the different methods of BST thin film material processing, since they are the ulti-mate factors determining the oxide properties. We then look into the main physical and electrical characteristics, high-lighting some well established experimental results. Specific examples from the recent literature are reviewed to exem-plify how the technique has been utilized to date in solid state technology. The general theories of electrical conduc-tion mechanisms and the various methods of leakage current reduction are reviewed in order to check the limits of their applicability to ULSI. Background information is given on the materials chemistry and physics and over 164 references are cited. The paper will end with a critical review of sum-mary and future trends.
1.1. Trends in the development of ULSI DRAM capacitors
The capacitor materials currently utilized in DRAMs are either silicon dioxide (SiO2) or a silicon oxide/nitride com-posite layer (ONO) with a relative dielectric constant of 6.
Table 1
The road map of DRAM technology [32]
Minimum feature size (m) C/A (fFm−2) Capacitor area (m2) Operating voltage (V) Yeara1 Million devices
16 Mbit 0.60 25 1.10 3.3 1992
64 Mbit 0.35 30 0.70 3.3 1995
256 Mbit 0.25 55 0.35 2.2 1998
1 Gbit 0.18 100 0.20 1.6 2001
4 Gbit 0.15 140 0.10 1.1 2004
aYear in which 1 million devices were/are projected to be produced.
Table 2
Medium dielectric constant materials [35]
Dielectric ε (thick films) Ccrit(fFm−2)a Growth
Ta2O5 25 13.8 (20.4) MOCVD 50 Sputtering TiO2 30–40 9.3 MOCVD ZrO2 14–28 9.9 MOCVD Nb2O5 30–100 – – Y2O3 17 4.7 Sputtering Si3N4 (comparison) 7 7–8.6 (120) MOCVD aThe values in parenthesis are given for the case of a HSG-rugged
Si capacitor.
Use of SiO2or ONO allows the memory cell to be fabricated as a metal-oxide-semiconductor (MOS) device. As the num-ber of memory cells increase to gigabits, the available area for the capacitor decreases rapidly (≈0.4 m2for a 256-Mbit device and 0.2m2for a 1-Gbit device) to maintain accept-able die sizes. Taccept-able 1 indicates that the capacitance-per-unit area should be increased to achieve higher DRAM densi-ties [32]. For maintaining sufficient storage capacitance of memory cell, manufacturers have abandoned the idea of flat integrated circuits and three-dimensional cell structures were consequently incorporated by use of deep trenches and stacked layer to offer more surface area. So far, these struc-tures with ONO storage dielectrics can adhere to the re-quirements of 256-Mbit DRAMs. The capacitor areas will be close to 0.2 and 0.1m2 for future 1-Gbit and 4-Gbit DRAMs, respectively, and there is a requirement that the capacitance per unit area be increased as shown in Table 1. The ONO dielectrics will not be used in these products since the capacitor area cannot be maintained constant in a cell that is still manufacturable and also the ONO dielectric thickness has reached a lower limit set by electron tunneling through the dielectric [33,34]. Consequently, an increasing effort has been made in search of alternative dielectric hav-ing a substantially higher permittivity.
The first step in the direction of high dielectric constant materials is to consider some single metal oxide materi-als such as Ta2O5, TiO2, or others. Table 2 illustrates the dielectric constant and critical capacitance (defined as the maximum capacitance-per-unit area that can be achieved for a film that satisfies DRAM leakage requirements) [35] for various single metal oxides that present dielectric constant values in the range 10–100. As can be seen, the highest capacitance values can be obtained for Ta2O5 films. These
Table 3
High dielectric constant materials for DRAM applications [35]
Dielectric ε t (nm) Ccrit (fFm−2) References
SrTiO3 230 53 55.0 [14] (Ba1−xSrx) TiO3 (BST) 320 70 40.5 [42] 800 60 118.1 Ba (Ti0.8Sn0.2)TiO3 (BTS) 210 100 – [43] (Ba,Pb) (ZrTi)O3 (BPZT) 200 200 8.9 [44] (Pb1−xLax) TiO3(PLT) 1400 500 24.8 [45] (Pb,La) (Zr,Ti) O3(PLZT) 1474 150 87.0 [46] (PbZr1−x) TixO3 (PLT) >1000 70 >70.0 [47]
films are also compatible with MOS fabrication facilities and can be easily deposited by the chemical vapor deposition (CVD) technique required to form complex 3D features. In-tegration issues relative to the choice of electrodes, in partic-ular, a top CVD-TiN electrode is needed and post-deposition annealings have to be limited to obtain the best film prop-erties, before such film can be used in mass production [36,37]. The reported storage capacitances for Ta2O5 are around 10–20 fF m−2[38]. If utilized at all, it appears that Ta2O5will only be appropriate for one DRAM generation [38–41].
On the other hand, ferroelectric materials are considered the ideal DRAM dielectrics for the Gbit era since they ex-hibit dielectric constants in the range 200–2000 range. These values are much lower, however, when thin films are consid-ered. For DRAM applications, ferroelectric films that are in the paraelectric phase in the DRAM operating temperature range should be considered to benefit from the full stored charge during the read operations. Table 3 lists some of the most promising ferroelectric material candidates for DRAM applications. Among this, (Ba1−xSrx)TiO3(BST) films have recently been investigated as the most promising capacitor material in future DRAM applications because the films have the advantages of a low leakage current, a room temperature paraelectric with a high dielectric constant and a large dielec-tric breakdown strength [41–48]. High dielecdielec-tric BST ca-pacitor is basically formed in metal-insulator-metal (MIM) structure. In this MIM structure, the storage poly-silicon electrode is replaced with metal electrode. By using a proper metal electrode to have strong resistance to native oxide, the native oxide on storage electrode can be completely removed. Pt-storage node electrode is one of the good ex-amples for metal to have strong resistance to oxidation. Therefore, MIM cell capacitor using BST dielectric seems to be the ultimate solution for the Gbit era. Fig. 1 compares the leakage capacitance characteristics of BST, Ta2O5 and ONO dielectrics to illustrate the considerable improvement that can be obtained with such materials. While the capac-itance improvements are clear, the integration issues faced with the introduction of these new materials are not simple. Although the BST capacitor can provide the sufficient cell capacitance for the Gbit era, many issues regarding BST ca-pacitor should be solved. The key issues of BST caca-pacitor are barrier height between metal electrodes and BST
dielec-tric, thickness dependent dielectric constant, crystallization temperature after BST film deposition, the barrier layers be-tween storage electrode and poly-silicon plug and its re-sistance to oxidation during crystallization temperature and electrode formation. The current conduction of BST capac-itor is known to be governed by Schottky emission current [50]. Since the Schottky conduction current is strongly de-pendent on the barrier height between metal electrode and BST, the metal electrode giving a higher barrier height is needed. It is very important to control surface property of metal electrode and interface property between metal elec-trode and BST in order to maintain good barrier property. The dielectric constant of BST is known to be dependent on the thickness of the BST film [51]. As BST film thick-ness decreases, the dielectric constant decreases. This can be explained by the lower dielectric constant resulting in depletion region between metal and BST dielectric. The de-posited BST dielectric requires a high temperature annealing around 750◦C in O2ambient in order to achieve crystalline structure. Crystalline structures of BST film is found to have higher dielectric constant and lower leakage current density [52]. During high-temperature annealing in O2ambient, con-siderable amount of oxygen penetrates storage Pt electrode, resulting in oxidizing poly-silicon at the interface between plugged poly-silicon and BST film. Therefore, the barrier
Fig. 1. Voltage at 1A cm−2 vs. capacitance for ONO, Ta2O5and BST
layer to block the oxygen penetration is needed between Pt electrode and plugged poly-silicon. The barrier layer should have resistance to oxygen penetration at high annealing tem-perature. Unfortunately, TiN/Ti barrier commonly used in current metallization scheme is not proper because of loss of barrier property around 500◦C. Another thing is the elec-trode formation because it determines the surface area of ca-pacitor. A more vertical etching profile of storage node and a larger capacitor area can be achieved. So far the Pt electrode is found to have superior leakage current characteristics as well as the highest capacitance [38,41]. But Pt is very diffi-cult to etch vertically [53]. Ru or RuO2electrodes are found to be easy in vertical etching. However, Ru or RuO2 based BST capacitor suffers from higher leakage current and lower dielectric constant. Therefore, the above mentioned issues need to be fully understood before BST films are subjected to mass production. In the following sections, we have ad-dressed these issues in detail by making use of the extensive research work carried out on BST films by various groups.
1.2. Barium strontium titanate (BST) thin films
BaTiO3 is a ferroelectric perovskite and has been well studied in bulk ceramic form where the measured permit-tivities are well into the thousands. The utilization of the BaTiO3–SrTiO3 solid solution allows the Curie tempera-ture (ferroelectric–paraelectric transition temperatempera-ture, Tc) of BaTiO3can be shifted from 120◦C to around room temper-ature for Ba1−xSrxTiO3films. For Sr addition into BaTiO3, the linear drop of Tc is ca. 3.4◦C per mol%. Therefore, 30 mol% Sr (x=0.3) would bring the Tcdown to room tem-perature. The effect of several isovalent substitutions on the transition temperatures (Curie temperature) of ceramic BaTiO3is as shown in Fig. 2 [6,28,42,46,49]. Ba1−xSrxTiO3
Fig. 2. Effect of several isovalent substitutions on the transition temper-ature of ceramic BaTiO3 [49].
films are not only paraelectric at the DRAM operating tem-perature range (0–70◦C ambient and 0–100◦C on chips) [33], but also achieve maximum permittivity around the operat-ing temperature. On the other hand, the volatilities of the BST components are lower than Pb-based ferroelectric ma-terials, thereby making it relatively easier to introduce into fabrication facilities [33,34].
BST films are polycrystalline. Their properties heavily de-pend on composition, stoichiometry, microstructure (grain size and size distribution), film thickness, characteristics of electrode, and homogeneity of the film. The BST thin film growth method significantly affects the composition, stoichiometry, crystallinity, and grain size of the film and, consequently, its dielectric properties. A variety of tech-niques such as rf-sputtering [42,46,51,52], laser ablation [79], metal-organic deposition (MOD) [54,55], chemical va-por deposition (CVD) [56–58], and sol–gel processing [59] have been used to deposit BST thin films. Above methods are highly competitive, each having advantages and disad-vantages in terms of homogeneity, processing temperature, and processing costs. Because of the multicomponent nature of BST materials precise microscopic control of stoichiom-etry is essential for obtaining uniform single phase films.
The basic parameters for applying capacitor thin films on DRAMs are dielectric constant, leakage current density and reliability. The targets for ideal Gbit era DRAM di-electrics include the followings [33]: (i) SiO2 equivalent thickness <0.2 nm for Gbit; (ii) leakage current density
<1×10−7A cm−2at 1.6 V; (iii) life time 10 years at 85◦C
and 1.6 V; (iv) stability 1015 cycles at >100 MHz; and (v) general compatibility to semiconductor processing.
2. Materials processing
Deposition process are generally divided into two cat-egories: physical vapor deposition (PVD); and chemical vapor deposition (CVD). CVD is of the most interest since PVD processes such as evaporation and sputtering do not generally produce films of the same quality as CVD processes. The commonly used techniques for depositing dielectric thin films include low pressure chemical vapor deposition (LPCVD), metal organic chemical vapor deposi-tion (MOCVD), sputtering, pulse laser abladeposi-tion, and sol–gel methods. Each technique has its merit and drawbacks. For example, MOCVD can be used for large scale production but elevated growing temperature is required for cracking the metal-organic (MO) source. Pulse laser ablation is suit-able for low temperature epitaxial growth but it can only process samples on limited scale. Thin films are used in a host of different applications in ULSI fabrication and can be prepared by a variety of techniques. Regardless of the method by which they are formed, however, the process must be economical and the resultant films must exhibit the following characteristics: (a) good thickness uniformity; (b) high purity and density; (c) controlled composition
stoichiometries; (d) high degree of structural perfection; (e) good electrical properties; (f) excellent adhesion; and (g) good step coverage [60].
In the recent, rapid thermal annealing (RTA) has become more important in the application on ULSI technologies, such as thin dielectric deposition, polysilicon growth, shal-low junction formation, silicidation and annealing [61,62]. The great advantages of the technique are a rather short pro-cessing time and its relative process simplicity as compared with the conventional furnace apparatus. A short processing time will be beneficial to reduce the time–temperature prod-uct such that the physical or chemical processes are com-pleted while unwanted processes such as dopant diffusion penetration, interface reactions and decomposition are effec-tively controlled. Rapid thermal N2O annealing (RTN2O) has been applied to reduce the leakage current in the BST films prepared by CVD [33].
Table 4 shows the comparison of the best properties of BST films prepared by various methods. Among the various techniques described above, the most common techniques that have been frequently utilized to deposit BST thin films are dc and rf-sputtering, CVD, PECVD, MOCVD, LSCVD, ECR-CVD, laser ablation and sol–gel method. For
Table 4
Comparison of electrical data from BST samples prepared by various deposition techniques
Deposition Composition Film thick- Dielectric Leakage current Dielectric strength Capacitor structure References techniques ness (nm) constant density (A cm−2) (MV cm−1) @ (Top/BST/Bottom)
@ 100 kV cm−1 10−6A cm−2
rf-Sputtering Ba0.75Sr0.25TiO3 80 320 1×10−8 0.5 Pt/BST/Pt [63]
rf-Sputtering Ba0.75Sr0.25TiO3 60 400 1×10−7 0.5 Pt/BST/Pt [64]
rf-Sputtering Ba0.65Sr0.35TiO3 100 400 5×10−9 0.35 Pt/BST/Pt [65]
rf-Sputtering Ba0.5Sr0.5TiO3 100 470 3×10−9 0.5 TiN/BST/Pt [66]
rf-Sputtering Ba0.5Sr0.5TiO3 100 600 3×10−7 0.3 Pt/BST/Pt [67]
rf-Sputtering Ba0.5Sr0.5TiO3 100 250 3×10−7 0.7 Pt/BST/LNO [68]
rf-Sputtering Ba0.5Sr0.5TiO3 60 200 1×10−8 1 Pt/BST/SRO [69]
rf-Sputtering Ba0.5Sr0.5TiO3 36 338 2×10−8 0.69 Pt/BST/Ir Pt/BST/IrO2 [70]
rf-Sputtering Ba0.5Sr0.5TiO3 100 375 8×10−9 1.6 Pt/BST/Pt [71]
rf-Sputtering Ba0.5Sr0.5TiO3 100 230 8×10−8 0.5 BRO/BST/BRO [72]
rf-Sputtering Ba0.5Sr0.5TiO3 20 274 8×10−9 1 SRO/BST/SRO [73]
rf-Sputtering Ba0.5Sr0.5TiO3 75 350 1×10−7 – LSCO/BST/LSCO [74]
rf-Sputtering Ba0.5Sr0.5TiO3 120 600 10−9 – Pt/BST/TiO2/Pt [75]
rf-Sputtering Ba0.5Sr0.5TiO3 100 573 10−7 – Pt/BST/RuO2 [76]
ECR-sputtering Ba0.55Sr0.45TiO3 200 320 2×10−7 0.09 Pt/BST/Pt [77]
Excimer laser ablation Ba0.5Sr0.5TiO3 200 375 5×10−7 0.15 Pt/BST/Pt [78]
Excimer laser ablation Ba0.5Sr0.5TiO3 500 467 10−7 – Au/BST/Pt [79]
MOCVD Ba0.7Sr0.3TiO3 40 450 2×10−8 0.7 Pt/BST/Pt [80]
MOCVD Ba0.7Sr0.3TiO3 40 210 1×10−8 0.37 Ir/BST/Pt [66]
ECR-MOCVD Ba0.4Sr0.6TiO3 100 600 7×10−7 0.15 Al/TiN/BST/RuO2 [81]
ECR-PCVD Ba0.5Sr0.5TiO3 27 140 1×10−8 0.44 Pt/BST/Pt [82] LSCVD Ba0.5Sr0.5TiO3 200 300 3×10−7 0.15 Pt/BST/Pt [83] LSCVD Ba0.5Sr0.5TiO3 50 200 1×10−8 0.35 Pt/BST/Pt [84] LSCVD (Ba, Sr)1+x TiO3+x x=±0.2 30 260 1×10−7 – Pt/BST/Pt [85] CVD Ba0.5Sr0.5TiO3 100 400 8×10−8 0.7 Pt/BST/Pt [86] MOD Ba0.7Sr0.3TiO3 140 420 1×10−9 0.43 Pt/BST/Pt [54]
MOD Ba0.7Sr0.3TiO3 300 563 10−6 – Au/BST/Pt [87]
MOD Ba0.7Sr0.3)
(Ti0.95 Nb0.05) O3
300 250 2×10−6 – Au/BST/Pt [87]
application to storage capacitors, the dielectric films must have a very small leakage current to maintain the favorable retention characteristics and in the case of topography for three-dimensional memory cells have the ability for excel-lent step coverage. DC or rf-sputtering deposition has the advantage of depositing BST films at low temperatures, which is very desirable for applications where the process-ing temperature or thermal budget is a major concern. A major difficulty in the sputtering deposition technique is choosing the process conditions to obtain stoichiometric BST films at the highest deposition rate. Several researchers have investigated the sputtering deposition process and have proposed different criteria of the deposition condition for preparing stoichiometric BST films.
Although as-deposited sputtered films have low leakage currents in amorphous phase, the high temperature treat-ments, which are necessary for standard DRAM processes, will lead to the crystallization of these films and hence a drastic increase in the leakage current [33,41]. This, ob-viously, limited their application on DRAMs in terms of the refresh characteristics of the cells. ECR-CVD process provides lower processing temperature (≤500◦C), for BST films thereby keeps the leakage current at the lower level
(<10−6A cm−2) and also helps to use various multiple elec-trode structures such as RuO2/Ru/TiN/TiSix, which are not stable otherwise at higher temperatures >750◦C [88] The as-deposited CVD BST films have rather leaky current char-acteristics due to oxygen deficiency and impurity contami-nation existing in films, this can be significantly reduced to acceptable levels for applications by annealing techniques. Reports indicate that RTA processed BST thin films in O2 or N2O ambients showed better electrical characteristics [33,41]. CVD BST films can provide better step coverage ability and good thickness uniformity across the wafer. Thus, based on the consideration of the electrical characteristics and step coverage, CVD BST is more suitable for applica-tion to mass producapplica-tion.
3. Factors that influences BST thin film properties
The parameters that have been identified to affect the properties of BST film capacitors are processing methods, annealing conditions, microstructure, interface structure, electrode materials and their correlation. These factors are discussed briefly as follows.
3.1. Processing methods
A variety of deposition techniques, such as rf- and ion-beam sputtering, laser ablation, chemical vapor deposition, metallo-organic deposition and sol–gel have been success-fully used to synthesize BST films. The various techniques employed to fabricate BST films are designed to produce the films’ specific microstructure and dielectric properties. In addition, it is also essential to obtain the lowest possi-ble process temperature to comply with silicon technology and to minimize post-deposition thermal treatments under low oxygen partial pressures to maintain the resistance of the films. Meanwhile, maintaining precise microscopic con-trol of the stoichiometry, large area deposition and achieving good step coverage, are also relevant tasks [33,41].
The deposition methods stated above are highly com-petitive. Each method has its own merits and limitations related to the deposition mechanics and film properties. For instance, the properties of rf-sputtered BST films can satisfy the requirements for use in a 256-Mbit DRAM ca-pacitor. The rf-sputtering method using a multicomponent oxide target not only satisfies this requirement but is also an appropriate method to produce BST films. NEC, Mitsubishi and Samsung have made great studies in rf-magnetron sput-tered (Ba0.5Sr0.5)TiO3 films to a practical stacked DRAM capacitor [42]. They sputter deposited thin BST films hav-ing an equivalent SiO2 thickness of 8 Å over Pt/Ta elec-trodes, subsequently attaining an unit area capacitance of 40 fFm−2 and leakage current of <10−7A cm−2. They also observed the dependence of dielectric constant on film thickness, BST’s dielectric constant decreased with reduced film thickness. The dielectric constant of the 70 nm thick
film exceeds 300 and 200 nm thick film is more than 600, which are much larger than those of SrTiO3. Mitsubishi deposited thin (Ba0.75Sr0.25)TiO3 films by an rf-sputter at substrate temperatures of 480–750◦C [89]. The 30 nm thick films deposited at 660◦C on Pt/SiO2/Si substrate have a dielectric constant of 250 corresponding to an equivalent SiO2thickness of 0.47 nm, and a leakage current density ca. 1×10−8A cm−2which partially satisfy the requirements for use in a 256-Mbit DRAM capacitor. Samsung researchers have studied rf-magnetron sputtered (Ba0.5Sr0.5)TiO3films with thickness of 15–50 nm at 640–660◦C on 6 in. Pt/SiO2/Si substrates and post-annealed at 550–850◦C in O2 or N2 [52]. The 20 nm thick film with SiO2 equivalent thickness of 0.24 nm possesses a leakage current of 4×10−8A cm−2 and unit area capacitance of 145 fFm−2which is the high-est storage capacitance reported to date for BST films. They also contended that the N2annealing of the BST thin film af-ter the top electrode deposition is critical for obtaining a low leakage current because n-type BST film is required to form a high interfacial potential energy barrier. However, their dielectric constants are insufficiently large for application to a Gbit era DRAM with a planar type storage capacitor.
The pulsed laser deposition method have been success-fully used to synthesize (Ba0.5Sr0.5)TiO3 thin films [79]. Though this method has the ability to grow crystalline films at low substrate temperature with a good control of stoichiometry, the reported leakage current density values are very high. The MOD technique provides advantages of reproducible coating thickness and compositions and low deposition cost. Fujii et al. [54], employed this tech-nique to prepare BST films over Pt/Ti/Si substrate based on alcohol-based precursor liquid. They obtained the de-pendence of the lattice constant and the dielectric constant of the fabricated BST film on the Sr composition. These results present maximum dielectric constants for films close to the composition of Ba0.7Sr0.3TiO3. They also employed this BST film which allows the planar-type single stack structure to be incorporated into the ULSI DRAM storage capacitor and achieve 1.3 nm equivalent SiO2thickness and 2×10−9A cm−2leakage current density at 3.3 V.
The advantages of CVD include a high deposition rate, uniform deposition over large areas and satisfactory step coverage [60]. However, the CVD of BST film is re-stricted by a low vapor pressure of source materials and deterioration during storage. Researchers at Mitsubishi Electric Corporation have developed an alternative way of precursor transportation. That is, suitable precursors are dissolved in organic liquids and the liquid is injected into a CVD reactor [84]. The liquid-source delivery methods have produced BST thin films on 6-in. Pt/SiO2/Si sub-strates by using Ba (DPM)2, Sr(DPM)2 and TiO(DPM)2 (DPM=dipivaloylmethanato, C11H19O2) dissolved in tetrahydrofuran and achieved the reproducibility of ±3% for (Ba+Sr)/Ti, coverage of 72%, dielectric constant of 230, equivalent SiO2 thickness of 7.8 Å, and leakage current density of 6.7×10−6A cm−2at 1.65 V.
Mitsubishi also constructed a DRAM cell with dimen-sions appropriate for 1-Gbit device on the basis of a Ru/BST/Ru stacked capacitor. The BST films, having an equivalent SiO2thickness of 0.5 nm and excellent step cov-erage, were deposited at 420◦C by a two-step process of LSCVD. Moreover, NEC corporation employed ECR-CVD to develop a Gbit storage capacitors. The BST films having a thickness of 61 nm, were deposited on Pt/TaOx/Si sub-strates at 450◦C and treated with RTA at 700◦C for 1 min. These films had a dielectric constant of 220 and leakage current density of 3×10−7A cm−2 at 1 V [90]. They also developed ECR-MOCVD BST-based stacked capacitor with RuO2/Ru/TiN/TiSix storage nodes for Gbit DRAM genera-tions [91]. Sol–gel processing involves hydrolysis and con-densation of organo-metallic precursors where the resulting sol is coated onto the substrates and dried to a solid film (gel). The resulting gel film is then decomposed and densi-fied by heat treatment to produce a crystallized film. Tahan et al. [92] sol–gel deposited 400 nm thick (Ba0.8Sr0.2)TiO3 films on Pt/Ti/SiO2/Si substrates to obtain a dielectric con-stant of 400 and a leakage current density of 0.17A cm−2 at 3 V. Although the BST films with adequate dielectric properties can be deposited by using various techniques, on the basis of DRAM capacitor cell structures proposed by NEC, Mitsubishi, Samsung and US DRAM consortium, CVD BST films are required in the future Gbit era DRAM to increase the storage capacitance. Integration issues in-clude selection and stability of electrode and barrier layer materials, step coverage of dielectric films, high tempera-ture endurance and etching methods must be solved before high-permittivity film based DRAMs are commercialized.
Thus, the step coverage of BST films deposited using the CVD technique has attracted increasing attention for use in the side area of bottom electrodes in DRAM capacitors to increase the storage capacitance. NEC researchers have ap-plied ECR plasma MOCVD BST films to a practical stacked Gbit DRAM capacitor. Applying this stacked capacitor tech-nology can achieve a sufficient cell capacitance of 25 fF for 1-Gbit DRAMs in a capacitor area of 0.225m2with only 0.3m high storage nodes [88].
Comparison of the electrical properties of the BST films prepared using various deposition techniques are tabulated in Table 4. For the leakage current densities, an extremely large variation in results is found for capacitors using var-ious electrodes, compositions and thickness of BST films. This table also includes values of the dielectric constant for (Ba0.5Sr0.5)TiO3between 140 and 600. Different stud-ies markedly vary with respect to the dielectric breakdown strength. Such a variation might be ascribed to intrinsic film properties (e.g. microstructure and stoichiometry) as well as electrode and interface properties [33,41].
According to previous investigation, oxygen vacancies in BST films play a prominent role in the leakage current [93]. In general, BST films sensitive to oxygen deficiencies are prepared or annealed in oxygen ambience to reduce the con-centration of oxygen vacancies and to improve the dielectric
Fig. 3. Effect of OMR on the dielectric constant and leakage current of the Ba0.5Sr0.5TiO3 films deposited at 450◦C [71].
properties of the films. As recently demonstrated, the dielec-tric properties depend on a gas ratio of O2/(Ar+O2) (OMR) during rf-sputtered BST films [71]. In that investigation, the dielectric constant increased with an increase of OMR and reached a maximum value at 50% OMR (Fig. 3). The leak-age current density, although decreasing with an increasing oxygen flow, had a minimum value at 40% OMR. The film deposited at 450◦C and 50% OMR had a dielectric constant of 375 and leakage current density of 7.35×10−9A cm−2at an electric field of 100 kV cm−1with a delay time of 30 s. The BST films can exhibit large dielectric constants due to polarization of electric dipoles. It has been reported that the dielectric constant of the films was influenced by oxy-gen stoichiometry, composition, grain size, grain boundary and crystallinity (dipole density, polarization). High oxygen incorporation in the films seems to play an important role in promoting the polarization of electric dipoles. A related study fabricated the Pt/BST/Pt capacitors using a sputtering technique and post-annealed under a N2 or H2atmosphere indicating abnormally higher leakage current when the neg-ative bias was applied to the top electrode [94]. In addition, the enhanced leakage currents were effectively reduced by annealing under an O2atmosphere. These results can be ac-counted for by compensating for the oxygen vacancy in the BST films by introducing oxygen through the top Pt elec-trodes with the grain boundaries of the columnar structure acting as a diffusion path for the oxygen.
The properties of BST thin films prepared on (1 1 1) Pt/Ti/SiO2/Si and (1 0 0) Si substrates by pulsed laser ab-lation (PLA) were reported as a function of the target composition and the oxygen pressure [95]. Surface mor-phology of the films prepared at high oxygen pressure was rough compared with that of the films prepared at low oxy-gen pressure. Dielectric constant of those films was found to be lower than that of the films prepared at low oxygen pressure. The authors suggested that the excessively high oxygen pressure during the PLA deposition deteriorated the crystal structure and the dielectric property of the BST films depends on the composition of BST films.
BST thin films were deposited on Pt/SiO2/Si sub-strates with various O2/Ar ratios by rf-sputtering and the
crystallinity, microstructure and electrical properties of the films were investigated by Lee et al. [96]. The deposition rate decreased with increasing of the O2 content of the sputtering gas. It was believed that this resulted from the sputtering yield of O2−being lower than that of Ar+. Park et al. [97] examined how post-annealing affects the electrical properties of 20 nm thick sputtered BST films. According to their results, the dielectric constant increased without significantly increasing the leakage current by annealing at 750◦C. Later, Horikawa et al. [85] developed post-annealing process for 30 nm thick CVD-deposited BST films. Their results indicated that direct annealing of BST capacitors roughened the surface morphology of the upper Pt elec-trodes of BST capacitors. However, the post-annealing of capacitors with a silicon dioxide passivation only slightly changed the surface morphology of Pt and BST, and also did not significantly deteriorate the leakage current.
The deposition temperature, a major parameter in the de-position process, determines the decomde-position rate of the precursors and has a strong influence on the crystallinity and structure of the deposited films. Depositing good qual-ity BST thin films requires a rather high process temperature owing to its high crystallization temperature. In addition to influencing the BST material, high temperature process also affects the interfaces with the electrodes, which critically controls the overall electrical properties of the capacitor, par-ticularly when the BST film thickness is very small [52].
3.2. Film composition
Film composition pronouncedly affects the dielectric con-stant [80,85]. The film with a composition of Ba0.5Sr0.5TiO3 has the highest dielectric constant at room temperature. Sev-eral researchers have conferred that a film has it’s maximum dielectric constant at room temperature when the (Ba+Sr)/Ti ratio is 1:1. According to their results, the dielectric constant decreases when films are either titanium-rich or titanium poor [84]. It has been found that in (BaxSr1−x)Ti1+yO3+z, the factor y corresponding to the (Ba+Sr)/Ti ratio, strongly affects most film properties at a given x and deposition temperature [84,98,99] and is therefore one of the primary parameters used to control film performance. For example, BST films with x=0.7 have a maximum resistance degra-dation lifetime at approximately y=0.083, although the maximum value of the dielectric constant is found at y=0 [98]. Reasonable film behavior is generally achieved up to
y=0.15, which greatly exceeds the solubility of excess Ti
in bulk BST, of approximately y≤0.001. Given this large stoichiometry, a necessary step in understanding the com-position dependence of film properties is to determine the locations within the microstructure at which the excess ti-tanium is accommodated in BST thin films. Stemmer et al. [99] reported measurements of the microstructural accom-modation of nonstoichiometry in BST thin films grown by liquid source chemical vapor deposition (LSCVD). Their observations indicate that partial accommodation of excess
titanium in the grain interiors of polycrystalline BST films, either concurrent with or followed by accommodation at the grain boundaries. At extreme titanium excess, an amor-phous phase, possibly TiOx, was found between grains. The increased grain boundary area in these nanocrystalline films compared with that in much larger grained bulk ceramics, in combination with the nonequilibrated microstructure of the films due to lower processing temperature were said to be responsible for why Ti contents well beyond the bulk solid solubility limit are tolerated by their BST film structure.
It has been reported that the addition of dopants seriously influences the electrical properties of BST thin film capac-itors [100,101]. The effects of Al and Nb doping on the leakage current behavior of Ba0.5Sr0.5TiO3 thin films de-posited by rf-magnetron sputtering were reported by In et al. [101]. Al and Nb were known to replace Ti-sites of the BST perovskite. BST thin films deposited at room tempera-ture and annealed subsequently in air showed improved elec-trical properties. In particular, the leakage current density of the Al-doped BST thin film was measured to be around 10−8A cm−2at 125 kV cm−1, which was much lower than those of the undoped or Nb-doped thin films.
Copel et al. [102] investigated the effects of Mn im-purities on Ba0.7Sr0.3TiO3 films using X-ray photo emis-sion spectroscopy. The decrease in leakage current in the acceptor-doped films were attributed to the increased bar-rier to thermionic emission of electrons from Pt contacts into the dielectric. Doping in the films lowered the dielectric constant. This lowering effect is owing to the incorporation of aliovalent ions which hinders the crystallization of the films due to the requirement for higher solution energies to form compensating point defects [87]. In addition, the com-position of surfaces/interfaces also largely determines the properties of the films and the characteristics of the devices based on the film. These results suggest that the segregation of acceptor or donor dopants at the grain boundaries in the film’s interior heavily influences the barrier height, which could determine the leakage behavior in the BST thin films.
3.3. Crystalline structure
Crystalline BST films are usually obtained at relatively high substrate temperature. During the film growth, how-ever, inter-layers and specific grain structures are developed which cause serious problems of low dielectric constant and the leakage current. An alternative approach is to grow amorphous BST films at low temperature and to crystallize them in a post-annealing process. Improvement of the dielec-tric constant and the leakage currents has been reported on post-annealed amorphous BST films. The crystallization of amorphous BaxSr1−xTiO3thin film grown on single crystal MgO (0 0 1) substrate by rf-sputtering was studied by Noh et al. [103] in a synchrotron X-ray scattering experiment. Their study shows that a metastable intermediate phase that was nucleated at around 500–600◦C at the interface plays a crucial role in the crystallization process. In a 550 Å thick
film, the crystallization to perovskite phase was occurred at around 700◦C, while a 5500 Å thick film became crystalline at 550◦C. The thickness dependence of the crystallization was attributed to the observed intermediate phase nucleated at near 600◦C at the interface.
In thin films, high annealing temperature was required due to the energy barrier between the perovskite phase and the intermediate phase. In the thick films, the perovskite phase was nucleated directly from the amorphous phase in the bulk of the film concurrent to the nucleation of the intermediate phase at the interface. A transmission electron microscopy (TEM) study by Paek et al. [104] has also reported the ob-servation of an intermediate phase near the interface.
X-ray diffraction patterns of as-grown BST films de-posited at various substrate temperatures are shown in Fig. 4 [67]. Cubic perovskite structure of BST films was typically obtained under all conditions. As can be seen in Fig. 4, the crystal orientation and the crystallinity of the films are strongly dependent on the deposition temperature. Films deposited below 600◦C have the cubic perovskite struc-ture and show the polycrystalline state. The crystallinity of the films increases with increasing deposition temperature. Films deposited at 600 and 650◦C have textured structures with [1 1 0] and [1 0 0] orientations, respectively. At 650◦C, highly [1 0 0] oriented BST films were obtained. Many re-searchers reported that BST thin films in the polycrystalline state were obtained on the polycrystalline Pt electrode at a substrate temperature of∼500–650◦C. However, the cause of the difference in crystal structures is not clearly under-stood yet. It is speculated that these are strongly associated with the crystallinity and the orientation of the Pt electrode. Furthermore, the change of the preferred orientation from the [1 1 0] to [1 0 0] direction above 600◦C is considered to
Fig. 4. XRD patterns of Ba0.5Sr0.5TiO3 thin films deposited at various
substrate temperatures [67].
be related to the surface energy. In the perovskite structure, the (1 0 0) plane is a closely packed oxygen plane which has the lowest surface energy. Even if there is a large lat-tice mismatch, the [1 0 0] preferred orientation is strongly developed at high deposition temperatures. In general the films deposited on Si surface require sufficiently higher substrate temperature to form the crystalline phase than on Pt surface. These results reveal that the Pt surface can en-hance the nucleation of the BST film more effectively than the Si surface [105]. BST films on Pt/Ti and Pt/Ta have higher dielectric constant than that of BST films directly on Si, TiSi2, and TaSi2.
3.4. Microstructure
The dielectric property of polycrystalline BST films is af-fected not only by the composition and crystalline structure of the phase present but also by the microstructure. The di-electric film in the next generation DRAM capacitor should have an equivalent SiO2thickness (teq) of<1 nm. When the BST film with dielectric constant of ca. 300 is applied for the DRAM, the actual film thickness must be<130 nm to obtain
teq<1 nm. The grain size effect on the dielectric properties will be important for application to the DRAM capacitor be-cause the BST film has such a small thickness [13]. Notable size effects of the dielectric constant, including thickness dependence and grain size dependence have been reported in BST films. Miyasaka and Matsubara [11] have reported that the highest value of dielectric constant exhibited by a poly-crystalline (Ba0.5Sr0.5)TiO3 film with thickness of 500 nm was 900, while that of bulk ceramics is known to be >5000. They have also reported that thinner films of 80 nm thickness showed a smaller dielectric constant of ca. 400. Horikawa et al. [13] have investigated the correlation between the dielectric constant and broadness of an X-ray diffraction in (Ba0.65Sr0.35)TiO3thin films. According to their result, the polycrystalline film with grain size of 45 nm had a dielectric constant smaller than 200, while the film with grain size of 220 nm showed a dielectric constant larger than 700 (Fig. 5). Horikawa et al. [13] studied the effect of grain size on the dielectric properties (Ba0.65Sr0.35)TiO3 films deposited at substrate temperatures of 500–700◦C. The dielectric con-stant of these films ranges from 190 to 700 at room temper-ature. This value changes with the grain size rather than the film thickness. The effects of plasma bombardment on the initial growth of BST films and their properties were studied by Tsai et al. [106]. The films that were grown outside the plasma region exhibited better crystallinity, higher dielectric constants, higher electrical conductivity and rougher sur-faces than those that were grown inside the plasma region. However, plasma bombardment did not affect the initial growth of the films on Pt/SiO2/Si or MgO substrates, as ex-plored by atomic force microscopy (AFM). The films that were grown on Pt/SiO2/Si showed island growth character-istics, whereas those that were grown on MgO substrates revealed layer-by-layer growth characteristics.
Fig. 5. The dependence of the dielectric constant on the grain size from XRD for the Ba0.65Sr0.35TiO3 films deposited at the different substrate
temperatures of 500–700◦C. The substrate temperatures are 500◦C (䊏), 550◦C (䊉), 600◦C (4), 650◦C (䉱) and 700◦C (䊊) [13].
Kawahara et al. [107] observed that protrusions of BST crystallites appeared on BST film surfaces prepared by LSCVD (at 420◦C). It was considered that these protrusions (consist of cubic BST perovskite phase) appeared because the BST films deposited in the first∼150 Å layer were not sufficiently crystallized, that is, the density of nuclei in that layer was small. As the ratio (Ba+Sr)/Ti increases, the den-sity of protrusions increases with a rate of increase similar to that of the BST (1 1 0) peak intensity. The protrusions were successfully restrained by two-step deposition.
Mukhortov et al. [108] have reported heteroepitaxial growth of BST films on MgO (1 0 0) single crystals. Abe et al. [109] studied, (Ba0.24Sr0.76)TiO3 thin film epitax-ially grown on a Pt/MgO (1 0 0) substrate, where the Pt film was also epitaxially grown on the MgO as a bottom electrode. The reason for choosing the Sr-rich composition was explained as due to the closeness of the lattice constant (a=3.93 Å) of BST to that of Pt (a=3.923 Å), was expected to bring about easy epitaxial growth on Pt. However, from the surface morphology observations using scanning elec-tron microscopy (SEM) and reflected high energy elecelec-tron diffraction (RHEED), they noticed ‘stitch’ like projections, which was assumed to have probably resulted from the lattice constant inequality between (Ba0.24Sr0.76)TiO3 and Pt. Recently, Yoon et al. [110] have successfully prepared BST thin films which were epitaxially grown on Pt/MgO and YBCO/MgO substrates by means of a laser ablation technique. The thickness of their BST film was ca. 200 nm. However, anomalous elongation of the lattice constant has not been reported.
Lee et al. [111] studied the microstructure dependence of the electrical properties of BST thin films deposited on Pt/SiO2/Si using cross-sectional TEM and diffraction anal-ysis. Accordingly, BST film has a columnar structure which grows from Pt to BST surface. Also, the different layers were dense and smooth. Generally, when BST films grow with random orientation, diffraction patterns show rings. How-ever, spot patterns were observed by Lee et al. for their
BST films, which indicate that their film growth has [1 1 0] preferred orientation. Their grain size measurement by the line intercept method on the surface of the SEM micrograph demonstrated that as the film thickness increased, grain sizes increased slightly. It was observed that the dielectric constant increased from 348 to 758 when the grain size increased from 32 to 82 nm in the 600◦C deposited BST films [65]. They suggested that the abrupt decrease of dielectric con-stant in the thin film (below 75 nm) was due to another fac-tor in addition to that by a low dielectric layer which formed during the initial deposition stage. They speculated that it is strongly associated with the grain size of BST thin films
In the case of (Ba0.75Sr0.25)TiO3 and (Ba0.5Sr0.5)TiO3 films, film structure changed from granular to columnar with increase in substrate temperature and was columnar for the film deposited at 750◦C [51]. Dielectric constant correlated closely with grain size in the direction parallel to film thickness for both films. The grain size in the direction perpendicular to film thickness increases with deposition temperature as does the grain size in the direction parallel to film thickness. Therefore, it is considered that the dielec-tric constant is greatly affected by film crystallinity, grain size and the ratio of Ba/Sr composition interactively.
The properties of interfaces between electrodes and BST depend not only upon the electrode material but also on the processing, such as deposition conditions and post-annealing. The existence of an interfacial layer be-tween the BST film and the Pt bottom electrode was con-firmed by HRTEM [104]. The interfacial layer appeared to have crystallinity different from both the BST thin film and the Pt bottom electrode which resulted in variation of the interfacial states between BST and Pt. As the thickness of the BST films decreased from 300 to 50 nm, the thickness of the interfacial layer increased from 9.5 to 11 nm. The di-electric constant of the interfacial layer calculated from its measured overall capacitance and thickness, confirmed by HRTEM, was ca. 30, This low-dielectric constant interfacial layer has been shown to affect the electrical degradation of BST thin films with decreasing thickness. The role of the interface becomes increasingly dominant in the overall electrical conduction process when the film thickness is typically<100 nm.
3.5. Surface morphology
The bottom electrode materials greatly affect the electrical characteristic of BST thin films through resultant formation of the surface morphologies. Increasing the OMR during the film deposition process increases the root-mean-square (rms) surface roughness of BST films [71]. The rms surface roughnesses are 1.67, 3.199, 4.179 and 3.782 nm for 0, 25, 50 and 60% OMR BST films, respectively and the rms value decreases for BST films deposited above 60% OMR. The diffusion energy of sputtered atoms is probably reduced when OMR increases and the lateral movement on the surface also may be reduced, because the sputtered atoms
Table 5
Properties of BST deposited on the various bottom electrodes [48]a
Properties Bottom electrodes
Pt Ir IrO2/Ir Ru RuO2/Ru
Dielectric constant 219 (503) 309 (593) 234 (501) 548 (325) 322 (433)
Leakage current (10−8A cm−2) @ 100 kV cm−1 2.2 (2.5) 4.9 (2.1) 2.5 (3.3) 39.4 (2.1) 3.5 (2.4) Tangent loss 0.014 (0.015) 0.046 (0.019) 0.016 (0.02) 0.32 (0.019) 0.017 (0.012)
Work function (eV) 5.6 5.35 – 4.8 –
Breakdown field (MV cm−1) 3.84 3.68 3.49 1.94 1.84
Fatigue endurance (cycling number) >1011 >1011 >1011 >1011 >1011
Surface roughness (nm) 1.9 1.27 2.25 4.40 4.12
H2damage endurance (dielectric constant variation) −16% −12% −13% −29% −14%
Stability in O2 ambient Up to 700◦C Up to 700◦C Up to 700◦C Up to 500◦C Up to 700◦C aThe values within parenthesis, 700◦C; O
2annealing for 20 min.
collision increase with oxygen atoms and mean free path may also be shorter. Therefore, the surface roughness of the films prepared at below 50% OMR would be expected to be increased. But above 50% OMR, O2re-sputtering rate may be stronger than Ar-sputtering rate and hence the surface roughness would decrease at 60% OMR. The film deposited at 450◦C and 50% OMR exhibited good surface morphol-ogy and had dielectric constant of 375, tangent loss of 0.074 at 100 kHz, leakage current density of 7.35×10−9A cm−2 at 100 kV cm-1with a delay time of 30 s. Lee et al. [96] en-visaged similar surface morphology studies for as-deposited and annealed BST films deposited in 0 and 50% OMR. Their observations indicate that the surface roughness of the as-deposited film decreased with increasing O2/Ar ratio and the annealing resulted in a sharp increase in the roughness of the films. The dielectric constants of the film increased with increasing O2 content, whereas the leakage current density decreased. From the AFM analysis, the authors veri-fied that the leakage current characteristics of the BST films are strongly related to the surface roughness of the films.
Also, the rms value showed greater variation for BST films deposited at different bottom electrode materials [48,112]. Table 5 indicates that greater rms surface roughness of BST deposited on Ru and RuO2/Ru compared to the Pt,Ir and IrO2/Ir, which is attributed to the higher rms roughness Ru and RuO2/Ru bottom electrode itself. If the as-grown film tends to be an amorphous layer with significant surface mo-bility of adatoms, the film usually has a smooth surface. The rms surface roughness may also be affected by the num-bers of bottom stack-layers and it mostly increases with the increase in the numbers of stack layers. Tsai and Tseng [48] observed that BST films deposited on Pt, Ir and IrO2/Ir with small grain size and smooth surface roughness showed higher breakdown field, whereas the BST on Ru or RuO2/Ru with larger grain size and surface roughness exhibited lower breakdown fields.
3.6. Film thickness
The effect of film thickness on the microstructure and the associated property variation of BST thin film is
discussed in earlier sections. The details on the role of film thickness on the BST film’s electrical and dielectric param-eters are briefly presented in the following. The thickness dependence of the dielectric constant of rf-sputtered BST films varies with the substrate temperature in connection with the grain size effect [65]. Film thickness has been established to impact primarily the zero bias permittivity through a thickness dependence of the first-order coefficient of the Landau–Ginzburg–Devonshire approach [113,114]. The dependence of inverse of the zero bias capacitance density of BST thin film to its thickness is often attributed to the presence of a constant-valued capacitance density,
Ci/A, represented by the nonzero intercept, in series with the thickness-dependent capacitance density of the bulk of the film [113,114]. The constant capacitance is usually thought to represent some type of interfacial layer between the dielectric and one or both of the electrodes, and might arise from surface contamination of the BST, nucleation or reaction layers at the film/electrode interfaces, or changes in the defect chemistry at the dielectric–electrode interfaces. The apparent capacitance density at zero field may then be expressed as A Capp = A Ci + A CB = ti εiε0 + (t − ti) εBε0 (1) where A is area, Capp the apparent capacitance, Ci the in-terfacial capacitance, CB the bulk film capacitance,εB the film bulk permittivity,εi the interfacial layer permittivity,
ε0the permittivity of the free space, t the total film thick-ness and ti the interfacial layer thickness. Therefore, the nonlinear ferroelectric response is a long range coopera-tive phenomenon and the true permittivity may quite well change with film thickness.
Noh et al. [103] suggested that the observed thickness dependence of the crystallization in BST might be related to the film substrate interfacial behavior during crystalliza-tion. In thin films, the amorphous phase first transforms to the intermediate metastable phase. Since the energy barrier from the metastable phase to the perovskite phase is prob-ably higher than that from the amorphous to the perovskite phase, the crystallization temperature in the thin film is
Fig. 6. Thickness dependence of the dielectric constant for Ba0.4Sr0.6TiO3
films deposited on RuO2electrodes at 500◦C by ECR-MOCVD [88].
higher. In thick films, the amorphous phase transforms di-rectly to the perovskite phase at relatively low annealing temperature. The thickness dependence of dielectric con-stant for as-grown BST films deposited on RuO2at 500◦C was studied by Yamamichi et al. [88]. Although ther de-creases with decreasing film thickness, the value larger than 400 was obtained for 100 nm BST without post-annealing (Fig. 6). This crystallization in the as-grown states is one of the most important advantages of ECR-MOCVD, resulting in the process step reduction for capacitor fabrication.
Film thickness dependences of the leakage current den-sity at the applied voltage of 1.65 V and the SiO2equivalent thickness (teq) are shown in Fig. 7, as reported by Kuroiwa et al. [51]. The teq is given by (εSiO2/εBST)×t, where t is
Fig. 7. Thickness dependences of leakage current density at an applied voltage of V and SiO2 equivalent thickness. Ba0.5Sr0.5TiO3 and
Ba0.75Sr0.25TiO3 films were deposited at the substrate temperature of
660◦C [51].
the thickness of the BST film andεSiO2 andεBST are
rela-tive dielectric constants for SiO2and BST, respectively. The leakage current density increased considerably for the film of thickness<30 nm but no marked difference is found be-tween the (Ba0.5Sr0.5)TiO3and (Ba0.75Sr0.25)TiO3films. It is regarded that leakage current depends on film thickness rather than the difference in the target compositions. The teq is 0.35 nm for 30 nm thick (Ba0.5Sr0.5)TiO3film in compar-ison with 0.47 nm for 30 nm thick (Ba0.75Sr0.25)TiO3 film and the leakage current density is less than 1×10−7A cm−2 in both films. Similar studies by Horikawa et al. [89] showed that the dielectric constant remains ca. 320, in the thickness range of 50–90 nm and the teq decreases linearly with film thickness. At thickness of<50 nm, the dielectric constant is no longer constant but goes down to 25 in the 30 nm thick film and the minimum teq value of 0.47 nm is obtained in this film.
Paek et al. [104] observed that the leakage current of BST increases exponentially with decreasing film thickness. A leakage current of 9.8×10−8A cm−2was obtained when their BST film thickness was 300 nm. However, this in-creased rapidly to 1.06×10−7A cm−2 for the 50 nm thick BST film. The increased proportion of grain boundaries in 50 nm thick BST film was said to be the main cause of the abrupt increase in the leakage current. On the other hand, Hwang et al. [52] notified that oxide equivalent thickness does not decrease in proportion with the decreasing BST film thickness but more slowly due to the decreased dielec-tric constant of the film when they become thinner. Also they found that the dielectric constant of the BST thin film sand-wiched between two Pt electrodes decreases as the thick-ness decreases because there exists a low dielectric constant layer which is a static space charge layer, at both interfaces with the electrodes due to the difference between the work function of Pt (5.5 eV) and electron affinity of the BST (ca. 1.7 eV). The abrupt decrease in dielectric constant of the thinner BST films (below 75 nm) is attributed to another factor in addition to that by a low dielectric layer which is formed during the initial deposition stages. Many authors speculate that it is strongly associated with the grain size of BST thin films [42,111].
3.7. Electrode materials
The metallic oxides of transition metals may present a very attractive metallization option in a variety of very large scale integrated (VLSI) applications [115]. Dioxides of Ru, Ir, Os, Rh, V, Cr, Re and Nb, have bulk metallic resistivi-ties ranging from 30 to 100 cm, with IrO2being the best conductor in this group. There exist other transition metal oxides that merit attention such as ReO3 has a resistivity of 10 cm, which is lower than that of the widely used TiSi2. The heats of formation of transition metal oxides are comparable to that of transition metal nitrides [116] which emphasizes their normal stability. Ruthenium dioxide was reported to have low contact resistance on Ti metal [117]
comparable to pure ruthenium and gold. Chromium oxide, although fairly resistive has been used successfully as a dif-fusion barrier in the late seventies and recently, films of RuO2prepared by CVD were also reported to exhibit good diffusion barrier properties [118].
The electrode materials used in BST film capacitors can be classified into two general groups: the first group consists of noble metals, such as Pt, Ir and Ru [119–121], while the second group involves conducting oxides, such as RuO2, IrO2, BaRuO3, YBa2Cu3O7, SrRuO3 and (La,Sr)CoO3 [30,81,122,123]. The metal electrodes normally indicate a lower leakage current density than oxide electrodes, imply-ing that the electrical conduction mechanisms are closely related to the BST/electrode interfaces. The greater leakage current appears in oxide electrodes to be related to the lack of a potential barrier at the BST/oxide electrode interface. High work function metals such as platinum (∼5.6 eV) or iridium (∼5.3 eV) films are primarily employed as the electrode material. Pt appears to be the material of choice for use as electrodes for BST capacitors, given its excellent electrical properties. However, in practical application of Pt bottom electrodes, there are still a few drawbacks, including the formation of hillocks at higher temperatures, amiability for oxygen diffusion, poor adhesion with Si and difficulty in patterning [53].
The dielectric constant and leakage current density of BST films deposited by rf-sputtering on the various bottom elec-trode materials (Pt, Ir, IrO2/Ir, Ru and RuO2/Ru) before and after annealing in O2and N2ambient were investigated by Tsai and Tseng [48,112]. Improvement in crystallinity of BST films deposited on various bottom electrodes was ob-served with annealing. The dielectric constant of BST thin films deposited on various bottom electrode materials also increases with increasing annealing temperature. The effect of bottom electrodes is summarized in Table 5. Based on the dielectric constant, leakage current and reliability, they sug-gested that the optimum electrode material for the bottom electrode with annealing was Ir and the Ru electrode was found unstable, because inter diffusion of Ru and Ti occurs at the interface between BST and Ru after annealing.
Conducting oxides, such as RuO2 (rutile-type), are known to be easily etched in the fabrication of Gbit den-sity DRAMs [124,125] and acts as a good diffusion bar-rier against oxygen. It has also been reported that oxide electrodes greatly mitigate fatigue problems which are en-countered in ferroelectric memory capacitors. However, one serious issue related to the oxide electrode is its large leakage current. Lesaicherre et al. [125] reported a leakage current density of severalA cm−2at an applied voltage of 1.5 V from their ECR-MOCVD BST thin films which were deposited on a RuO2 electrode. The large leakage current appears to be related to the absence of a potential barrier at the BST/RuO2 interface. The phenomena of reduction and re-oxidation of ruthenium oxide during a BST deposi-tion procedure appears to be the cause of the high leakage current and large property variation of BST thin films
deposited on RuO2electrodes. Therefore, it is very impor-tant to set up the process condition to inhibit the reaction of RuO2⇔Ru+O2, especially in the case of a high vacuum process, such as sputtering, PECVD and ECR-CVD [76].
SrRuO3is known to be a conductive oxide with a pseu-docubic perovskite structure. It has metallic conduction with low resistivity (ρ<1 m cm), and has a pseudocubic lat-tice parameter of 0.393 nm which provides a suitable base for heteroepitaxial growth of BST films [126]. Abe et al. [30] and Jia et al. [127] have described the heteroepitax-ial growth of a BST films on SrRuO3/LaAlO3and SrRuO3 electrodes, respectively, and verified good electrical proper-ties. According to Abe et al. [128], their film deposited on the SrRuO3electrodes demonstrated a dielectric constant of 740 (t=42 nm) and a leakage current density <10−8A cm−2 (at 5 V). In addition, Hou et al. [129] made a Ba0.5Sr0.5TiO3 (100–200 nm)/SrRuO3/YSZ capacitor on an Si substrate us-ing 90◦ off-axis sputtering. They used Au/Ti as the top electrode.
Pt-based structures with a Si diffusion barrier layers such as Pt/TiN and Pt/Ta are also used as storage electrodes be-cause of their stability. However, difficulty in fine patterning of thick Pt will restrict its use for Gbit DRAM capacitors where the use of the side wall area of thick electrodes will be necessary to obtain a sufficient storage charge density [88,125]. The authors have proposed RuO2/TiN storage nodes for a Gbit DRAM capacitor. A thick RuO2layer can easily be patterned into a 0.15m line-and-space struc-ture by O2–Cl2plasma [88,125]. In addition, the sputtered BST/RuO2interface was shown to be stable and no hillocks were observed on the RuO2surface after BST deposition at 650◦C. Consequently, high dielectric BST thin film capac-itors with low leakage current have been obtained [130].
Grill et al. [131] and Yoshikawa et al. [132] have re-ported structural changes occurring in RuO2-based stacked structures on Si during annealing and film deposition. Even a slight degradation of the electrode/ barrier or barrier/contact/plug-interface affects the electrical proper-ties of the capacitors used for high density DRAM appli-cation. The electrical properties of thick RuO2/TiN-based storage electrode with poly-Si contact plugs for BST films have been studied by Takemura et al. [133]. Resistance of the storage electrodes including contact plugs can be evalu-ated from the dispersion observed in capacitance-frequency measurements. A Ru layer inserted at the RuO2/TiN in-terface, a TiN/TiSi2/Si junction and RTA annealing in N2 ambient of the TiN layer are effective ways to reduce the resistance of RuO2/TiN-based electrode. The barrier layer is required to prevent the electrode from being reacted with poly-Si plug. However, the oxidation of barrier during BST deposition and post-annealing imposes a serious problem on the integration because the barrier layer must remain conductive after the whole integration process.
Continued efforts on the etching of Pt recently generate a much improved storage node shape. An integrated BST capacitor for 256 Mbit, with Pt electrodes and TiSiN as
diffusion barrier, covered by SiO2spacers was recently fab-ricated by Samsung electronics [134]. Excellent diffusion barrier and oxidation resistant properties of TiSiN, further protected from being oxidized by the SiO2 spacers, make post-annealing up to 650◦C be possible. 72 fF per cell of ca-pacitance and 1.0 fA per cell at ±1.0 V of leakage current density were obtained from a capacitor having projected area of 0.3×00.8 m2 (0.58m pitch) and 200 nm with 256 M density. The capacitance is correspondent to a value of 25 fF per cell of a DRAM with 0.30m pitch which is expected to be the cell size of 1-Gbit DRAM.
An appropriately placed oxidation resistant barrier and adhesion layers enhance the thermal and physical stability of the bottom electrode structure. Khamankar et al. [135] suc-cessfully demonstrated novel BST storage capacitor node technology using Pt electrodes for Gbit DRAMs. Promising results were obtained in separate Pt etch experiments using TiAlN as a hard mask. A 40 nm TiAlN hard mask was uti-lized to etch 300 nm Pt. The absence of thick photo resist during the Pt etch and the high Pt/hard-mask etch selec-tively led to the formation of fence free bottom electrodes with a high side-wall angle (∼70◦). No elaborate post-etch clean up, regarded as a major issue with the Pt etch process was required. A capacitance of 17 fF per cell, with a leakage current density of 1.2×10−7A cm−2 at 1 V was obtained for a capacitor array with 0.5m features for 100 nm Pt bot-tom electrode. The BST with 250 nm Pt thickness showed a capacitance of ∼33 fF per cell and tan δ∼0.009. These results demonstrate the promise of integrating Pt as an electrode material with BST as the capacitor dielectric for Gbit DRAMs.
4. Conduction mechanisms
The study of carrier transport in BST films is important both from the fundamental and the practical points of view. Although the conduction mechanisms in BST films have been studied very broadly, the subject is still controversial and very often confusing. More recently, several conduc-tion mechanisms have been reported in literature to describe the nature of electrical conductivity in BST thin films and some controversies still exist regarding the major leakage mechanisms as suggested by different researchers depend-ing on the electrode materials, processdepend-ing conditions and the type of storage node structures used for the BST capacitors. Many experimental results show that thin dielectric films subjected to an external high electric field displayed a lin-ear relationship in the log10(I/V) vs. V1/2 plots, where I is the current passing through the film and V the voltage ap-plied across the film. This dependence is attributed to either the field-enhanced Schottky (SE) [136] or the Poole–Frenkel (PF) mechanism [136,137]. The former is a Schottky emis-sion process across the interface between a semiconductor (metal) and an insulating film as a result of barrier lower-ing due to the applied field and the image force. The latter
Fig. 8. Typical J–V behavior of Ba0.5Sr0.5TiO3 capacitors [139].
is associated with the field-enhanced thermal excitation of charge carriers from traps, sometimes called the ‘internal Schottky effect’. These two transport mechanisms are very similar, except that in the PF mechanism the barrier lower-ing is twice as large as in the SE mechanism due to the fact that the positively charged trap in PF mechanism is immo-bile and the interaction between the electron and the charged trap is twice as large as the image force in the SE mecha-nism. This phenomenon leads to the doubling of the slope, which is given by (q3/πε)1/2, in the log10(I/V) vs. V1/2plot.
q is the electronic charge and the dielectric constant of the
film.
Many papers have reported on the leakage properties of BST thin films with high work function metals such as Pt [14,21,28,97,138,139]. Fig. 8 shows a typical J–V behav-ior as reported by Fukuda et al. [139]. Two distinct regions are observed; in the low voltage region the current density is almost proportional to the applied voltage, while in the high voltage region it is proportional to the V1/2. It has been accepted by some researchers that the former region is at-tributed to the dielectric relaxation and the later is to the Schottky emission from the cathode [14,21,28,97,138,139]. Fukuda et al. [140] also reported that post-annealing in oxy-gen ambient is very effective in reducing the currents due to both mechanisms. Since the diffusion coefficient is propor-tional to the oxygen vacancy density in the BST, the increase in the Pt/BST Schottky barrier height by post-annealing is thought to be caused by the decrease in the oxygen vacancy density at the Pt/BST interface. In other words, the Fermi level of the BST thin film may be pinned at the interface because of the oxygen vacancies in the film [139].
It is well known that oxygen vacancies in BST films play a prominent role in leakage current of films [71,93,141]. Tsai and Tseng [141] made an attempt to correlate the electrical leakage mechanism and possible concentration variation of oxygen vacancies in the BST films deposited
![Fig. 2. Effect of several isovalent substitutions on the transition temper- temper-ature of ceramic BaTiO 3 [49].](https://thumb-ap.123doks.com/thumbv2/9libinfo/7778618.150722/4.918.184.392.746.1059/effect-isovalent-substitutions-transition-temper-temper-ceramic-batio.webp)
![Fig. 3. Effect of OMR on the dielectric constant and leakage current of the Ba 0 .5 Sr 0 .5 TiO 3 films deposited at 450 ◦ C [71].](https://thumb-ap.123doks.com/thumbv2/9libinfo/7778618.150722/7.918.535.826.103.295/fig-effect-dielectric-constant-leakage-current-films-deposited.webp)
![Fig. 8. Typical J–V behavior of Ba 0 .5 Sr 0 .5 TiO 3 capacitors [139].](https://thumb-ap.123doks.com/thumbv2/9libinfo/7778618.150722/14.918.524.833.101.387/fig-typical-j-behavior-ba-sr-tio-capacitors.webp)
