Reliability of key technologies in 3D integration

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a r t i c l e

i n f o

Article history: Received 27 May 2012

Received in revised form 5 August 2012 Accepted 12 August 2012

Available online 5 September 2012

a b s t r a c t

3D IC packaging offers miniaturization, high performance, low power dissipation, high density and het-erogeneous integration. Through-silicon via (TSV) and bonding technologies are the key technologies of 3D IC, and the corresponding reliability has to be well evaluated and qualiﬁed before real production applications. This paper reviews the emerging 3D interconnection technologies in worldwide 3D integra-tion platforms with the latest reliability assessment results, including the reliability demonstraintegra-tion of Cu and oxide hybrid bonding in Ziptronix’s platform, micro-bump and adhesive hybrid bonding in ITRI’s platform, adhesive bonding followed by TSV formation in WOW alliance’s platform, wide I/O interface TSV interposer in Xilinx’s platform, and the active and passive TSV interposer in Samsung, TSMC and ASE’s platforms. With low temperature bonding and TSV processes, optimized design and material selec-tion to lower the induced stress and warpage, these platforms are successfully developed with enhanced reliability. The reliability of key technologies in 3D integration with these representative platforms are summarized in the paper to address the feasibility of 3D IC in mass production, which could be the guide-lines for future development and applications of 3D integration technology.

1. Introduction

Three-dimensional integrated circuits (3D ICs) has emerged as a promising solution beyond Moore’s law to achieve system level integration with high function density, high performance, small form factor, and low power consumption. Various 3D integration platforms have been developed to realize with TSV and chip/wafer stacked bonding technologies [1–9]. Although each integration platform has innovations and benefits, cost and reliability are al-ways the major concerns for considering as the real product appli-cations. For instance, bonding interfaces are susceptible to failure due to structure and process induced stress. Crack or fatigue failure could be resulted from the CTE (Coefficient of Thermal Expansion) mismatch between Si and TSV. In addition, the thermal issue in 3D stacking structure, and the electro-migration issue in the ul-tra-fine electrical path are both the tough reliability problems in 3D IC. In this paper, the emerging 3D interconnection technologies in worldwide 3D integration platforms are studied with the reliabil-ity assessment demonstration, including the reliabilreliabil-ity of Cu and oxide hybrid bonding in Ziptronix’s platform[10–14], micro-bump and adhesive hybrid bonding in ITRI’s platform[15–17], adhesive bonding followed by TSV formation in WOW (Wafer-on-Wafer) alliance’s platform[18–22], wide I/O interface TSV interposer in Xi-linx’s platform[23–26], and the active and passive TSV interposer in

Samsung Electronics[27–29], TSMC[24,30]and ASE’s[30–32] plat-forms. These 3D integration platforms could be the guidelines for future development and applications of 3D integration technology.

2. Reliability of Cu and oxide hybrid bonding

Ziptronix reported the copper and silicon oxide DBI (Direct Bonding Interconnect) hybrid bonding technology[10–14]. It uti-lizes the standard damascene processes to build the hybrid surface with exposed copper CMP (Chemical Mechanical Polishing) planar or dished topography about 2 nm below silicon oxide layer. TiW diffusion barrier liner is included in via and trench for reliability enhancement.Fig. 1shows the process ﬂow of DBI bonding tech-nology [12]. By activating and terminating the CMP planarized oxide surface, the bonds can be formed at signiﬁcantly low temper-ature, which enables the room-temperature direct oxide bonding with preserved alignment accuracy since no external heat and pressure applied. After bonding, 300–350 °C annealing is employed to improve the inter-wafer bond strength and the Cu–Cu contact quality. The fully functional serial daisy chains with 72500 and 463000 3D copper DBI interconnects on a 25

l

m pitch with 125 °C heat treatment and 10

l

m pitch with a 350 °C heat treat-ment were achieved, respectively [12]. Fig. 2 demonstrates the 10

l

m pitch bonded structure using 4

l

m size Cu DBI plugs and a TiW barrier liner[12]. The corresponding DBI contact resistance was about 50 mX and resistivity was achieved less than 0.45X

l

m2_{, respectively} _[12]_{. These parts passed the JEDEC}

⇑ Corresponding author.

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temperature cycling ( 65 °C to 175 °C, 1000 cycles) and HAST (Highly Accelerated Stress Test) (130 °C, 85% RH, 333 psi)

reliabil-ity assessment asTable 1 presents[13]. No failures were found as deﬁned by a signiﬁcant change in resistance of the daisy chain. With increasing the temperature cycling by 10 times to 10,000 cy-cles and HAST by 3 times to 288 h, no failures were detected. In addition, the electro-migration resistance of DBI connections was evaluated with a daisy chain (1 mm of total length and 8

l

m of width) at a current density of 3 106A/cm2 for 100 h, showing no failures or signiﬁcant change in resistance[13].

3. Reliability of micro-bump and adhesive hybrid bonding ITRI has developed various micro-bump and assembly technolo-gies for 3D IC applications[33–37], including Cu/Ni/Sn2.5Ag by con-ventional reflow process, Cu/Ni/Sn2.5Ag by thermo-compressive bonding (TCB), and Cu/Sn by solid liquid interdiffusion (SLID) bond-ing.Fig. 3a shows one example of the bonding schemes for investi-gation, and the micro-joint interconnects were subjected to reliability test for assessment and comparison[33].Fig. 3b shows the Weibull analysis results of the three kinds of micro-joints for thermal cycle test[37]. The ranking of characteristic life (the inter-section with the dotted line located on 63.2% in theFig. 3b) is Cu/Ni/ Sn2.5Ag (TCB) with 4980 cycles > Cu/Sn (SLID) with 3262 cycles > -Cu/Ni/Sn2.5Ag (Reflow) with less than 1000 cycles. The micro-joint bonded by conventional reflow is not reliable enough due to the short lifetime. Although the average lifetime of the Cu/Sn interme-tallic micro-joint is inferior to that of Cu/Ni/Sn2.5Ag micro-joint by TCB, the first failure of the former occurred when 1000 cycles passed. Compared to that of the latter of 200 cycles, Cu/Sn SLID bonding seems to be more beneficial to lead in the mass production to prevent the early failure of products[33,37]. The failure of Cu/Sn SLID bonding micro-joint was induced by the volume change re-sulted from the phase transformation as theFig. 4presents[37]. The intermetallic micro-joints formed by SLID bonding has a charac-teristic life of more than 3000 cycles under TCT because of a slight volume contraction (0.59%) elicited by the reaction 2Cu3Sn +

3Sn ? Cu6Sn5.

Fig. 1. The process ﬂow of DBI bonding technology[12].

Fig. 2. 10lm pitch direct bond interconnects from Ziptronix DBI technology[12].

Table 1

Ziptronix DBI interconnect reliability data[13].

Test part 50lm pitch 25lm pitch 10lm pitch Test part 9,950 Serial

connections 72,500 Serial connections 460,000 Serial connections Typical resistivity <20 mX(<1.5X/ lm2 ) <50 mX (<0.5X/lm2 ) <50 mX (<0.5X/lm2 ) Thermal cycling 65 °C to 175 °C 1000 cycles, 18/18 pass 10,000 cycles, 9/9 pass 1000 cycles, 5/5 pass 10,000 cycles, 4/4 pass 1000 cycles, 10/10 pass Hast (130 °C, 85% RH, 333 psi) 96 h, 12/12 pass 288 h, 6/6 pass

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ITRI and NCTU reported a wafer-level carrier-less 3D integration platform using high reliable Cu/Sn micro-bump and Benezocyclob-utene (BCB) adhesive hybrid bonding technology[15–17].Fig. 5 shows the structure design and schematic process flow[16]. Cu/ Sn micro-bumps are fabricated on bottom wafer and Cu TSVs of top wafer, respectively. Photo-definable BCB is subsequently spin-coated and lithographed to form the hybrid scheme before hybrid bonding at 250 °C. Cu/Sn micro-bump and BCB adhesive are adopted for low temperature hybrid bonding to achieve metal-lic interconnection with adhesive sealing around to enhance the reliability of the micro-joints, and serving reinforcement of the mechanical stability to stand the severe wafer thinning and back-side processes. There is no carrier and thin wafer handling tech-nique required in the 3D integration platform. Therefore, it is beneficial to simplify the process flow, decrease the production cost, and enhance the reliability of the stacked devices.Fig. 6

dem-onstrates the completed 3D integration scheme with Cu/Sn and BCB excellent hybrid bonding integrity. Herein 5

l

m TSVs and 10

l

m micro-bumps in 20

l

m pitch were applied for 3D intercon-nection. The scheme was investigated after multiple current stress-ing and humidity test for reliability assessment[16].

Fig. 7shows the characteristics of voltage and current on single 5

l

m Cu TSV and 10

l

m Cu/Sn micro-joint under multiple current stressing[16]. There is no apparent change between the character-istic curves, which implies the integration scheme has excellent electrical performance and stability even after 1000 cycles current stressing. The via chain samples were subjected to 1000 cycles of current stressing and humidity test under 45 °C, 100% humidity and 2 h conditions, and the results show excellent stability as well and passed both tests. The micro-joints are well protected from atmosphere with BCB perfect sealing performance. The assessment results indicate the 3D integration scheme possesses excellent Fig. 3. (a) One example of the micro-bump bonding scheme for investigation, and (b) the Weibull analysis results of the three kinds of micro-joints conducted to TC test [33,37].

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reliability and electrical stability, and is potentially to be applied for the 3D IC applications[16].

4. Reliability of adhesive bonding with TSV formation

WOW (Wafer-on-Wafer) alliance reported using BCB adhesive bonding followed by low temperature TSV fabrication approach for 3D integration [18–22]. Fig. 8 shows the process ﬂow of WOW stacking method[19]. The secondary wafer (Si 2) with tran-sistors and interconnect metallization is temporarily bonded with support glass before thinning down to less than 20

l

m. This wafer is then permanently bonded to the primary wafer (Si 1) with BCB adhesive. After removing the support glass from the wafer stack, TSV and RDL are subsequently fabricated by Cu dual-damascene Fig. 4. (a) Cross-sectional image of the failed Cu/Sn SLID micro-joint, and (b) FIB

analysis of the SLID micro-joint after TCT for 2650 cycles[37].

Fig. 5. The structure design and schematic process ﬂow of ITRI’s 3D integration platform[16].

Fig. 6. The demonstration of the completed 3D integration scheme with Cu/Sn and BCB excellent hybrid bonding integrity[16].

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processes[19].Fig. 9shows the FIB–SEM (Focused Ion Beam Scan-ning Electron Microscope) image of stacked wafers and multiple TSV on BEOL device[21]. Herein 150 °C low temperature TSV pro-cess was applied to reduce the pumping stress on Cu TSV for reli-ability enhancement.

Fig. 10shows the calculation results of the pumping height in TSV with varied thermal stress[21]. The pumping stress induced by CTE mismatch at the dielectric film in TSV decreases with re-duced via size and process temperature. Cu diffusion profile in the dielectric layers was analyzed by BS-SIMS after annealing at 400 °C, 10 h for thermal aging [21]. As the results shown in Fig. 11 [20], Cu diffusion increased with decreasing deposition temperature, but the SiON film deposited by PECVD at the low temperature of 150 °C was sufficient to be a barrier layer against Cu diffusion in TSV. Cu diffusion rate is evaluated as a function of film density relative to the value of bulk Si3N4and SiO2calculated

using Cu depth profiles. The rate becomes higher in lower density film formed at lower deposition temperature. In case of density be-low 50%, the dielectric layer thicker than 1000 nm is recommended to suppress the Cu diffusion into Si substrate[20]. Thermal stress test evaluation using Cu TSV and BEOL chain contact was carried out with 55 °C to 125 °C temperature cycling. As the results shown inTable 2 [21], there was no open failure and significant resistance change in the Cu interconnects with TSV process after 1000 cycles of TC testing by using 150 °C LT-PECVD (Low-Temper-ature Plasma Enhanced Chemical Vapor Deposition) dielectric film. The LT-TSV (Low Temperature Through-Silicon via) process can lower the overall process temperature and induced stress, and is suitable to be applied for high reliable TSV structure for the wa-fer-level 3D stacking[21].

Fig. 8. The process ﬂow of WOW stacking method[19]. Cu/Sn micro-joint under multiple current stressing[16].

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5. Reliability of TSV interposer

The conventional ﬂip chip packaging with the organic IC sub-strate is facing great challenge in ultra ﬁne pitch wiring fabrication as the interconnect density becomes higher and higher. TSV inter-poser has emerged as a promising solution to provide high wiring density interconnects, improve electrical performance, and mini-mize CTE mismatch between the Cu/low-k die and the TSV inter-poser for reliability enhancement. Xilinx has reported the development of wide I/O interface TSV interposer technology for a 4-slice high performance 28 nm FPGA (Field Programmable Gate Array) dies mounted on a large TSV interposer (manufactured by TSMC)[23–26].Fig. 12a and b shows respectively the schematic

ing or after 264 h of HAST at 110 °C. All the samples passed 1000 cycles of TCB without Cu protrusion of TSV, as one SEM image shown inFig. 13. It is suggested that this developed TSV interposer is a desirable 3D path to have a reliable package for high density interconnection, and has been proven in high-volume production [25].

The worldwide leading manufacturers, such as Samsung Elec-tronics[27–29], TSMC [24,30]and ASE[30–32], have worked in the development of TSV interposer technology.Table 5 summa-rizes and compares their technology platforms. Samsung focuses on the ﬁeld of wide I/O memory and wide I/O DRAM application, therefore the active interposer is fabricated by forming TSVs on CPU or Logic devices. Lots of reliability issues are concerned as forming TSVs on active devices, because TSV stress (due to CTE mismatch between Cu (17 ppm) and Si (3 ppm)) and Cu con-tamination (due to Cu diffusion) may damage the CMOS layer, and TSV stress induced Cu extrusion may cause the low-k IMD (In-ter-Metal Dielectric) crack or interface delamination happened [27,29]. Samsung has reported the less stress induced by the smal-ler TSV size. As the results shown inFig. 14, TC 1000 cycles could be passed without IMD crack or interface delamination as the Cu extrusion height was controlled less than 0.2

l

m [29]. Table 6 shows the TSV proximity impacts on 45 nm CMOS devices[27]. Impact on TSV was observed in less than 2

l

m distance only, and the amount of changes caused by TSV is very small (2% in maxi-mum). Long channel looks more sensitive than short channel, and NMOS looks more sensitive than PMOS. In addition, no signif-icant impact was found in thin_short_NFET and off-current. Regardless of the TSV positions, Idsatis decreased for NFET and

in-creased for PFET by TSV.

TSMC and ASE have developed 2.5D and 3D IC technologies with passive interposer, which eliminates above issues because TSVs are formed on passive device. TSMC has developed 2.5D interposer for Xilinx for wide I/O interface application [24]. As aforementioned, the developed TSV interposer shows excellent reliability. In March 2012, Altera and TSMC announced to devel-op the world’s first heterogeneous 3D IC test vehicle using TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) integration process [30], an integrated technology that attaches devices to a wafer through the chip on wafer (CoW) bonding process, following by attaching CoW chip to the substrate to form the final compo-nent. By attaching the device to the original thick wafer before the fabrication process, manufacturing-induced warpage could be avoided. TSMC plans to offer CoWoS as a turnkey manufac-turing service. ASE developed TSV structure with polymer isola-tion for 2.5D silicon interposer, which shows the features of low temperature fabrication process, low warpage, and low leakage with minimized TSV parasitic parameters [30–32]. Fig. 15 pre-sents the 2.5D Si interposer assembly process flow and package prototype [32]. Herein the simplified direct reflow flip chip assembly process is adopted to minimize the cost. The interposer Fig. 11. SIMS depth profile of Cu diffusion in SiON barrier layer of TSV[20].

Table 2

Resistance change of Cu-TSV and BEOL interconnects after TC testing[21]. Before TSV process After TSV process After TC 1000 cycle 0.4lm dense chain (X) 1.04E + 05 1.00E + 05 1.01E + 05 3lm single line (X) 10.02 10.04 9.97

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has been assessed and passed MSL3/260 °C precondition, fol-lowed by TCT condition-B 3000 cycles and HAST 504 h without failures.

6. Conclusions

The emerging 3D interconnection technologies in various 3D integration platforms are reviewed in the paper with the latest reli-ability assessment results, including the relireli-ability demonstration of Cu and oxide hybrid bonding in Ziptronix’s platform, micro-bump and adhesive hybrid bonding in ITRI’s platform, adhesive bonding followed by TSV formation in WOW alliance’s platform, wide I/O interface TSV interposer in Xilinx’s platform, and the ac-tive and passive TSV interposer in Samsung, TSMC and ASE’s plat-forms. Ziptronix activates the CMP planarized oxide surface to perform bonding at room-temperature and followed by annealing to improve the bond strength and Cu–Cu contact quality, and this scheme passes the TCT, HAST and electro-migration reliability test. ITRI adopts high reliable Cu/Sn SLID and BCB hybrid bonding at low temperature to perform carrier-less 3D integration platform, and this scheme passes multiple current stressing and humidity test assessment. WOW alliance develops 150 °C LT-TSV process with qualiﬁed LT-PECVD dielectric ﬁlm to reduce the pumping stress on Cu TSV, which enhances the reliability. Xilinx develops wide I/ O interface TSV interposer with several DOEs performed to opti-mize design and material selection for yield and reliability enhancement, and this scheme passes the HAST and TCB tests. The interposer technologies developed by Samsung, TSMC and Table 3

Summary of solder fatigue study in Xilinx TSV interposer[25]. After x cycles @

125 °C

After x cycles @ 55 °C lbump solder inelastic

strains

0.12 0.38

lbump solder inelastic energy

2.52 2.93

C4 solder inelastic strains 0.08 0.17

Table 4

TSV stresses in silicon interposer during 55 °C to 125 °C cycling[25]. Max in-plane stress (MPa) Max shear stress (MPa) Max out-of-plane stress (MPa) Si 127.5 4.28 82.10 SiO2 120.3 16.47 77.06 Cu-TSV 146.3 21.75 111.3

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ASE were introduced and compared as well. Samsung studies the impact influence of TSV induced stress and successfully develops the active interposer with well design of TSV size and position. TSMC and ASE develop 2.5D and 3D IC technologies with passive interposer with simplified process flow and low warpage to reduce cost and enhance reliability. The assessment results indicate that all of these emerging 3D interconnection technologies possess excellent reliability, and show the potential to be applied for 3D integration in real product applications. These 3D integration plat-forms could be the guidelines for future development and applica-tions of 3D integration technology.

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