430 IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO. 6, JUNE 2004
A Novel 25-nm Modified Schottky-Barrier
FinFET With High Performance
Bing-Yue Tsui, Senior Member, IEEE, and Chia-Pin Lin, Student Member, IEEE
Abstract—High-performance modified Schottky barrier (MSB)
FinFET with 25-nm channel length and fully silicided source/drain (S/D) is proposed for the first time. Using an implant-to-silicide technique, an ultrashort and defect-free S/D extension can be formed at temperature as low as 600 C. The MSB FinFET exhibits better current–voltage characteristics than those of pub-lished Schottky barrier devices and FinFETs. With 4-nm-thick gate oxide, the on o current ratio higher than109is achieved. The subthreshold swing of 25-nm and 49-nm MSB FinFETs is 83 and 64.5 mV/dec at room temperature. The advantage of low thermal budget relaxes the thermal stability issue for metal gate/high- dielectric integration. It is believed that the proposed MSB FinFET would be a very promising nano device.
Index Terms—FinFET, Schottky barrier, silicon-on-insulator
(SOI).
I. INTRODUCTION
S
CHOTTKY-BARRIER (SB) source/drain (S/D) sil-icon-on-insulator (SOI) MOSFETs have been proposed for future nanoscale devices because of easy process and small external resistance of S/D [1]–[5]. However, the SB MOSFETs still have some drawbacks. The first drawback is the smaller on-state driving current than that of the conventional pn junction MOSFETs due to the Schottky barrier between the silicide and the inverted channel. In the previous study, a method of using complementary low-barrier silicide : PtSi for pMOS and ErSi for nMOS, has been suggested to reduce this barrier [2], [3]. The problem of high of SB-SOI MOSFETs comes from the thermionic emission at the drain contact has been confirmed [6]. Kedzierski et al. introduced the FinFET architecture on SOI and demonstrated low A/ m for 20 25 nm devices [7]. Adding a metal field-plate over the MOSFETs has been shown to be effective in reducing the by suppressing back-injection from the drain contact, but it requires an additional voltage supply and sacrifices device density [8].In this letter, to overcome the drawbacks of SB MOSFETs while keeping the effect of Schottky contact on the low S/D external resistance and the low temperature process, we pro-pose a modified SB FinFET (MSB FinFET) with ultrashort
Manuscript received February 17, 2004; revised March 25, 2004. This work was supported by the National Science Council of Taiwan, R.O.C., under Con-tract NSC-91-2215-E-009-018. The review of this letter was arranged by Editor B. Yu.
B.-Y. Tsui is with the Department of Electronics Engineering and Institute of Electronics, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C., and also with the National Nano Device Laboratories, Hsinchu 300, Taiwan, R.O.C. (e-mail: [email protected])
C.-P. Lin is with the Department of Electronics Engineering and Institute of Electronics, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C.
Digital Object Identifier 10.1109/LED.2004.828980
S/D extension (SDE) at the interface of silicide and inverted channel. Adding an extension doping in the silicon drastically improves Schottky limit for by thinning and reducing the SB at the source/body junction at on-state. The proposed MSB devices also show significant lower than the conventional SB devices because of the high and wide Schottky-barrier at drain/body junction at off-state. Therefore, it is demonstrated that the driving current of the proposed MSB FinFET can be higher than 250 A/ m (or 750 A/ m dependsing on the definition of the channel width) and the current ratio can be higher than .
II. DEVICEFABRICATION
Fig. 1 shows the main fabrication process flow of the pro-posed MSB FinFET. The starting material was boron-doped 6-in SOI wafers with background doping of around cm . The nominal Si layer and buried oxide layer thickness were 40 and 150 nm. The device island (including S/D region and Si fins) was defined by electron-beam (e-beam) lithography and plasma etching. A 4-nm-thick SiO was thermally grown as gate dielec-tric. Poly-Si film of 150 nm thick was deposited and doped by ion implantation at 40 KeV to a dose of cm . After a rapid thermal activation at 1025 C, 50-nm-thick TEOS oxide was deposited with low-pressure chemical vapor deposi-tion (LPCVD) as hard mask. E-beam lithography was employed again to define gate pattern as shown in Fig. 1(a). Following gate patterning, a SiO (10 nm)/Si N (30 nm) composite spacer was formed and is shown in Fig. 1(b). The hardmask on poly-Si was etched away during spacer etching. Ni film of 22 nm thick was then deposited in a sputtering system. To convert Si layer at S/D region into silicide completely with suitable lateral growth, a two-step annealing process was performed. At first, the wafer deposited with Ni was annealed in vacuum chamber at 300 C for 80 min. After the unreacted Ni was selectively removed by wet chemical etching with H SO /H O solution, the wafer was annealed in N ambient at 600 C for 30 s [Fig. 1(c)]. Ni-silicide was formed on poly-Si gate simultaneously. BF2 ions were implanted to silicide (ITS) at 30 KeV to a dose of cm followed by a furnace annealing at 600 C for 30 min. Monte Carlo simulation shows that the ions straggle distribution is only 8 nm, which is shorter than the lateral growth of silicide [9]. Because of the low solid-state solubility of boron in Ni silicide, boron atoms diffused out and piled up at the Si–silicide interface to form an ultrashort SDE as shown in Fig. 1(d). It has been reported that ITS process forms a modified Schottky junction with characteristics between pn junction and Schottky junction [10], [11]. Since the ion implantation process does not damage
TSUI AND LIN: NOVEL 25-nm MODIFIED SCHOTTKY-BARRIER FinFET WITH HIGH PERFORMANCE 431
Fig. 1. Main process flow of the modified Schottky barrier FinFET.
Si layer directly, the junction would be free of crystalline defects and low junction leakage current could be expected [12]. Typ-ical inter layer dielectric deposition, contact hole patterning, and Al metallization completed the fabrication process. For compar-ison, simple SB FinFETs were fabricated with the same process but neglecting the ITS process step.
Fig. 2 shows the schematically layout and transmission elec-tron microscopy (TEM) micrograph of the MSB FinFET in the A-A’ direction with gate length of 25 nm, fin thickness of 40 nm, and fin height of 40 nm. The fin thickness represents the fin width perpendicular to A-A’ in Fig. 2(a). Fully silicided S/D and free crystalline defects are confirmed.
III. RESULTS ANDDISCUSSION
Fig. 3 shows the output characteristic of the MSB FinFET
with nm, fin thickness nm, and fin
height nm. It is known that for conventional SB devices,“sublinear”phenomenon is pronounced at linear region due to the Schottky barrier and the channel-S/D offset. For our SB FinFET, the large offset should be the dominant mechanism although the effect of Schottky barrier cannot be ignored. For the MSB FinFET, the ultrashort SDE bridges channel and S/D sili-cide. Furthermore, the Schottky barrier thickness, i.e., the car-rier injection resistance from source to channel, is reduced by the high concentration ultrashort SDE. Therefore, the sublinear phenomenon is not observed. The driving current of the 25 nm MSB FinFET at V is about 250 A/ m under the
def-Fig. 2. (a) Schematically layout and (b) TEM micrograph of the MSB FinFET withL = 25 nm, W = 40 nm and T = 40 nm.
Fig. 3. Output characteristic of the MSB FinFET withL = 25 nm, W = 40 nm and T = 40 nm.
Fig. 4. Subthreshold characteristics of MSB and SB FinFETs withL = 25 nm, W = 40 nm and T = 40 nm.
inition of channel width or 750 uA/um under the definition of channel width . It should be noted that the could be further improved by shorter spacer length and thinner gate-oxide thickness.
Fig. 4 compares the transfer characteristics of the MSB FinFET and the SB FinFET. In the case of SB FinFET, a typical ambipolar operation is observed. For p-channel operation, the SB FinFET has poor subthreshold swing and current ratio of lower than . The small current ratio is attributed to the high Schottky barrier at on-state and low Schottky barrier at off-state. By inserting a ultrashort SDE to
432 IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO. 6, JUNE 2004
modify the Schottky barrier property, the MSB FinFET can be turned on more steeply and had extremely high
current ratio . The 25-nm MSB FinFET also shows superior subthreshold characteristics with swing of 83 mV/dec and drain-induced barrier lowering (DIBL) of 235 mV/V. The low ( mV) comes from the p poly gate; it could be adjusted using a mid-gap gate material such as p SiGe or Ta–Pt alloy, etc [13], [14]. For thinner gate oxide and smaller fin height/channel length ratio, better short channel characteristics could be expected [8]. In fact, subthreshold swing of 64.5 mV/dec and DIBL of 39 mV/V are obtained at nm. These results are better than those reported conventional FinFETs and SB FinFETs.
IV. CONCLUSION
High-performance MSB FinFETs with several unique fea-tures such as fully silicided S/D, ultrashort SDE, defect-free S/D junction, and low-temperature process is proposed. This device exhibits better current–voltage characteristics than those of published SB devices and FinFETs. With 4-nm-thick gate oxide, the current ratio higher than is achieved. The subthreshold swing of 25 and 49 nm MSB FinFETs is 83 and 64.5 mV/dec at room temperature, respectively. These values are close to the theoretical limitation. The of the 25-nm MSB FinFET is higher than 250 or 750 A/ m, which depends on the definition of channel width. It is expected that the device charac-teristics can be further improved by thinner gate-oxide thickness and shorter spacer length.
The low-temperature process of MSB FinFET is an impor-tant advantage. Beyond 65-nm technology node, it is predicted that metal gate and high dielectric constant gate dielectric, must be employed to improved device performance continuously. Thermal stability between metal gate and a high- dielectric is a critical issue because the conventional S/D process acquires a high temperature annealing at least 900 . On the contrary, the process temperature of MSB process is around 600 C. The thermal stability issue is relaxed and the interfacial layer formation at high- dielectric and Si interface is also reduced. Furthermore, the ultrashort SDE also helps device scale down.
ACKNOWLEDGMENT
The authors would like to thank the National Nano Device Laboratory staff for their support in device fabrication.
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