Current-mode design techniques in low-voltage 24-GHz RF CMOS receiver front-end

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Current-mode design techniques in low-voltage 24-GHz RF

CMOS receiver front-end

Chung-Yu WuÆ Wen-Chieh Wang Æ Fadi R. ShahrouryÆ Zue-Der Huang Æ Hao-Jie Zhan

Received: 1 August 2007 / Revised: 18 December 2007 / Accepted: 20 December 2007 / Published online: 19 January 2008 Ó Springer Science+Business Media, LLC 2008

Abstract A new high frequency CMOS current-mode receiver front-end composed of a current-mode low noise amplifier (LNA) and a current-mode down-conversion mixer has been proposed in the frequency band of 24 GHz and fabricated in 0.13-lm 1P8M CMOS technology. The measurement of the current-mode receiver front-end exhibits a conversion gain of 11.3 dB, a noise figure (NF) of 14.2 dB, the input-referred 1-dB compression point

ðP1 dBÞ of -13.5 dBm and the input-referred third-order

intercept point (PIIP3) of -1 dBm. The receiver dissipates 27.8 mW where the supply of LNA is 0.8 V and the supply of mixer is 1.2 V. The power consumption of output buffer is not included. The receiver front-end occupies the active area of 1:45 0:72 mm2 including testing pads. The measured results show that the proposed current-mode approach can be applied to a high-frequency receiver front-end and is capable of low-voltage applications in the advanced CMOS technologies.

Keywords 24-GHz  CMOS  Current-mode  Receiver front-end

1 Introduction

Over the last two decades, the frequency spectra below 10 GHz have gradually become crowded because of mas-sive requirements of data transmission from the modern wireless applications such as Bluetooth, wireless local area network (WLAN) and ultra-wideband (UWB), etc. Con-sequently, many researchers start to investigate RF transceiver front-end circuits in much higher frequency bands like 24 and 60 GHz for example because higher operating frequency can provide more bandwidth. In addition to the original industrial-science-medical (ISM) band within 24–24.25 GHz, the FCC has opened the 22–29-GHz frequency band in 2002 for short-range auto-motive radar systems, autonomous cruise control (ACC) for example [1]. In the 24-GHz frequency range, some applications such as radars, wireless local area networks, point-to-point wireless communications, local multipoint distribution services (LMDS) and other ISM band appli-cations are implemented by CMOS, SiGe BiCMOS and III-V compound semiconductor [2–6].

Table 1shows the pros and cons of different technolo-gies which are used for the implementation of 24-GHz systems. Although III–V compound semiconductor and SiGe BiCMOS have good performance in higher frequency RF circuits, the cost of these technologies is relatively higher than CMOS technologies. In addition, these tech-nologies suffer from the difficulties to integrate with complex digital systems which are usually realized by CMOS technologies for low cost and low power. With the fast advancement of CMOS technologies, the nanometer CMOS technologies have already become a candidate to realize 24-GHz or even 60-GHz RF systems. Conse-quently, nanometer CMOS technologies are recommended to realize 24-GHz systems because of their advantages of C.-Y. Wu (&)  W.-C. Wang  F. R. Shahroury 

Z.-D. Huang H.-J. Zhan

Nanoelectronics and Gigascale Systems Laboratory, Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan e-mail: cywu@alab.ee.nctu.edu.tw W.-C. Wang e-mail: wangste@ieee.org F. R. Shahroury e-mail: fadirs@gmail.com Z.-D. Huang e-mail: zuederhu@gmail.com DOI 10.1007/s10470-007-9130-0

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higher integration level, smaller chip area, lower power consumption and lower cost.

As the CMOS technology is scaled down to nanometer nodes, the supply voltage is gradually reduced to around or even below 1 V. The lower the supply voltage, the smaller the voltage headroom is left in the design of CMOS RF circuits. In voltage-mode circuits, the impedances of inter-nal nodes are usually large so that the siginter-nal information can be mostly carried with the time-varying voltage signals. Since large enough voltage swing is required to keep signal information, it is difficult for voltage-mode circuits to use reduced voltage headroom under low supply voltage.

In current-mode circuits, however, the impedances of internal nodes are smaller than those in voltage-mode cir-cuits and voltage swings at internal nodes become smaller. But the signal information is mainly carried with the time-varying current signals. Consequently, current-mode circuits can be designed under small voltage headroom. Furthermore, when dealing with signal processing, it is easy to perform the function of summation by simply connecting the signal paths together without additional amplifiers. Thus power consumption can be further reduced. With the above advantages, current-mode RF circuits are capable of operating in low supply voltage and dissipating smaller power. The current-mode design tech-niques can have great potential in the design of CMOS RF front-end in the advanced nanometer CMOS technologies. Two current-mode CMOS RF front-end circuits have been published by the present authors [7, 8]. A 24-GHz current-mode power amplifier (PA) was designed in 0.13-lm bulk CMOS technology [7]. This CMOS current-mode PA can achieve large output power with high power added efficiency (PAE) in the 24-GHz frequency range. The proposed PA is capable of operating in the low supply voltage of 1.2 V. In [8], a 24-GHz transmitter using cur-rent-mode approach in 0.13-lm CMOS technology is proposed. The transmitter is operated in low supply voltage of 1 V, and it consumes very small power. So far, no current-mode CMOS receiver circuit is proposed.

The first 24-GHz receiver front-end using current-mode design techniques in 130-nm CMOS technology is

proposed, analyzed, and measured. The proposed current-mode receiver front-end is of single-balance structure and integrated with a current-mode LNA and a current-mode down-conversion mixer. In the proposed current-mode LNA, two cascaded current-mirror amplifiers are adopted to realize the amplification of current signals. Following the LNA is the current summing circuit to perform the summation of RF and LO signals. The summed signal is sent to the current squaring circuit to perform the function of current mixing of RF and LO signals. The measurement results have shown that the proposed current-mode CMOS receiver achieves the conversion gain of 11.3 dB, the P1 dB

of -13.5 dBm, and the PIIP3 of -1 dBm. The measured

total NF is 14.2 dB at RF frequency of 24 GHz and LO frequency of 19 GHz. The current-mode receiver front-end dissipates 27.8 mW under the condition that the supply of the LNA is 0.8 V and the supply of the mixer is 1.2 V. Compared to other implementations for 24-GHz receiver front-ends in [2] and [5], the proposed 24-GHz current-mode receiver front-end has the advantage of low-voltage operation and low-power dissipation with comparable performances.

In Sect.2, the architecture, operational principles, and circuit realizations of CMOS current-mode RF receiver front-end are described. The experimental chip is designed and fabricated in 130-nm 1P8M CMOS technology. The measurement results are presented in Sect.3 to verify the circuit performances. Finally, the conclusion is given in Sect.4.

2 Operational principles and circuit realizations

The block diagram of the designed 24-GHz receiver front-end is shown in Fig.1. It is composed of a LNA and a mixer. The off-chip signal generator provides the local oscillator (LO) signal for the receiver. With the LO signal at 19 GHz, the received RF signal at 24 GHz is Table 1 The pros and cons of different technologies

GaAs BiCMOS CMOS

gm High High Low

fT High Moderate Moderate

RF performance High High Moderate

Yield Low Moderate High

Integration Low Moderate High

Cost High Moderate Low

Technology improvement Slow Moderate Fast

LNA RF (24 GHz) LO (19 GHz) IF (5 GHz) Mixer LNA i LO i IF i RF i

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down-converted to the intermediate frequency (IF) which is at the frequency band of 5 GHz by the Mixer. The IF is chosen at 5 GHz so that the mature RF receiver front-end circuits at 5 GHz can be adopted to realize the second-step down-conversion from the IF to the baseband.

In the design of CMOS LNA, the CMOS current-mirror structure is adopted as the current amplifier and two stages of current-mirror amplifiers are cascaded to provide suffi-cient gain. As for the current-mode down-conversion mixer, the high frequency analog current multiplier is proposed. It consists of a current summing circuit and a current squaring circuit. The detailed circuit designs and analyses are presented in the following.

2.1 Current-mode LNA

The circuit diagram of the proposed current-mode LNA is shown in Fig.2(a) where M1 and M2form the first-stage current-mirror amplifier and M3 and M4form the second stage cascaded with the first stage. All MOS are operated in the saturation region. The aspect ratio of M2is designed M times of that of M1 whereas the aspect ratio of M4 is designed N times of that of M3. Therefore, the gate-source capacitances of M2ðM4Þ, CGS;M2ðCGS;M4Þ, is about MðNÞ

times of CGS;M1ðCGS;M3Þ. M6M8 with gate shorted to

drain are used to reduce the supply voltage to the amplifiers

so that the LNA can be biased well and operated at low dc power dissipation. The bypass capacitors C1C3 are used

at the nodes A1A3, respectively, to make them ac ground

and bypass the supply noise. If VDDis low enough, M6M8

and C1C3is not required as shown in Fig.2(b). To reduce

the signal losses at the operating frequency, the inductors L1L3are chosen as the loads of the current-mode LNA to

resonate out the parasitic capacitances CT1, CT2, and CT3at

the nodes A4, A5, and A6, respectively, where CT1 ¼

ð1 þ MÞCGS;M1þ CDS;M1, CT2 ¼ ð1 þ NÞCGS;M3þ CDS;M2þ

CDS;M3 and CT3¼ CDS;M4.

The input ac coupling capacitor CIN and the input pad

with the capacitance of CPAD1 form the input matching

network of the current-mode LNA. COUT is the capacitor

that blocks dc between LNA and the following current-mode mixer. Only ac current signals can pass to the next stage. LGD is designed to resonate out the gate-drain

capacitor CGD2 of M2 at the operating frequency x0 in

order to enhance the reverse isolation of the LNA. After resonating out the parasitic capacitances of the transistor between its gate and drain, the transistor becomes more unilateral so that the stability can be improved. In addition, the input matching network is easier to design because of good isolation of the LNA.

At the operating frequency x0, inductors L1L3and the

respective parasitic capacitors CT1CT3 are resonated.

The small-signal equivalent circuits of the current-mode

(a) M1 M2 M3 M4 M6 M7 M8 CPAD1 CIN C OUT C1 C2 L1 LGD L2 L3 VDD LNAIN 1 : M 1 : N A1 A2 A3 A4 A5 A6 CT1 CT2 CT3 LNAOUT , out LNA i , in LNA i C3 (b) M1 M2 M3 M4 CPAD1 CIN COUT L1 LGD L2 L3 VDD LNAIN 1 : M 1 : N A4 A5 A6 CT1 CT2 CT3 LNAOUT , out LNA i , in LNA i Fig. 2 (a) Circuit diagram of

the current-mode LNA and (b) circuit diagram of the current-mode LNA of low-voltage version

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LNA of Fig.2(a) and2(b) at the operation frequency x0

are the same and can be depicted in Fig.3 where RT1¼ ðRp;L1==ro;M1Þ, RT2¼ ðRp;L2==ro;M2==ro;M3Þ and

RT3¼ ðRp;L3==ro;M4Þ. Rp;L1Rp;L3are the equivalent parallel

resistances of the inductors L1L3. ro;M1ro;M4 and

gm1gm4 are the output impedance and

transconduc-tance of the transistors M1M4, respectively. Because the

circuit dimensions are much smaller than the wave-lengths involved, the distributed effect of circuits is negligible. Thus the lumped small-signal equivalent circuit is adopted.

From Fig.3, the input impedance Zin;LNA in s-domain

can be expressed as Zin;LNAðsÞ ¼ 1 sCPAD1 k 1 sCIN þ RT1k 1 gm1     ¼ ð1þ gm1RT1Þ þ sRT1CIN s Cð PAD1þ CINÞ þ s2CPAD1CINRT1 : ð1Þ

Let s¼ jx and the input impedance of the LNA can be calculated as Zin;LNAðjxÞ ¼xRT1CIN½ðCPAD1þ CINÞ  1 þ gð m1RT1ÞCPAD1 x Cð PAD1þ CINÞ 2 þ xRð T1CPAD1CINÞ 2 h i  j 1þ gm1RT1 ð Þ Cð PAD1þ CINÞ  x2R2T1C 2 INCPAD1 h i x Cð PAD1þ CINÞ2þ xRð T1CPAD1CINÞ 2 h i : ð2Þ In order to achieve maximum power transfer, Zin;LNA

should be equal to 50 X at the operation frequency x0.

The imaginary part of the Zin;LNAcan be eliminated at x0if

the following equation is satisfied. 1þ gm1RT1 ð Þ Cð PAD1þ CINÞ  x20R 2 T1C 2 INCPAD1¼ 0: ð3Þ

Thus the relation among CIN; CPAD1; RT1, gm1, and x0

can be designed according to the following equation

x0¼ 1 RT1CIN ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1þ gm1RT1 ð Þ 1 þ CIN CPAD1   s : ð4Þ

Substituting (4) into (2), the input impedance at the operation frequency x0 can be expressed as

Zin;LNA x¼xj 0¼ RT1CIN½ðCPAD1þ CINÞ  1 þ gð m1RT1ÞCPAD1 CPAD1þ CIN ð Þ2þ xð 0RT1CPAD1CINÞ 2 h i : ð5Þ To calculate the current gain Aiand the voltage gain Av

of the LNA, the input impedance Zrfin;SUMof the following

current mixer should be taken into considerations. From Fig.3, the current gain Ai at the operating frequency x0

can be calculated and expressed as

The simulated gain, NF, and input matching character-istics of the current-mode LNA in Fig.2(b) are shown in Fig.4. The LNA can achieve the maximum gain of 17 dB at the operating frequency of 24 GHz. It can reach the NF of 3.4 dB at 24 GHz. The linearity performance of the LNA is verified by harmonic balance (HB) simulation. With the signals at 23.9 and 24.1 GHz, the simulated linearity curves shown in Fig. 5 depicts a P1 dB;LNA of

-18.5 dBm and a PIIP3;LNA of -10.8 dBm. The LNA

in Fig.2(b) drains 20.4 mA from the supply voltage of 0.8 V and drains 34.82 mA from the supply voltage of

1 1 m t g v g vm2 t1 CPAD1 CIN , in LNA Z + − 1 t v A4 A5 + − 2 t v g vm3 t2 RT1 RT2 4 2 m t g v RT3 Z M U S, ni f r , out LNA i , out LNA v RS=50 s v , in LNA i , in LNA v A 6

Fig. 3 Small-signal equivalent circuit of the current-mode LNA at the operating frequency x0

Aijx¼x0 iout;LNA iin;LNA     x¼x0 ¼ gm2gm4RT1RT2 1þ gm3RT2 ð Þ ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffið1þ gm1RT1Þ 2 1þ CPAD1=CIN ð Þ2þx2 0R2T1CPAD12 q  RT3 Zrfin;SUMþ RT3   : ð6Þ

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1.2 V. The increase in simulated current consumption from 20.4 to 34.82 mA is because the overdrive voltage of LNA is changed from 0.8 to 1.2 V as the supply voltage is increased from 0.8 to 1.2 V.

The accuracy of the gain (S21) of the LNA over different

process corners including FF, FS, TT, SF, SS are depicted in Fig.6(a) and (b). The S21 is varied from around 17.6 to

13.8 dB at the supply voltage of 0.8 V and is varied from about 18.1 to 16.9 dB at the supply voltage of 1.2 V.

2.2 Current-mode down-conversion mixer

The conceptual block diagram of the proposed current-mode down-conversion mixer is depicted in Fig.7. This mixer is composed of a current summing circuit, a current squaring circuit, and a band-pass filter (BPF). The RF input

current signal iLNA¼ ILNAcos xRFt from the current-mode

LNA and the LO input current signal iLO¼ ILOcos xLOt

from the off-chip LO signal generator are summed in advance through the current summing circuit. The summed current signal iSUM¼ ðiLNAþ iLOÞ ¼ ðILNAcos xRFtþ

ILOcos xLOtÞ are sent to the following current squaring

circuit which results in the square components of i2LNA and i2LO and the multiplication component iLNAiLO. The

Fig. 4 Simulated gain, NF, and input matching characteristics of the current-mode LNA

Fig. 5 Simulated linearity performance of the current-mode LNA

Fig. 6 S21of the LNA in different process corners (a) at the supply

voltage of 0.8 V and (b) at the supply voltage of 1.2 V

Mixer

(

iLNA+iLO

)

LNA i LO i + + Current Summing Circuit Current Squaring Circuit

( )

2

(

)

2 LNA LO i +i IF i Bandpass Filter

Fig. 7 Conceptual block diagram of the current-mode down-conver-sion mixer

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multiplication component of two current input signals provides the function of double sideband mixing.

Through the double sideband mixing, the received 24-GHz signal is converted to 5 24-GHz which is the lower sideband (LSB) and 43 GHz which is the upper sideband (USB) with the LO signal at 19 GHz. Following the current squaring circuit is the BPF which is capable of frequency selectivity. In this receiver design, the center frequency of the BPF is designed at 5 GHz so that the targeted LSB can be obtained and the unwanted USB can be attenuated. The detailed operational principles of the current squaring circuit and the current summing circuit are described in the following subsections.

2.2.1 Current squaring circuit and band-pass filter

The conceptual circuit of the current squaring circuit as modified from [9] is shown in Fig.8where MSQ1and MSQ2

are current mirror circuit. The bulk and source of MSQ3are

connected together to eliminate the body effect. Assume that both short-channel effect and channel-length modula-tion effect are negligible, and the MOS transistors MSQ1MSQ3 are well matched with the same channel

width/length W=L. If all MOS devices are in the saturation

region, the relation between vGS;MSQ1; vGS;MSQ3, and the

input current iin can be expressed as

vGS;MSQ1¼ VB 2 þ iin knWLðVB 2VthÞ ; ð7Þ vGS;MSQ3¼ VB 2  iin knWLðVB 2VthÞ ; ð8Þ

where kn¼ lnCOX is the mobility ln times the oxide

capacitance per unit area COX; Vthis the threshold voltage,

vGS is gate-to-source voltage, and VB is the dc bias

voltage of the current squaring circuit and equal to ðvGS;MSQ1þ vGS;MSQ2Þ. From (7) and (8), the drain currents

i1and i3of MSQ1and MSQ3, respectively, can be calculated.

Since i1¼ i2, the output current iOUTcan be written as

iOUT ¼ i1þ i3¼ IBþ i2 in 4IB ; ð9Þ where IB¼ 1 4kn W LðVB 2VthÞ 2 : ð10Þ

Suppose the input current iin of the current squaring

circuit equals ðIRFcos xRFtþ ILOcos xLOtÞ, the output

current signal of the current squaring circuit from (9) can be expressed as iOUTð Þ ¼ It Bþ I2 RFþ I 2 LO 8IB   þ 1 8IB I2RFcos 2xRFtþ ILO2 cos 2xLOt   þIRFILO 4IB cos xð RFþ xLOÞt þ cos xð RF xLOÞt ½ : ð11Þ From the last term in (11), the double sideband mixing is achieved and the RF signal at the frequency xRFis mixed

with the LO signal at the frequency of xLO. The signal at

xRF is converted into the signals at ðxRFþ xLOÞ and at

ðxRF xLOÞ. The xIFin this design is set toðxRF xLOÞ.

The current conversion gain of the current squaring circuit can be defined as

Currnet conversion gain¼iOUTjx¼ xð RFxLOÞ

iRF ¼ILO 4IB ¼ ILO knWLðVB 2VthÞ 2: ð12Þ

From (12), the current conversion gain can be controlled by the magnitude of LO signal and the biasing voltage VB.

The load of the current squaring circuit can be designed by a LC tank which is resonated at IF and serves as a BPF. Because of its bandpass characteristics, both harmonic and inter-modulation components with frequencies far away

M

SQ1 in

i

3

i

1

i

i

2 OUT

i

V

B

M

SQ2

M

SQ3

C

7

L

7 Bandpass Filter Current Squaring Circuit

Fig. 8 Circuit diagram of the current squaring circuit and bandpass filter

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from the IF can be suppressed. Only the IF signal can be selected and sent to the output.

With the advanced of the CMOS technology, the device current is not of the square characteristic. Due to the short-channel effect, the relation among drain current iDS,

overdrive voltage vOVand drain to source voltage vDS can

be written as iDS¼ 1 2k W LðvOVÞ m 1þ kvDS ð Þ; ð13Þ

where 1 m\2, vOV¼ vGS Vth, and the coefficient k

models the effect of the channel length modulation which is related to vDS. Besides, the parameter m is roughly equal

2 if the overdrive voltage of the MOS is small. Because the drain to source voltage vDSbetween MSQ1and MSQ3are not

exactly the same when the biasing voltage VB is slightly

varied, the channel-length modulation effect should be considered as in (13).

Because VB is usually designed a little higher than two

times threshold voltage of MSQ1 and MSQ3 from the

con-sideration of the current conversion gain as shown in (12), the overdrive voltage voltages of both MSQ1 and MSQ3 are

not high. Consequently, the coefficient m in (13) can be approximated as 2. If d¼ ðvDS;MSQ3vDS;MSQ1Þ=2 and r ¼

ðvDS;MSQ3þ vDS;MSQ1Þ=2 is assumed, the expression iOUTin

(9) can be modified as iOUT¼ i2in 1 v ð Þ 4IB þ iinðVB 2VthÞ2  k 1þ kr ð Þ2 d 2IBþ rþ kr 2dð2þ2kr27k2r2Þ 2þ3kr ð Þ   dkr 3þ10krþ11k 2 r2þ4k3 r3 ð Þ 2þ3kr ð Þ   8 > > > > < > > > > : 9 > > > > = > > > > ; þ IB 1þ 2krþ2dk ð Þ 2þ3krð Þ2 2 2þ 3krð Þ 1þ krð Þ2þ2k 3dþ 7dkrþ4k2 r2   " # ; ð14Þ where v¼ k 2 1ð þ krÞ4 r 1 þ krð Þ 2 1þ 2kr ð Þ  d 1  krð Þ h i : ð15Þ If the effect of channel length modulation effect is neglected as k = 0, v is equal 0 and (14) can be simplified to (9). The factor of the i2

in in (14) reveals that the

conversion gain of the squaring circuit with the channel-length modulation becomes (1-v) times smaller than that without channel-length modulation.

Moreover, even if the drain to source voltage differences of MSQ1 and MSQ3 are the same, we have d¼ 0. But the

channel length modulation effect makes the coefficient v not equal 0. In this case, (14) can be simplified to

iOUT ¼ i2in 1 c ð Þ 4IB þ iinðVB 2VthÞ2 kr 1þ kr   þIB 2 1þ 2kr ð Þ 2 þ 3krð Þ2 2þ 3kr ð Þ 1 þ krð Þ2þ 4k3r2 " # ; ð16Þ where c¼kr 1ð þ 2krÞ 2 1ð þ krÞ2 : ð17Þ

From the above derivations, channel length modulation effect degrades the conversion gain of the current squaring circuit which is ð1  vÞ smaller in (14) or ð1  cÞ smaller in (16). Besides, this effect also results in the leakage of the fundamental signal of LO and RF signals. The simulation results in Fig.9 show that the conversion gain approaches maximum when the biasing voltage VB equals VDD which

is 1.2 V in this design. Meanwhile, the minimum value of drain to source voltage difference of MSQ1and MSQ3can be

achieved under this condition.

2.2.2 Current summing circuit

Figure10 shows the current summing circuit. Two com-mon-gate transistors M9and M10 operated in the saturation

region function as current buffers. The bulks of M9and M10

are connected to ground. Although M9and M10suffer from

the body effect resulting in slightly increase of their threshold voltage, the isolation among the input port of RF, the input port of LO, and the output port can be improved. Besides, the voltage headroom of this circuit is sufficient because the inductor L4is tied to VDDand L5L6are tied to

Fig. 9 Simulated conversion gain and jvDS;MSQ1vDS;MSQ3j versus VB.

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ground. This current summing circuit can be operated at very low supply voltage.

Due to the advantage of current-mode signal processing, the current signals iout;LNAfrom LNA circuit and iin;LOfrom

off-chip LO signal generator are summed by connecting the drains of M9 and M10 together. L4 is designed to

pro-vide high impedance at the output so that the summed current signal ðiout;LNAþ iin;LOÞ can be fed into the

fol-lowing current squaring circuit. C5 is the dc blocking

capacitor to prevent from disturbing the biasing point of the LNA. At the frequency of RF, L5 is resonated with the

parasitic gate-to-source capacitance CGS;M9 of M9 and

source-to-bulk capacitance CSB;M9 of M9 to provide high

impedance to ac ground so that the input RF current signal from the LNA circuit can flow into M9. L6, C6 and CPAD2

form the matching network for LO input port. The parasitic gate-to-source capacitance CGS;M10 of M10 and

source-to-bulk capacitance CSB;M10 of M10 are also considered in this

matching network.

2.3 Current-mode receiver front-end

The detailed connections of the current-mode receiver front-end circuits under a single supply voltage of VDDare

shown in Fig.11. The circuits include a two-stage current-mode LNA of low-voltage version, a current summing circuit, and a current squaring circuit. The input signal at xRFis firstly amplified by LNA, and then is mixed with the

LO signal at xLO by the current-mode mixer formed by a

current summing circuit and a current squaring circuit. The down-converted signal at xIFis finally sent to output buffer

which is a current-mirror amplifier formed by M14, M15,

and L8. The output matching network is designed by L8,

C9, and CPAD3 so that the output impedance of the

mea-suring buffer equals 50 X and the maximum power transfer can be achieved. Table 2 shows the design parameters of the two-stage current-mode LNA of low-voltage version. Table3 shows the design parameters of current-mode down-conversion mixer and output buffer.

M9 M10 L5 L6 L4 C5 INPUTRF VDD , out LNA

i

CPAD2 C6 INPUTLO , in LO

i

, rfin SUM

Z

OUTPUTSUM , out SUM

i

, loin SUM

Z

Fig. 10 Circuit diagram of the

current summing circuit

r e f f u b t u p t u O t i u c r i c g n i r a u q s t n e r r u C t i u c r i c g n i m m u s t n e r r u C M9 M10 M 1 1 M 2 1 M13 M14 M 5 1 L 5L6 L 4 L8 CPAD2 C 3 D A P C 6 C5 C 8 C9 IFOUT O L IN L7 VB C7 VDD2 A N L e d o m -t n e r r u c e g a t s -o w t , ol n i i , ,SUM inSQU t u o i i = ,SQU t u o i M 1 M2 M3 M4 CPAD1 CIN L1 LGD L2 L3 F RIN ,LNA n i i V 1 D D ,LNA t u o i r e x i m e d o m -t n e r r u C A 4 A5 A6

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In this work, the RF input frequency is set at 24 GHz, the LO frequency is set at 19 GHz, and accordingly the IF output frequency is at 5 GHz. The image frequency is at 14 GHz. According to Fig.4, the image rejection of the proposed receiver front-end is more than 30 dB before the first down-conversion mixer due to the large IF frequency of 5 GHz is selected. This performance is achieved due to the multistage nature of bandpass LNA. If much higher image rejection is required, the off-chip band-select filter

before the LNA can be used to enhance the performance of image rejection.

For testing consideration, the three ports are also designed to match with 50 X. If multiple power supplies can be used in the receiver front-end, the simulated power consumption of the current-mode receiver is 29.94 mW where the two-stage current-mode LNA of low-voltage version drains 20.4 mA from the supply voltage of 0.8 V, and the current summing circuit and current squaring circuit drain 8.8 and 2.55 mA, respectively, from the supply voltage of 1.2 V. Under this condition, the two-tone analyses by HB simulation with two RF input signals at 23.95 and 24.05 GHz and the LO signal at 19 GHz with the power level of -3 dBm are depicted in Fig.12. It reveals that the receiver has a simulated conversion gain of 21.5 dB, a P1 dB;RX of -29 dBm, and a PIIP3;RX of

-18.2 dBm. The simulated total NF is 4.2 dB with the RF at 24 GHz and LO at 19 GHz.

Moreover, if the receiver front-end is restricted to use single power supply, it consumes 55.4 mW from the supply voltage of 1.2 V. The excess power consumption is from the LNA because higher voltage is adopted to bias the LNA of the low-voltage version, and the LNA drains 34.82 mA from the supply voltage of 1.2 V.

The use of multiple supply voltage of 0.8 and 1.2 V complicates the design. In this design, the supply voltages are from different off-chip power supplies. Therefore, the smaller supply voltage can be easily supported. If the receiver is restricted to use a single supply voltage of 1.2 V, the LNA is recommended to use the circuit in Fig.2(a) where M6M8 provide a simple way to have the

voltage drop of around 400 mV for the LNA such that the voltages of A1A3 are around 0.8 V and M1M4 can be

well biased. Table 3 Device parameters of 24-GHz CMOS down-conversion

mixer and output buffer

Current-mode down-conversion mixer Current summing circuit

M9 L = 0.13 lm W = 38.4 lm M10 L = 0.13 lm W = 38.4 lm CCPAD2 20 fF C5 63 fF C6 274 fF L4 443 pH Rad = 27 lm, w = 3 lm, nr = 1.5 L5 945 pH Rad = 20 m, w = 3 lm, nr = 3.25 L6 916 pH Rad = 26 lm, w = 3 lm, nr = 2.75

Current squaring circuit

M11 L = 0.13 lm W = 14.4 lm M12 L = 0.13 lm W = 14.4 lm M13 L = 0.13 lm W = 14.4 lm L7 884 pH Rad = 15.5 lm, w = 3 lm, nr = 3.5 C7 1 pF C8 132 fF Output buffer M14 L = 0.13 lm W = 1.2 lm M15 L = 0.13 lm W = 150 lm L8 1.69 nH Rad = 20 lm, w = 3 lm, nr = 4.5 C9 583 fF

CPAD3 20 fF Fig. 12 Simulated linearity performance of the 24-GHz

current-mode receiver by two-tone HB analyses Table 2 Device parameters of 24-GHz CMOS LNA

Current-mode LNA of low-voltage version M1 L = 0.13 lm W = 1.2 lm M2 L = 0.13 lm W = 52.8 lm M3 L = 0.13 lm W = 1.2 lm M4 L = 0.13 lm W = 31.2 lm CPAD1 20 fF CIN 89 fF LGD 506 pH Rad = 32.5 lm, w = 3 lm, nr = 3 L1 298 pH Rad = 15 lm, w = 9 lm, nr = 1.5 L2 315 pH Rad = 15 m, w = 3 lm, nr = 1.5 L3 315 pH Rad = 15 m, w = 3 lm, nr = 1.5

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3 Experimental results

The designed 24-GHz current-mode receiver front-end circuit was fabricated in 0.13-lm 1P8M CMOS technol-ogy. The top metal of this process is with the thickness of 3.35 lm. The equivalent relative dielectric constant eeff is

about 4.2. Based on the technology information of the backend process, the electromagnetic (EM) tool HFSS is used to evaluate and extract the characteristics of the on-chip octagonal spiral inductors and the interconnections within the circuits.

The floor plans of the proposed receiver front-end are depicted in Fig.13. Nine on-chip octagonal spiral induc-tors are used. The distances of each inductor are more than 100 lm to mitigate the magnetic coupling between on-chip inductors. In addition, the distances of the active devices of mode LNA, current summing circuit, current-squaring circuit and output buffer are arranged far, the noise influence between these circuits are kept small. The signal path between input pad and the input of the LNA is drawn as short as possible to avoid additional signal losses and increase of NF. Besides, large on-chip decoupling capacitors are used between the biases and ground, such that high frequency noises can be bypassed to ground and consequently stable biases and supplies of the receiver can be achieved. All dc pads are protected by ESD diodes to enhance the reliability of the proposed receiver. The performance of each circuit block in this 24-GHz current-mode receiver is over-designed to overcome pro-cess variations. This chip occupies the active region of 1.45 9 0.72 mm2including testing pads.

The measurement setups of this fabricated receiver are described as follows. The on-wafer probing measurement is adopted to verify the performance of the receiver front-end. Three GSG RF probes with the pitch of 150 lm and a 6-pin dc probe with the pitch of 150 lm are applied to probe the testing pads. The S parameters are measured to analyze both the input and output matching characteristics by the network analyzer, Agilent E8364B, which can

characterize the S-parameter performance from 10 MHz to 50 GHz. To measure conversion gain and linearity, three signal generators Agilent E8257D are used to provide two RF and one LO signals for the device under test (DUT). The spectrum analyzer Agilent E4448A is used to monitor the spectrum to verify the linearity and conversion gain of the receiver. The NF analyzer Agilent N8975A with a broadband noise source HP 346C is used to measure the performance of NF of the receiver.

Owing to the layout mistake of the fabricated chip, the focused ion beam (FIB) post-process is used to modify the metal connections of the current-mode LNA. The FIB metal lines connect the LNA circuit to the power supply. Under the condition that multiple power supplies can be used so that the power supply of LNA is 0.8 V and the power supply of the current-mode mixer is 1.2 V, the measured total power consumption is 27.8 mW. Moreover, if the single power supply of 1.2 V is applied to the receiver front-end, the measured power dissipation is increased to about 49.8 mW. The reason why the increase in measured power dissipation from 27.8 mW for the multiple supply voltages to 49.8 mW for the single supply voltage is the supply voltage of LNA is increased from 0.8 to 1.2 V. This results in increasing more overdrive voltage of 400 mV of the LNA, and consequently the measured power dissipation of LNA itself is increased. The measured current consumption of the LNA is 19.45 mA from the supply voltage of 0.8 V and is 31.3 mA from the supply voltage of 1.2 V.

Figure14 presents the measured and revise-simulated conversion gain versus RF input frequency. The losses from cables, probes and adaptors are compensated. More-over, the parasitic resistances resulting from FIB post-process are considered in the revise-simulated results. The tested RF input power is -30 dBm. The LO is set to the frequency which is 5 GHz lower than the RF, fLO¼ fRF 5 GHz, and the tested LO input power is

-3 dBm. The output is observed at the fixed IF frequency of 5 GHz. The measured conversion gain of the RF frequency at 24 GHz is 11.3 dB under the condition that the power supplies of the LNA and Mixer are 0.8 and 1.2 V, respectively. In addition, the conversion gain is 12 dB under the condition that the power supply of both LNA and Mixer is 1.2 V. Because the parasitic resistances from FIB post-process are in series with the inductive loads of the current-mode LNA, the quality factor of the loads of the LNA is decreased. This makes the gain of the LNA decrease, and consequently the conversion gain of the receiver is decreased.

The two-tone test results are shown in Fig.15. Two RF inputs with 100 MHz frequency spacing are at the fre-quency of 24.05 and 23.95 GHz and the LO is at 19 GHz with the power of -3 dBm. Because of the conversion gain Fig. 13 Chip micrograph of the fabricated current-mode receiver

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reduction of the receiver, the measured P1 dBand PIIP3are

raised to -13.5 dBm and -1 dBm, respectively, under the condition that the power supplies of LNA and Mixer are 0.8 and 1.2 V, respectively. Besides, the measured P1 dB

and PIIP3are about -12 and -1.5 dBm, respectively, under

the condition that the single power supply of 1.2 V for LNA and mixer is adopted. At the RF frequency of 24 GHz and the LO frequency of 19 GHz, the measured total NF of the receiver is 14.2 and 13.3 dB if the power supply of LNA is 0.8 and 1.2 V, respectively.

Table4 summaries the performance of the proposed current-mode receiver front-end. In addition, some com-parison results of published 24-GHz receiver front-end circuits are also provided. Compared to the works pub-lished in [2] and [5], the proposed 24-GHz CMOS

current-mode receiver front-end has the advantage of smaller power dissipations and can be operated in low supply voltage. This current-mode receiver front-end also has better linearity performance.

The layout mistake has been corrected and the modified design is under fabrication now. Therefore, the new test results are unavailable at present.

4 Conclusion

In this work, the current-mode design techniques of CMOS RF circuits are developed and are applied to realize the first 24-GHz CMOS current-mode receiver front-end. The receiver integrated with a current-mode LNA and a Fig. 14 The measured and simulated conversion gain of the receiver

versus RF input frequency

Table 4 The measured performances and comparisons results of published 24-GHz receiver front-end circuits

This work [2] [5]

Technology 0.13 lm CMOS 0.18 lm CMOS 0.8 pm SiGe HBT

fT= 80 GHz

Receiver architecture Direct-conversion (2-stage LNA + Mixer)

Direct-conversion (3-stage LNA + single-balanced Gilbert Mixer) Direct-conversion (3-stage differential LNA + I/Q differential Gilbert Mixer)

Topology Current mode Voltage mode Voltage mode

FreqRF(GHz) 24 21.8 24.1 FreqLO(GHz) 19 16.9 23.9 FreqIF(GHz) 5 4.9 0.2 GainRX(dB) 12 11.3 27.5 31 NFRX(dB) 13.3 14.2 7.7 8.8 PIIP3, RX(dBm) -1.5 -1 – – P1 dB, RX(dBm) -12 -13.5 -23 -27 Power (mW) 49.8 27.8 64.5 640 Supply (V) 1.2 0.8/1.2 1.5 4 Chip area (mm2) 1.45 9 0.72 0.4 9 0.5 1.48 9 1.15

Fig. 15 The measured linearity performance of the receiver by two-tone testing

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current-mode down-conversion mixer is designed, fabri-cated in 0.13-lm CMOS technology and measured. Two-stage current-mirror amplifiers cascaded are used to realize the current-mode LNA. The LNA has the capability of low voltage operation. The current summing circuit and current squaring circuits are adopted to perform the mixing of the current signals. The measured results demonstrate that the proposed current-mode receiver front-end can operate well in the 24-GHz frequency band. Although the receiver does not achieve the expected performance because of the layout mistake, after the FIB post-process to remedy for the layout mistake, the designed 24-GHz CMOS current-mode receiver front-end still can exhibit the conversion gain of 11.3 dB, the NF of 14.2 dB, and the PIIP3 of -1 dBm

under the condition that power supply of the current-mode LNA is 0.8 V and the power supply of the current-mode mixer is 1.2 V. The total power dissipation of the current-mode receiver front-end under this condition is 27.8 mW. The current-mode design techniques have the capability of designing low-voltage RF circuits in the advanced nano-meter CMOS technologies. Future research on the applications of short range automotive radar systems or point-to-point wireless communication systems will be explored and discussed by the proposed current-mode approaches.

Acknowledgements This work was supported by the National Science Council (NSC), Taiwan, under the Grant NSC-95-2221-E-009-292. The authors would like to thank the National Chip Imple-mentation Center (CIC), National Applied Research Laboratories, Taiwan, for the fabrication of testing chip. The authors would also like to thank the support of CAD tools HFSS from Ansoft Taiwan.

References

1. Federal Communications Commission, FCC 02–04, Section XV.515.15.521.

2. Guan, X., & Hajimiri, A. (2004). A 24-GHz CMOS front-end. IEEE Journal of Solid-State Circuits, 39(2), 368–373.

3. Hajimiri, A., Hashemi, H., Natarajan, A., Guan, X., & Komijani, A. (2005). Integrated phased array systems in silicon. Proceedings of the IEEE, 93(9), 1637–1655.

4. Hugo, V., Van Der Heijden, E., Notten, M., & Dolmans, G. (2007). A SiGe-BiCMOS UWB receiver for 24 GHz short-range automo-tive radar applications. In IEEE Microwave Symposium, IEEE/ MTT-S International, pp. 1791–1794.

5. Ojefors, E., Sonmez, E., Chartier, S., Lindberg, P., Schick, C., Rydberg, A., & Schumacher, H. (2007). Monolithic integration of a folded dipole antenna with a 24-GHz receiver in SiGe HBT technology. IEEE Transactions on Microwave Theory and Tech-niques, 55(7), 1467–1475.

6. Meliani, C., Huber, M., Boeck, G., & Heinrich, W. (2006). A GaAs HBT low power 24 GHz downconverter with on-chip local-oscillator. In 1st European Microwave Integrated Circuits Con-ference, pp. 141–144.

7. Wu, C.-Y., Hsu, S.-W., & W.-C. Wang (2007). A 24-GHz CMOS current-mode power amplifier with high PAE and output power. In

2007 IEEE International Symposium on Circuits and Systems, ISCAS’07, New Orleans, USA, May 27–30, pp. 2866–2869. 8. Wang, W.-C., & Wu, C.-Y. (2007). The 1-V 24-GHz low-voltage

low-power current-mode transmitter in 130-nm CMOS technol-ogy. In IEEE 3rd Ph.D. Research in Microelectronics and Electronics, PRIME 2007, Bordeaux, France, July 2–5, 2007, pp. 49–52.

9. Bult, K., & Wallinga, H. (1987). A class of analog CMOS circuits based on the square-law characteristics of an MOS transistor in saturation. IEEE Journal of Solid-State Circuits, SC–22, 357–364.

Chung-Yu Wu was born in 1950. He received the M.S. and Ph.D. degrees from the Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Tai-wan, R.O.C., in 1976 and 1980, respectively. In addition, he conducted post-doc research at UC Berkeley in summer of 2002. Since 1980, he has served as a consultant to high-tech industry and research organiza-tions and has built up strong research collaborations with high-tech industries. From 1980 to 1983, he was an Associate Professor at National Chiao Tung University. During 1984 to 1986, he was a Visiting Associate Professor in the Department of Electrical Engineering, Portland State University, Portland, OR. Since 1987, he has been a Professor at National Chiao Tung University. From 1991 to 1995, he was rotated to serve as the Director of the Division of Engineering and Applied Science on the National Science Council, Taiwan. From 1996 to 1998, he was honored as the Centennial Honorary Chair Professor at National Chiao Tung University. Currently, he is the president and chair pro-fessor of National Chiao Tung University. He has published more than 250 technical papers in international journals and conferences. He also has 19 patents including nine U.S. patents. His research interests are nanoelectronics, low-power/low-voltage mixed-signal VLSI design, biochips, neural vision sensors, RF circuits, and CAD analysis. Dr. Wu is a member of Eta Kappa Nu and Phi Tau Phi Honorary Scholastic Societies. He was a recipient of IEEE Fellow Award in 1998 and Third Millennium Medal in 2000. In Taiwan, he received numerous research awards from Ministry of Education, National Science Council, and professional foundations.

Wen-Chieh Wang was born in 1978. He received the B.S. in Electronics Engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2000. He is currently working toward the Ph.D. degree at the National Chiao Tung University. His cur-rent research interests are in CMOS low-voltage low-power radio-frequency integrated cir-cuits design and analog integrated circuits design.

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Fadi R. Shahrourywas born in 1977. He received the B.S. in Electronics Engineering from Princess Sumaya University for Technology, Jordan, in 2000. He is currently working toward the Ph.D. degree at the National Chiao Tung University, Hsinchu, Taiwan. His current research interests are in voltage, low-power, and very high-frequency integrated circuits design and analog integrated circuits design in CMOS technology.

Zue-Der Huang was born in 1975. He received the B.S. and M.S. degrees from the Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Tai-wan, R.O.C. and Department of Electrical Engineering, Univer-sity of Southern California, USA in 1998 and 2002, respectively. From 2002 to 2004, he joined the Atheros Taiwan Research & Develop-ment Center as a design engineer. He is now pursuing the Ph.D degree in the Depart-ment of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan. His research interests include low-voltage current-mode CMOS RF circuits, focusing on RFVCO, frequency synthe-sizer, and transceiver design.

Hao-Jie Zhanreceived the M.S. degree from the Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C. in 2006. His research interests include CMOS RF integrated circuit design and analog inte-grated circuit design.

數據

Fig. 1 Block diagram of the 24-GHz current-mode receiver front-end
Fig. 1 Block diagram of the 24-GHz current-mode receiver front-end p.2
Fig. 3 Small-signal equivalent circuit of the current-mode LNA at the operating frequency x 0
Fig. 3 Small-signal equivalent circuit of the current-mode LNA at the operating frequency x 0 p.4
Fig. 6 S 21 of the LNA in different process corners (a) at the supply
Fig. 6 S 21 of the LNA in different process corners (a) at the supply p.5
Fig. 7 Conceptual block diagram of the current-mode down-conver- down-conver-sion mixer
Fig. 7 Conceptual block diagram of the current-mode down-conver- down-conver-sion mixer p.5
Fig. 4 Simulated gain, NF, and input matching characteristics of the current-mode LNA
Fig. 4 Simulated gain, NF, and input matching characteristics of the current-mode LNA p.5
Fig. 5 Simulated linearity performance of the current-mode LNA
Fig. 5 Simulated linearity performance of the current-mode LNA p.5
Fig. 8 Circuit diagram of the current squaring circuit and bandpass filter
Fig. 8 Circuit diagram of the current squaring circuit and bandpass filter p.6
Fig. 9 Simulated conversion gain and jv DS;MSQ 1 v DS;MSQ 3 j versus V B .
Fig. 9 Simulated conversion gain and jv DS;MSQ 1 v DS;MSQ 3 j versus V B . p.7
Figure 10 shows the current summing circuit. Two com- com-mon-gate transistors M 9 and M 10 operated in the saturation

Figure 10

shows the current summing circuit. Two com- com-mon-gate transistors M 9 and M 10 operated in the saturation p.7
Fig. 11 Detailed connections of the 24-GHz current-mode receiver front-end with output buffer
Fig. 11 Detailed connections of the 24-GHz current-mode receiver front-end with output buffer p.8
Figure 14 presents the measured and revise-simulated conversion gain versus RF input frequency

Figure 14

presents the measured and revise-simulated conversion gain versus RF input frequency p.10
Fig. 15 The measured linearity performance of the receiver by two- two-tone testing
Fig. 15 The measured linearity performance of the receiver by two- two-tone testing p.11
Table 4 The measured performances and comparisons results of published 24-GHz receiver front-end circuits

Table 4

The measured performances and comparisons results of published 24-GHz receiver front-end circuits p.11
Table 4 summaries the performance of the proposed current-mode receiver front-end. In addition, some  com-parison results of published 24-GHz receiver front-end circuits are also provided

Table 4

summaries the performance of the proposed current-mode receiver front-end. In addition, some com-parison results of published 24-GHz receiver front-end circuits are also provided p.11

參考文獻