Abstract—This paper describes a hybrid image rejection receiver. The hybrid image rejection receiver contains a modified Hartley image rejection mixer and a digital image rejection processor. The modified Hartley image rejection mixer performs similarly to an original Hartley image rejection receiver but provides two digital outputs. In one output it enhances the desired signal, and in the other output it enhances the image signal. The digital image rejection processor first measures the mismatching effect in the analog devices and then suppresses the image signal by compensating for the mismatching effect. We also propose a simplified implementation method for the hybrid image rejection receiver to reduce its computation complexity. Computer sim-ulation was used to evaluate the performance of this simplified implementation method to include the quantization effect intro-duced by the A/D converters. Simulation results show that the proposed hybrid image rejection receiver achieves much better performance than the original Hartley image rejection receiver. This architecture greatly relaxes the matching requirements of the analog devices and has a low complexity for an IC implementation. Index Terms—Digital mismatch compensation, gain mismatch, hybrid image rejection receiver, low-IF, phase mismatch.
I. INTRODUCTION
T
HE CONTINUING evolution in both cellular mobile telephone services and personal communication services (PCS) demands small-size handsets at low cost [1], [2]. A monolithic RF module with a highly integrated transceiver architecture is required for fulfilling this purpose. Various transmitters designed with compact size and good performance have been proposed for different modulation schemes [3]–[5]. However, on the receiver side, it is still a major challenge to search for well-designed and highly integrated solutions [6].Conventionally, three types of receiver architectures have been used: the heterodyne receiver architecture, the direct-conversion receiver architecture, and the low intermediate frequency (IF) receiver architecture. A heterodyne receiver architecture requires two or more local oscillators (LOs) and external filters, including a very high factor channel selec-tion filter at a high frequency band. These filters are usually implemented with discrete components. Because a heterodyne receiver has good performance in its image rejection capability and channel selectivity, it has been used in most applications for a long time [7]. Nevertheless, this architecture is not suitable for a single-chip integrated circuit design.
A direct-conversion receiver architecture requires fewer discrete components and achieves a higher integration level
Manuscript received September 30, 1999; revised August 9, 2000. The authors are with the Communication Engineering Department, National Chiao Tung University, Hsinchu, Taiwan, R.O.C.
Publisher Item Identifier S 0733-8716(01)01911-4.
than other traditional receiver architectures [8]–[10]. Neverthe-less, this architecture comes with several drawbacks [11]. For instance, DC-offset due to self-mixing and flicker noise near DC frequency in the devices substantially corrupt the baseband signal. Moreover, the mismatches between the in-phase and quadrature phase channels also distort the baseband signal constellation, thereby degrade the SNR performance. These mismatches can be reduced through a careful circuit design and fabrication procedure [12]. Nevertheless, both DC-offset and flicker noise problems are still difficult to deal with and require further efforts to overcome [13].
A low-IF receiver architecture can be implemented in a highly integrated way and is not sensitive to parasitic effects such as DC-offset voltages and self-mixing products. However, this ar-chitecture suffers severely from the image problem [14]. An image signal comes from an adjacent channel and cannot be to-tally removed by RF bandpass filtering. In 1928, Hartley intro-duced an image rejection receiver which has a similar structure as a single sideband (SSB) modulator [15]. The primary diffi-culty with Hartley’s architecture is the serious degradation in its image rejection capability due to both gain and phase mis-matches. For example, if the architecture needs to provide a 60 dB of image suppression, its phase mismatch between the in-phase and the quadrature phase channels must be maintained below 0.1 , even with no gain mismatch. This matching require-ment is very difficult to meet in a typical IC design.
Many methods have been proposed to improve the matching issues in the low IF receiver architecture. Modifying the phase-shift circuit was proposed in [16]. Careful tuning and trimming in the analog circuits was introduced in [17]. A double quadra-ture downconverter makes the analog circuits more robust with respect to phase mismatch [18], [19]. Digital approaches for the correction of channel mismatch were presented in [20] and [21]. In [22], a complex least-mean-square algorithm and a modified adaptive noise cancellation model were used to com-pensate for the mismatching effect, which needed high compu-tation power.
Conventional image rejection receiver architectures are imple-mented by analog circuit techniques. In this paper, we propose a hybrid analog and digital image rejection receiver architecture. Unlike conventional pure analog realizations, this architecture uses both analog and digital signal processing techniques to suppress the image signal. This architecture adopts a modified Hartley image rejection mixer and a digital image rejection processor. The modified Hartley image rejection mixer has per-formance similar to the original Hartley image rejection receiver but provides two digital outputs. In one output it enhances the de-sired signal, and in the other output it enhances the image signal.
Fig. 1. A hybrid image rejection receiver system.
In the digital image rejection processor, this hybrid receiver first measures the mismatching effects in the analog devices and then suppresses the image signal digitally by compensating for the mismatching effects. The proposed architecture greatly relaxes the matching requirements for analog circuits and achieves a very high degree of image suppression capability.
In Section II, we describe the proposed hybrid image rejec-tion receiver and derive its image rejecrejec-tion ratio (IRR) with mismatches in analog devices as parameters. In Section III, we describe a simplified implementation method for the proposed hybrid image rejection receiver architecture. Both the perfor-mance and the numerical accuracy of this architecture were evaluated by computer simulations and the simulation results are presented in Section IV. Finally, a conclusion is given in Section V.
II. A HYBRIDIMAGEREJECTIONRECEIVERARCHITECTURE
In this section, we describe a hybrid image rejection receiver architecture. Its simplified block diagram is shown in Fig. 1. In this architecture, a radio frequency (RF) signal is received by an antenna and passed through an RF front end to generate a bandpass signal. The bandpass signal is then sent to a hybrid image rejection receiver to suppress the image signal.
The hybrid image rejection receiver can be divided into two parts. One part is a modified Hartley image rejection mixer, and the other part is a digital image rejection processor. The modi-fied Hartley image rejection mixer generates two digital output signals and , where the signal emphasizes on the de-sired signal and the signal emphasizes on the image signal. The digital image rejection processor utilizes both the signal and the signal to achieve a much higher degree of image suppression.
In the following three subsections, we first describe the mod-ified Hartley image rejection mixer. Then we introduce a single-stage image rejection processor. Next, we describe a multisingle-stage image rejection processor.
A. The Modified Hartley Image Rejection Mixer
The block diagram of the modified Hartley image rejection mixer is shown in Fig. 2. This mixer is a hybrid analog and digital circuit which is essentially an extended Hartley image rejection receiver. An RF input signal is mixed with the two local
quadrature oscillator signals and down converted to a low IF band. After IF bandpass filtering, the lower arm signal is subject to a phase shift with respect to the upper arm signal. The two bandpass A/D converters are used to generate two baseband digital signals through an IF sampling technique [23]. The digital output signal is obtained by adding signals coming from both arms, and the digital output signal is obtained by subtracting the lower arm signal from the upper arm signal.
Ideally, the output signal will be the desired signal and the output signal will be the image signal. Due to the mis-matches in the analog devices, however, the signal preserves the desired signal more than the image signal, and the signal preserves the image signal more than the desired signal. To fur-ther understand the signal contents in and , we formulate them individually as follows.
Assume that an RF input signal is represented by (1) where is the real part notation. On the right side of the equa-tion, the first term is the desired signal and the second term is the image signal. and are their equivalent baseband repre-sentations, and and are their carrier frequencies. In general, both and are complex and can be represented by
(2) (3) where and are the real and imaginary components of , and and are the real and imaginary com-ponents of . Without loss of generality, the mixing opera-tion is assumed to be of a low-side injecopera-tion type. This implies , where is the local oscillator frequency and is a low IF frequency.
Multiplying the signal by the local oscillator in-phase signal and neglecting the high frequency components, we obtain the signal as
(4) Assume the gain mismatch and phase mismatch between the lower arm and the upper arm are represented by and , respec-tively. We multiply the signal by
Fig. 2. The modified Hartley image rejection mixer.
and neglect the high frequency components to obtain the signal as
(5) After applying an additional phase shift, we obtain the signal as
(6) From (4) and (6), we observe the discrete-time equivalent base-band signals and in both arms are
(7)
(8) where is the discrete-time index. Finally, the output signals
and can be calculated as
(9) and
(10) where
We observe from (9) that the gain for the desired signal is and the gain for the image signal is . On the other hand, we observe from (10) that the gain for the desired signal is and the gain for the image signal is . In general, as approaches 1 and approaches 0. Thus, the output signal
emphasizes the desired signal, and the output signal emphasizes the image signal.
To examine the performance of this mixer, we define the image rejection ratio (IRR) as the ratio between the output “desired signal to image signal power ratio” and the input “desired signal to image signal power ratio.” From (9), we can calculate the IRR for the signal as
IRR
(11) Note that IRR has the same performance as that of an original Hartley image rejection receiver [14].
Fig. 3. The single-stage image rejection processor.
B. The Single-Stage Image Rejection Processor
To enhance the IRR performance of the modified Hartley image rejection mixer, the mismatching effects in the analog devices must be compensated digitally. In the digital image re-jection processor, we compensate for the mismatches by elim-inating the image signal component in the output signal of the modified Hartley image rejection mixer.
The block diagram of a single-stage image rejection pro-cessor is shown in Fig. 3. This propro-cessor contains a correlation coefficient processor, a multiplier, and a subtractor. First, the correlation coefficient processor measures the mismatching ef-fects in the analog devices by calculating a modified correlation coefficient between the two signals and . Assume the desired signal and the image signal are uncorrelated and have zero means, from (9) and (10) we get
where is the expectation notation [24]. The modified cor-relation coefficient is defined and computed as
(12) Note that depends only on the mismatches in the analog de-vices.
We estimate the image signal component within the signal by multiplying the input signal with the correlation co-efficient . Then, we subtract the estimated image signal
com-ponent from the input signal to obtain the output signal . From (9), (10), and (12), we get
(13) Although this subtraction attenuates the desired signal, it sup-presses much more the image signal. The IRR performance for the output signal can now be calculated as
IRR (14)
After cascading a single-stage image rejection processor with a modified Hartley image rejection mixer, we obtain an overall IRR for the output signal as the cube of the IRR that can be achieved by using the modified Hartley image rejection mixer alone [see (11)].
C. The Multistage Image Rejection Processor
To improve the IRR performance, we introduce a multi-stage image rejection processor. Its simplified block diagram is shown in Fig. 4. We observe that multiple stages of digital de-sired/image signal separators are cascaded with a single-stage image rejection processor to make a multistage image rejection processor. Each stage of digital desired/image signal separator is used to further separate desired signal from image signal, and vice versa. Theoretically, we can obtain better and better IRR performance by cascading more and more stages of the digital desired/image signal separators with a final stage of single-stage image rejection processor.
Fig. 5 shows the block diagram of a digital desired/image signal separator. This device is a modification from a single-stage image rejection processor. In this device, the correlation coefficient processor is the same as the one in the single-stage image rejection processor. In addition to the original output signal , an extra output signal is generated to enhance
Fig. 4. The multistage image rejection processor.
Fig. 5. Digital desired/image signal separator.
the image signal for the next stage input. To examine the func-tion of this device, we derive the output signals and
below. Let , , , and
. From (13), we can directly calculate the first stage output signal as
(15)
Reversing the order of and and applying the complex conjugate of the correlation coefficient, we can calculate the first stage output signal as
(16)
Now we can rewrite (15) and (16) as
(17) (18) where
and
Since , the output signal
pre-serves more desired signal as compared with its input signal , and the output signal preserves more image signal as com-pared with its input signal . In a similar way, we can derive the output signals and for the second stage of the dig-ital desired/image signal separator as
(19) (20)
Fig. 6. A simplified implementation method for the proposed receiver.
where
and
In a similar way, we can achieve better separation between the desired signal and the image signal by cascading more and more stages of digital desired/image signal separators. Finally, a single-stage image rejection processor is used to further eliminate the image signal and obtain the final output signal . From (17) and (18), we observe that the IRR for the output signal is the cube of the IRR for the input signal for each stage of the digital desired/image signal separator. We can calculate the overall IRR for the output signal of the multistage image rejection processor as
IRR (dB) (21)
where is the IRR of the modified Hartley image rejection mixer in dB scale, and is the number of stages (including the final stage) in the multistage image rejection processor. A multistage image rejection processor requires higher computa-tion power than a single-stage image rejeccomputa-tion processor, but it greatly enhances the IRR performance.
III. A SIMPLIFIEDIMPLEMENTATIONMETHOD FOR THE
PROPOSEDRECEIVERARCHITECTURE
The image rejection receiver architecture we described above utilizes digital signal processing techniques to enhance the IRR performance. Extra computations, such as correlation coeffi-cient calculations, are needed to implement the architecture. In this section, we propose a simplified implementation method for this receiver architecture to reduce its computation require-ments. Here, we assume the mismatching effects in the analog devices are fixed such that the computation of the correlation coefficients can be done in an off-line processor.
Fig. 6 shows the block diagram of the simplified imple-mentation method. The architecture now contains a simplified image rejection receiver and an off-line correlation coefficient calculator. The simplified image rejection receiver consists of a modified Hartley image rejection mixer, a programmable data register, a multiplier, and a subtractor. The off-line correlation coefficient calculator includes a training signal generator and an equivalent correlation coefficient processor. This implemen-tation method operates in a training mode and a receiving mode separately. In the training mode, the training signal generator generates a desired signal and an image signal simultaneously, and sends them to the modified Hartley image rejection mixer. The desired signal and the image signal are assumed to be uncorrelated. The two output signals of the modified Hartley image rejection mixer are then sent to the equivalent correlation coefficient processor to calculate an equivalent correlation coefficient. To understand the meaning of the equivalent corre-lation coefficient, we reformulate the correcorre-lation coefficient for each stage of the multistage image rejection processor.
Fig. 7. The flow chart for the training mode.
From (15) and (16), the signals and can be repre-sented in a matrix form as
(22)
where is the correlation coefficient and
(23)
where
and
Substituting (23) to (24), we can obtain as
(25) In a similar way, we can deduce that the th stage correlation coefficient can be represented by the th stage correlation coefficient as
(26) After computing the correlation coefficient for each stage, we can calculate an equivalent correlation coefficient for a multi-stage image rejection processor.
Consider an -stage image rejection processor, the output signal of the th stage can be represented as
(27) where are the correlation coefficients of all the stages and is defined as an equivalent correlation matrix, which is represented by
TABLE I SIMULATIONPARAMETERS
Fig. 8. Image rejection ratio performance at different A/D resolutions ( = 0 dB, m = 2 dB, and = 15 ).
Both and are functions of according to (26), and we define the equivalent correlation coefficient as
(29) After the equivalent correlation coefficient is computed, we send it to the programmable data register (see Fig. 6) and com-plete the training mode operation. The training mode operation can be understood in more detail by examining the flow chart shown in Fig. 7. This whole training process can be done as an off-line procedure.
In the receiving mode, an RF input signal is received from an antenna and goes through the modified Hartley image rejection
mixer to obtain two digital output signals, and . We sub-tract the signal from the product of the signal and the stored equivalent correlation coefficient to obtain the output signal , i.e.,
(30) According to the analysis we have done above for the training mode, the IRR performance of the output signal in Fig. 6 is equivalent to that of a multistage image rejection processor. The simplified implementation method eliminates most of the computations by calculating an equivalent correlation coeffi-cient. This can be done when the receiver is being manufac-tured. In practical implementation, the mismatches in the analog
Fig. 9. Image rejection ratio performance at different A/D resolutions (N = 2, = 0 dB, and m = 1 dB).
devices might be a function of frequency and temperature. In such a case, we can calibrate the receiver system at a different frequency and temperature in advance. In real system opera-tion, we can dynamically adjust the equivalent correlation co-efficient if we can closely monitor the variations in frequency and temperature.
IV. PERFORMANCEVERIFICATION BYSIMULATION
The performance of the hybrid image rejection receiver was evaluated by computer simulation. The quantization effect in-troduced by the A/D converters [25] was included in our evalu-ation. The simplified implementation method for the proposed image rejection receiver as shown in Fig. 6 was adopted in our simulation.
A. Simulation Method and Parameters
In our simulation, we assume the input signals are two com-plex tones in the training mode and two comcom-plex Gaussian sig-nals in the receiving mode, respectively. In the training mode, the desired signal and the image signal are assumed
to be complex baseband sinusoidal signals with frequency 2 kHz and 3 kHz, that is,
In the receiving mode, the desired signal and the image signal are assumed to be complex baseband signals where
where , , , and are independently
generated Gaussian signals. Other simulation parameters are given in Table I. In order to investigate the improvement of the IRR performance in cascading a multistage image rejection processor, the number of stages of the multistage image rejection processor was varied from 1 to 7. The phase mismatch parameter and the gain mismatch parameter were used to model the imbalance of the two arms (see Fig. 2). Due to the mismatches in the two arms, the input signal power to the A/D converters is different in general. Without loss of generality, we assume the signal power in the lower arm is stronger than
Fig. 10. Image rejection ratio performance at different A/D resolutions (N =2, = 0 dB, and = 1 ).
the signal power in the upper arm. In order to minimize the quantization distortion, we normalize the input signals to fit in the dynamic range of the A/D converters according to the signal power in the lower arm. With the complex sinusoidal input signals, the input signals to the A/D converters were limited by the maximum magnitude of the input signal in the lower arm. With the complex Gaussian input signals, the input signals to the A/D converters were limited by three times of the standard deviation of the input signal in the lower arm. In the training mode, the input “desired signal to image signal power ratio” parameter was set to 0 dB. In the receiving mode, the input “desired signal to image signal power ratio” parameter was varied within the range as shown in Table I.
Including the quantization effect, the output signal of the proposed receiver can be represented as
(31) where is the desired signal component, is the image signal component, both from floating-point calculation, and is the overall quantization noise. From (30), (9), and (10), the desired signal component can be calculated as
by replacing and with and . We de-fine an image rejection ratio (IRR) with quantization noise as
IRR (dB) (32)
This IRR measure is used to evaluate the performance of the proposed image rejection receiver in our simulation.
B. Simulation Results
To examine the quantization effect on the IRR performance, we simulated the simplified implementation method at 8, 10, and 12 bits resolutions of the A/D converters. Fig. 8 shows the simulated IRR performance versus the number of stages (in-cluding the final stage) . In this simulation, the input “desired signal to image signal power ratio” was set to 0 dB. The gain mismatch and the phase mismatch were set to 2 dB and , respectively. The IRR performance of the original Hartley image rejection receiver, which is computed by (10), is also shown for comparison purpose. When the number of stages is one ( ), we observe that the IRR of our receiver is nearly three times the IRR (in dB scale) obtainable from the original Hartley image rejection receiver, which agrees with (21). As the number of stages increases, the IRR performance improves and remains a constant when the number of stages exceeds two. In addition, we observe that the IRR performance becomes better and better as the bit resolution increases.
Fig. 9 shows the simulated IRR performance versus phase mismatches. Here, the number of stages ( ) was set to 2. The input “desired signal to image signal power ratio” was set to 0 dB and the gain mismatch was set to 1 dB. We observe from this figure that the IRR performance of our receiver is much
Fig. 11. Image rejection ratio performance at different A/D resolutions (N =2, = 1 , and m = 1 dB).
better than the original Hartley image rejection receiver. The IRR performance also becomes better as the bit resolution in-creases. In addition, IRR does not vary much until the phase mismatch exceeds about .
Fig. 10 shows the simulated IRR performance versus gain mismatches and the IRR performance of the original Hartley image rejection receiver. In this simulation, the number of stages ( ) was also set to 2. The input “desired signal to image signal power ratio” was set to 0 dB and the phase mismatch was set to . From this figure, we again observe that the IRR perfor-mance of our receiver is much better than the original Hartley image rejection receiver, and it becomes better as the bit res-olution increases. The IRR performance of the original Hartley image rejection receiver decays rapidly as the gain mismatch in-creases. However, the IRR performance of our receiver degrades slowly as the gain mismatch initially increases.
To investigate the effect of the input “desired signal to image signal power ratio” on the IRR performance, we simulated the simplified implementation method at different values when the number of stages was set to 2. Fig. 11 shows the simulated
IRR performance versus values. The gain mismatch was set to 1 dB and the phase mismatch was set to . From the figure, we observe that the IRR performance improves as the bit resolution increases. In addition, the IRR performance improves as decreases and remains at a constant value when is below about 30 dB.
From the above simulation results, we found that the IRR performance of the hybrid image rejection receiver is limited by the quantization effect. Therefore, a higher resolution A/D is needed to achieve better IRR performance. For example, if we want to achieve a 50 dB of IRR, we need to use an A/D converter with 12 bits resolution in the hybrid receiver system.
Although the IRR performance is limited by the quantiza-tion effect, it is quite insensitive to phase mismatch in the hy-brid receiver system. We can achieve good IRR performance even though the phase matching is relatively poor. On the other hand, gain mismatch affects the IRR performance more but it can be corrected also more easily. Therefore, the matching re-quirements for the analog devices in the hybrid image rejection receiver can be greatly relaxed.
V. CONCLUSION
The mismatching effect in the analog devices is the main problem of a Hartley image rejection receiver. In this paper, we presented a hybrid image rejection receiver architecture. This architecture utilizes both analog and digital signal processing techniques to compensate for the mismatching effect and sup-press the image signal. This method is shown to be able to ef-fectively enhance the image rejection ratio (IRR) performance. We also proposed a simplified implementation method for the hybrid image rejection receiver to reduce its computation requirements. The performance of the simplified implementa-tion method was simulated to include the quantizaimplementa-tion effect. Our simulation results demonstrated that the IRR performance of the hybrid image rejection receiver is much better than the original Hartley image rejection receiver and is insensitive to the phase mismatch. This architecture not only greatly relaxes the matching requirements for the analog devices but also pro-vides a feasible solution for an IC implementation.
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Chun-Chyuan Chen was born in Hualien, Taiwan,
R.O.C. He received the B.S. and M.S. degrees in elec-tronic engineering from the Chung Yuan Christian University (CYCU), Chung-Li, Taiwan, R.O.C., in 1990 and 1992, respectively.
From 1994 to 1995, he was with the Tecom Co. Ltd., in the Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C., as an engineer, working on HDSL based Digital Pair-Gain System (DPGS). He is cur-rently a Ph.D. candidate in the Department of Com-munication Engineering of the National Chiao Tung University (NCTU). His research interests include the design of baseband re-ceivers in communication systems and spread spectrum systems, especially for wireless communications.
Chia-Chi Huang was born in Taiwan, R.O.C. He
re-ceived the B.S. degree in electrical engineering from National Taiwan University in 1977, and the M.S. and Ph.D. degrees in electrical engineering from the Uni-versity of California, Berkeley, in 1980 and 1984, re-spectively.
From 1984 to 1988, he was an RF and Communi-cation System Engineer with the Corporate Research and Development Center, General Electric Co., Sch-enectady, NY, where he worked on mobile radio com-munications. From 1989 to 1992, he was with the IBM T.J. Watson Research Center, Yorktown Heights, NY, as a Research Staff Member, working on indoor radio communications. Since September 1992, he has been with the Department of Communication Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C., as an Associate Professor.
