On-Chip ESD Protection Design by Using Polysilicon
Diodes in CMOS Process
Ming-Dou Ker, Senior Member, IEEE, Tung-Yang Chen, Student Member, IEEE, Tai-Ho Wang, and
Chung-Yu Wu, Fellow, IEEE
Abstract—A novel on-chip electrostatic discharge (ESD) protec-tion design by using polysilicon diodes as the ESD clamp devices in CMOS process is first proposed in this paper. Different process splits have been experimentally evaluated to find the suitable doping concentration for optimizing the polysilicon diodes for both on-chip ESD protection design and the application require-ments of the smart-card ICs. The secondary breakdown current (It2) of the polysilicon diodes under the forward- and reverse-bias conditions has been measured by the transmission-line-pulse (TLP) generator to investigate its ESD robustness. Moreover, by adding an efficient VDD-to-VSS clamp circuit into the IC, the human-body-model (HBM) ESD robustness of the IC with polysilicon diodes as the ESD clamp devices has been successfully improved from the original 300 V to become 3 kV. This design has been practically applied in a mass-production smart-card IC.
Index Terms—Electrostatic discharge (ESD), ESD protection circuit, polysilicon diode, smart card, transmission-line-pulse (TLP) generator.
I. INTRODUCTION
I
N THE smart-card IC application, the electrical power for circuit operations is generated from the transformer (formed by several loops of planner inductor on the circuit board) and the on-chip bridge rectifying circuit into the smart-card IC. The traditional full-wave bridge rectifying circuit formed by four diodes to convert the ac power into dc power is shown in Fig. 1. An ac voltage between terminals Vs1 and Vs2 is rectified into a dc voltage and stored in the capacitor Cs for application across the load. When the smart card is close to a card reader (or de-tector), the electromagnetic field generated from the card reader is coupled by the transformer in the smart card and charges up the electrical power of the smart card for circuit operation. The coupled ac power is converted into dc power by the on-chip four-diode bridge rectifying circuit in the smart-card IC. With the converted dc power, the information stored in the smart-card IC can be emitted out and detected by the card reader for per-sonal identification or other applications. The typical applica-tion of such a smart-card IC to enter a controlled door is illus-trated in Fig. 2.When the on-chip rectifying circuit is realized in a CMOS IC with a p-type substrate, the diodes D1 and D2 are often made by the p–n junctions across p diffusion and n-well. The diodes D3
Manuscript received July 26, 2000; revised December 21, 2000.
M.-D. Ker, T.-Y. Chen, and C.-Y. Wu are with the Integrated Circuits and Systems Laboratory, Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan 300, R.O.C. (e-mail: [email protected]).
T.-H. Wang is with the Production and Technology Division, Sunplus Tech-nology Company, Ltd., Hsinchu, Taiwan, R.O.C.
Publisher Item Identifier S 0018-9200(01)02401-5.
Fig. 1. Traditional full-wave bridge rectifying circuit formed by four diodes to convert the ac power into dc power.
Fig. 2. Typical application of a smart-card IC for personal identification to enter a controlled door.
and D4 are often made by the p–n junctions across n diffusion and p-substrate. The diode device structures in a CMOS IC with a common p-substrate are illustrated in Fig. 3. Due to the common p-substrate of a CMOS IC, besides the diode structures in Fig. 3, there are four parasitic bipolar junction transistors (BJTs), Q1, Q2, Q3, and Q4, in this structure. Q1 (Q2) is a parasitic vertical p–n–p BJT between the Vs1 (Vs2) and the common p-substrate. Q3 (Q4) is a parasitic lateral n–p–n BJT between the Vs2 (Vs1) and the VDD-biased n-well. These parasitic BJTs would cause the degraded rectification efficiency, or even no rectification at all, for the full-wave bridge rectifying circuit. The parasitic BJTs are drawn into the full-wave bridge rectifying circuit and illus-trated in Fig. 4 to show its influence. When the ac voltage is in 0018–9200/01$10.00 © 2001 IEEE
Fig. 3. Device cross-sectional view of the four p–n junction diodes of the full-wave bridge rectifying circuit realized in a CMOS IC with a common p-type substrate.
its positive half-wave period (Vs1 Vs2), the base–emitter junc-tion (the diode D3) of the parasitic BJT Q3 is forward biased to turn on the BJT Q3. Thereby, a great amount of charge current is created that directly flows through the parasitic BJT Q3 (from VDD node to Vs2) instead of through the capacitor Cs. During the positive half-wave period (Vs1 Vs2), the diode D1 is also forward biased and therefore turns on the parasitic BJT Q1. Some of the charge current is directly flowing through the parasitic ver-tical BJT Q1 (from Vs1 to VSS node) instead of through the capacitor Cs. Similarly, the same problem caused by the para-sitic BJTs Q2 and Q4 occurs during the negative half-wave pe-riod (Vs1 Vs2). Therefore, the rectification efficiency of this full-wave bridge rectifying circuit realized in the CMOS IC with a common substrate is seriously decreased, and could even have no rectification at all.
In some modified design, the diodes may be changed to nMOS or pMOS devices in the full-wave bridge rectifying circuit for realization in CMOS IC [1]. The parasitic vertical or lateral BJTs still exist among such device structures to degrade its rectification efficiency. Moreover, the different connections between the bulk and the source of nMOS or pMOS devices in the full-wave bridge rectifying circuit cause the body effect to degrade the power-converting speed and results in a poor rectification efficiency [1].
If the diodes in the full-wave bridge rectifying circuit are real-ized by the polysilicon diodes, which have no parasitic BJT in their device structures, the aforementioned problem can be to-tally eliminated. Therefore, the rectification efficiency can be-come much higher to convert the coupled ac power into dc power for circuit operation in a smart card. However, due to the low heat dissipation capability of the polysilicon layer, the polysil-icon diodes connected at the VS1 and Vs2 nodes (which are wire bonded to the circuit board in the final application) result in a very low human-body-model (HBM) electrostatic discharge (ESD) level of around 200–300 V. With such a low ESD level, the die of a smart-card IC assembled into the smart card by chip-on-board (COB) bonding is very susceptible to ESD events. This limits the ability to mass produce this smart-card IC.
In this paper, the breakdown voltage, leakage current, and ESD performance of the polysilicon diodes are first evaluated in the literature by performing different n- or p-type doping con-centrations with experimental process splits. The dependence between the secondary breakdown current (It2) (measured by
Fig. 4. Leakage current paths along the parasitic BJTs in the traditional full-wave bridge rectifying circuit realized in CMOS IC with a common p-type substrate.
Fig. 5. On-chip bridge rectifying circuit in a smart-card IC realized by four polysilicon diodes with the original design of on-chip ESD protection circuits.
the transmission-line-pulse generator) and layout spacing in the polysilicon diodes is also characterized in detail. The HBM ESD level of the smart-card IC can be finally improved to 3 kV by using a new power-rail ESD clamp circuit with the stacked polysilicon diodes as the turn-on control circuit [2].
II. ORIGINALDESIGN IN ASMART-CARDIC
Due to the aforementioned concerns on both leakage and substrate current in practical smart-card applications, the four-diode bridge rectifying circuit cannot be simply realized by using the n /p-substrate or the p /n-well junction diodes in a bulk CMOS process. Therefore, the on-chip bridge rectifying circuit in this smart-card IC is realized by four polysilicon diodes, as shown in Fig. 5. The coupled ac voltage across the pad1 and pad2 has a maximum voltage swing of 12 V and a frequency of 125 kHz in the smart-card application. The mem-orized data or number in the smart-card IC for identification is emitted out by the output pMOS (Mp2) in cooperation with the off-chip transformer. The diodes (Dp1, Dn1, Dp2, and Dn2) to form the four-diode bridge rectifying circuit are all realized by the polysilicon layer with p /n /n -doping concentration. The device structure and layout top view of the polysilicon diodes realized in a CMOS process are shown in Fig. 6(a) and (b), respectively. The polysilicon layer has a thickness of 1500 Å in a 0.8- m CMOS process. The layout spacing of the lightly doped center region in polysilicon diode is originally drawn as 3 m. The anode and cathode contacts of
Fig. 6. (a) Device structure and (b) layout top view of the p+/n0/n+ polysilicon diode realized in a 0.8-m CMOS process.
the polysilicon diode have a clearance of 4 m to the lightly doped center region.
To sustain a higher breakdown voltage ( 12 V) of the polysil-icon diode for smart-card application, an extra mask layer is added into the CMOS process flow to implant the n-region in the polysilicon diode. The p (n ) region in the polysilicon diode is implanted with a doping concentration of 6E15 (3.5E15) cm , which is the same as the drain/source implantation of pMOS (nMOS) in the CMOS process.
Due to the limitation of using the bulk p–n junction diodes to realize the bridge rectifying circuit, the on-chip ESD protec-tion circuits for pad1 and pad2 are therefore also realized by the polysilicon diodes (Dp1, Dn1, Dp2, and Dn2) with an input se-ries resistor (R1, R2) of 500 . Each polysilicon diode has a total perimeter of 250 m. The n-region has a width of 3 m between the p and n regions of the polysilicon diode. A gate-cou-pled nMOS with a device dimension ( ) of 300 m/2 m is also added into the chip across VDD and VSS power lines as the VDD-to-VSS clamp circuit for ESD protection. Such an nMOS has a breakdown voltage of 16.5 V. However, the HBM ESD level of this smart-card IC fabricated in a 0.8- m CMOS process is only around 300 V, especially on the pad1 pin with the polysilicon diodes which are fully isolated from the p-sub-strate. With an ESD level below 500 V, the die of smart-card IC assembled into the smart card by the COB bonding is very sus-ceptible to ESD events.
To improve the ESD level of the smart-card IC, a process split on increasing the doping concentration of the n-region in the polysilicon diode was investigated in the 0.8- m CMOS process. The increased doping concentration of the n-region can lower the breakdown voltage of the polysilicon diode, there-fore reducing the ESD-generated heat located on the
polysil-TABLE I
HBM ESD LEVEL OF ASMART-CARDICWITH THEORIGINALESD PROTECTIONDESIGNUNDERDIFFERENTn-DOPINGCONCENTRATIONS
icon diode. The experimental results are summarized in Table I, where the HBM ESD level of pad1 pin in VSS( ) test mode only varies from 150 to 300 V when the n-doping concentration is increased from 3E13 to 9E13 cm . Even in the VSS( ) ESD test mode, where the polysilicon diode is forward stressed, the HBM ESD level of pad1 pin only varies from 400 to 600 V. This is quite low for a diode with a perimeter of 250 m in forward-biased condition. The high turn-on resistance of the polysil-icon diode would limit the ESD current discharged through the polysilicon diode and cause ESD damage located on the internal devices.
The photo-emission microscope (EMMI) pictures of failure locations on the smart-card IC after the VSS( ) and VDD( ) ESD stresses are shown in Fig. 7(a) and (b), respectively. In Fig. 7(a) [Fig. 7(b)], the ESD failure is located on the nMOS (pMOS) gate oxide of the first input stage that connected to the pad1 pin through the resistor R1, rather than on the polysilicon diodes Dp1 or Dn1. The pMOS and nMOS in the 0.8- m CMOS process have a gate-oxide thickness of 250 Å. In this original design, the polysilicon diodes and the VDD-to-VSS ESD clamp circuit with gate-coupled nMOS cannot effectively protect the 250-Å gate oxide of the input circuits. The inefficiency of the original ESD protection design in Fig. 5 could be caused by the high trigger voltage (Vt1) of the VDD-to-VSS ESD clamp circuit, the parasitic resistance along the VDD/VSS power rails [3]–[5], or the high turn-on resistance of the polysilicon diodes. Therefore, simply changing the n-doping concentration cannot effectively improve ESD level of the pad1 pin in such a smart-card IC. A more efficient ESD protection design should be developed to overcome this problem in the smart-card IC with polysilicon diodes.
III. NEWON-CHIPESD PROTECTIONDESIGN
A. ESD Protection Circuit
To still apply the polysilicon diodes as the ESD protection devices at the pad1 pin, the concept of whole-chip ESD protec-tion by using a more efficient VDD-to-VSS ESD clamp circuit to significantly improve ESD level of the I/O pin [6]–[10] is ap-plied into this smart-card IC. The new proposed on-chip ESD protection circuit is shown in Fig. 8 with a novel VDD-to-VSS ESD clamp circuit [11], where the ESD protection circuit for the pad1 pin has two-stage protection diodes. The VDD-to-VSS ESD clamp circuit is formed by the nMOS Mn3 and its corre-sponding ESD-detection circuit. The gate of Mn3 is controlled by a stacked diode string, which is also realized by the
polysil-(a) (b)
Fig. 7. EMMI pictures showing the ESD failure location (indicated by the arrows) on the input circuits after (a) the VSS(+) test mode and (b) the VDD(0) test mode, HBM ESD stresses.
Fig. 8. New design of on-chip ESD protection circuit with a novel VDD-to-VSS ESD clamp circuit in the smart-card IC.
icon diodes. If the stacked diodes were realized by the p dif-fusion in the n-well in CMOS process with a common p-sub-strate, there was a significant leakage current on the order of milliamperes from VDD to VSS due to the parasitic vertical BJT effect in CMOS process [12]–[14]. But, when the stacked diodes are realized by the polysilicon layer, the leakage current can be reduced below 1 A under 5-V VDD bias. Therefore, the leakage current from VDD to VSS through the diode string and the resistor of 10 k in Fig. 8 can be designed smaller than 1 A, if the diode number in the stacked diode string is large enough. The detailed calculation to find the suitable number of stacked polysilicon diodes in the proposed VDD-to-VSS ESD clamp circuit has been derived in the Appendix.
For use in a smart-card IC with converted VDD power, eight polysilicon diodes are used in the diode string to control the gate voltage of Mn3, which has a device dimension ( ) of 300 m/2 m in the practical IC. When the VDD is charged no more than 5 V, the Mn3 is kept off. But when the VDD is charged up greater than 5 V, the Mn3 is turned on to clamp the VDD voltage level. By changing the number of polysilicon diodes in the stacked diode string, the clamped voltage level on VDD can be adjusted for different applications.
With the novel VDD-to-VSS ESD clamp circuit, the ESD current under the VSS( ) ESD stress is discharged through the forward-biased Dp1a to VDD, and then discharged through the turned-on Mn3 to VSS, rather than the breakdown of polysil-icon diode Dn1a. In the VDD ESD stress, the negative ESD
Fig. 9. Partial picture of a smart-card IC with the realization of ESD protection circuit on the pad1 pin and the VDD-to-VSS ESD clamp circuit.
current is conducted to VSS through the forward-biased Dn1a, and then discharged to the grounded VDD through turned-on Mn3, without causing breakdown on polysilicon diode Dp1a. The second diode stage with Dp1b and Dn1b is used to further clamp overstress voltage across the gate oxide of the input cir-cuits for safer ESD protection. A partial picture of a smart-card IC with realization of ESD protection circuit on the pad1 pin and the VDD-to-VSS ESD clamp circuit is shown in Fig. 9, where the polysilicon diodes of the pad1 pin are all drawn in the multiple-fingers style with a total perimeter of 300 m for each diode.
B. Leakage Current in the VDD-to-VSS ESD Clamp Circuit
The leakage current from VDD to VSS in the new proposed VDD-to-VSS ESD clamp circuit can be calculated to find the suitable number of diodes in the stacked diode string under different VDD voltage levels. The leakage current includes the subthreshold current of Mn3 and the diode string current. Be-cause the diodes are all realized by the polysilicon layer, there is no parasitic vertical BJT in these diodes. The leakage current in such polysilicon diode strings is not increased by the par-asitic vertical BJT effect [12]–[14]. This makes the proposed
Fig. 10. HSPICE simulated leakage current of the proposed VDD-to-VSS ESD clamp circuit with eight diodes in the stacked diode string under different resistance ofR3. (Y axis is drawn in log scale.)
Fig. 11. HSPICE simulated leakage current of the proposed VDD-to-VSS ESD clamp circuit with a fixedR3 of 10 k but different diode numbers (n) in the stacked diode string. (Y axis is drawn in log scale.)
VDD-to-VSS ESD clamp circuit to have a much lower leakage current in the IC normal operating condition.
When the diode string has eight stacked diodes ( ), the leakage current in the proposed VDD-to-VSS ESD clamp cir-cuit under different resistance of is simulated by HSPICE, and the results are shown in Fig. 10. When the has a higher resistance, the leakage current is slightly increased due to the greater subthreshold current of Mn3, or significantly increased if Mn3 is turned on. By changing the number of diodes in the stacked diode string, the leakage current of the proposed VDD-to-VSS ESD clamp circuit can obviously be reduced. The HSPICE simulated results between the leakage current and VDD voltage level under different diode numbers are shown in Fig. 11, where the is kept at 10 k . The -axis of Fig. 11 is drawn in log scale to more clearly distinguish the leakage current under different diode numbers. As seen in Fig. 11, the increase of diode number causes a smaller leakage current at a fixed VDD voltage level. For general IC specification, the leakage current should be smaller than 1 A. The turn-on
voltage (defined at A) can be found from the –
Fig. 12. Relation betweenV defined at I = 1 A and the diode number (n) of the VDD-to-VSS ESD clamp circuit underR3 of 10 or 100 k.
TABLE II
PROCESSSPLITS ON THEn-DOPINGCONCENTRATION TOINVESTIGATE THEBREAKDOWNVOLTAGE AND THEFORWARD-BIASEDCURRENT OF
THEPOLYSILICONDIODES
curves of Fig. 11. The relation between and the diode number under of 10 or 100 k is compared in Fig. 12. The increase of R3 resistance only causes a slight increase on the turn-on voltage , but the increase of diode number causes a significant increase on the turn-on voltage . The
turn-on voltage (defined as A) should be greater
than VDD of the IC to meet the leakage current specification of smaller than 1 A. The device dimension of Mn3 in these calculations (Fig. 10–Fig. 12) is fixed at 300 m/2 m. The leakage current is also increased if the device dimension of Mn3 is increased. For the IC applications in different CMOS process, the suitable diode number in the stacked diode string can be found by the equations in the Appendix or HSPICE simulation.
C. Process Splits
To choose a better doping concentration for the n-region in the polysilicon diode for smart-card application, a comprehensive process split with different implantation energy is investigated in Table II. If the n-region has a higher doping concentration or a higher implantation energy, the polysilicon diode has a lower breakdown voltage and a higher forward-biased current, which is better for ESD protection. But, because the transformer-cou-pled ac voltage could have a maximum voltage swing of 12 V, the breakdown voltage of polysilicon diode is selected to be
Fig. 13. (a) Device structure and (b) layout top view of the p+/p0/n+ polysilicon diode realized in a CMOS process.
TABLE III
PROCESSSPLITS ON THEp-DOPINGCONCENTRATION TOINVESTIGATE THEBREAKDOWNVOLTAGE AND THEFORWARD-BIASEDCURRENT OF
THEPOLYSILICONDIODES
greater than 12 V for safe application. Therefore, the split case of #n2 in Table II is suitable for use in this smart-card IC.
The polysilicon diode can also be realized with a p-type lightly doping region, as shown in Fig. 13(a) and (b). The process split is also used to investigate the characteristics of such a p /p /n polysilicon diode. The experimental results are listed in Table III, where the polysilicon diode has a layout spacing (the p-doping region) of 3 m. Due to the concern for the transformer-coupled maximum ac voltage swing of 12 V, the split case of #p2 in Table III is suitable for use in this smart-card IC.
IV. DEPENDANCE OFLAYOUTPARAMETERS ONIt2OF POLYSILICONDIODES
Although the process splits can find the optimized doping concentration for the lightly doped center region in the polysilicon diode, the ESD performance of the polysilicon diode can be further improved by suitably choosing its layout parameters. Under a fixed process split condition with the n-(of 1.5E14 cm ) doped center region, many polysilicon diodes
Fig. 14. MeasuredI–V curves of the p+/n0/n+ polysilicon diodes with a fixedW t of 300 m but different S spacings in a CMOS process.
are fabricated in a test wafer with different layout spacings of the lightly doped center region and different total perimeters
. A polysilicon diode with a large device dimension is drawn in the multiple-fingers layout style, in which every finger has a layout length of 30 m. For a polysilicon diode with a total perimeter of 300 m, there are ten fingers drawn in parallel in the device layout. The measured – curves of the polysilicon diodes with a fixed of 300 m but different spacings are shown in Fig. 14. The polysilicon diode with a narrower spacing has a smaller cut-in voltage in the forward-bias condition, and a smaller (in magnitude) breakdown voltage in the reverse-biased condition.
To further investigate ESD performance of the fabricated polysilicon diodes, the transmission-line-pulse (TLP) generator (according to the prior art of [15]) has been successfully set up with a pulse width of 100 ns [16] and used to measure It2 of the polysilicon diodes. The TLP-measured – curves of the polysilicon diodes with a fixed of 300 m but different spacings are shown in Fig. 15(a) and (b) in the forward-and reverse-biased conditions, respectively. The dependence of It2 on the layout parameter in both the forward- and reverse-biased conditions is summarized in Fig. 16. The TLP-measured – curves of the polysilicon diodes with a fixed spacing of 3 m but different total perimeters are shown in Fig. 17(a) and (b) in the forward- and reverse-biased conditions, respectively. The dependence of It2 on the total perimeter of the polysilicon diode in both forward- and reverse-biased conditions is compared in Fig. 18. A polysilicon diode with a wider perimeter also has a larger volume for heat dissipation, therefore it has a higher It2 value.
As seen in Fig. 16 and Fig. 18, the polysilicon diode in forward-biased condition has a much higher It2 value than it does in the reverse-biased condition. This is due to the different
power ( , the product of ESD current and the
operating voltage of device) generated by the ESD current on the polysilicon diode in the forward- and reverse-biased con-ditions. The diode in the reverse-biased condition has a higher operating voltage across itself than in the forward-biased condition. Therefore, the ESD current generates more
Fig. 15. TLP-measured I–V curves of the polysilicon diodes in (a) the forward-biased condition and (b) the reverse-biased condition, with a fixedW t of 300m but different S spacings.
Fig. 16. Dependence of the TLP-measured It2 on the layout parameterS of the polysilicon diodes in both the forward- and reverse-biased conditions.
heat on the polysilicon diode in the reverse-biased condition to cause a lower It2.
When the spacing increases in the polysilicon diode, the It2 is also decreased, even if the diode is stressed in the forward-biased condition. In the forward-biased condition,
Fig. 17. TLP-measured I–V curves of the polysilicon diodes in (a) the forward-biased condition and (b) the reverse-biased condition, with a fixed spacingS of 3 m but different total perimeters W t.
Fig. 18. Dependence of the TLP-measured It2 on the layout parameter
W t (total perimeter) of the polysilicon diodes in both the forward- and
reverse-biased conditions.
the power generated by ESD current on the polysilicon diode is mainly decided by the turn-on resistance of the diodes. A polysilicon diode with a smaller layout spacing has a lower turn-on (breakdown) resistance, therefore it has a relatively
higher It2 in the forward- (reverse-) biased condition. With well understood and detailed investigation on It2 of the polysilicon diodes under different bias conditions and layout parameters, ESD robustness of the smart-card IC can be effectively improved by arranging the polysilicon diodes to discharge ESD current in its forward-biased condition. This can be achieved by designing a more efficient VDD-to-VSS ESD clamp circuit into the chip, as that shown in Fig. 8. The efficient VDD-to-VSS ESD clamp circuit should have a fast turn-on speed and a low turn-on voltage to discharge the ESD current from VDD to VSS.
V. EXPERIMENTALRESULTS ANDDISCUSSION
A. ESD Test and Failure Analysis
The smart-card ICs with the polysilicon diodes and the new proposed ESD protection design in Fig. 8 have been fabricated. The polysilicon diodes realized with the n- or p-doped center regions can perform the desired circuit function for smart-card application. The HBM ESD test results of this new ESD protec-tion design with the polysilicon diodes of n- or p-doped center regions are listed in Table IV. While the polysilicon diodes are realized by the n- (p-) doped center region with a doping concen-tration of 9E13 (5E13) cm and a total perimeter of
m (under the spacing of m), the HBM ESD-sustained level of pad1 pin in the VSS( ) ESD test mode is improved to 3 kV (3.5 kV). In the VDD( ) ESD test mode, the HBM ESD-sustained level is improved to 4 kV (3 kV). In both the VSS( ) and VDD( ) ESD test modes, the smart-card IC with polysilicon diodes can sustain the ESD-stress voltage of greater than 4 kV. The HBM ESD level of this smart-card IC under the direct VDD-to-VSS ESD stress is also greater than 4 kV.
A picture showing the failure location on the smart-card IC with the p-doped polysilicon diodes after the pad1 pin is zapped with a 4-kV VSS( ) HBM ESD stress is shown in Fig. 19(a), where the ESD failure is located on the polysilicon diode Dp1a, rather than on the Dn1a or the gate oxide of input circuits. In Fig. 19(b), it shows that the ESD failure is located on the polysil-icon diode Dn1a, rather than the diode Dp1a, after the pad1 pin is zapped with a 4-kV VDD( ) HBM ESD stress. From the ESD failure analysis, it has confirmed that the ESD current is actually discharged through the polysilicon diodes in the for-ward-biased conditions. This is achieved by adding the turn-on efficient VDD-to-VSS ESD clamp circuit into the chip, as well as by reducing the parasitic resistance along the power rails, as shown in Fig. 8. The ESD test results have successfully veri-fied the proposed ESD protection design in the smart-card IC by using the polysilicon diodes as the ESD clamp devices.
Fig. 19. Pictures showing the ESD failure location (indicated by the arrows) on the smart-card IC with the p-doped polysilicon diodes after the pad1 pin is zapped with a 4-kV HBM ESD stress in (a) the VSS(+) and (b) the VDD(0) ESD test conditions.
The smart-card IC with n-doped polysilicon diodes has also been verified by the charged-device-model (CDM) ESD test in a socketed CDM tester. The maximum CDM ESD-sustained voltage level of the fabricated smart-card IC is 750 and 600 V in the positive and negative CDM stresses conditions, respectively. A picture indicating the ESD failure location on the smart-card IC with n-doped polysilicon diodes after a negative 700-V CDM ESD stress is shown in Fig. 20, where the ESD failure is lo-cated on the polysilicon diode Dn1a, not on the gate oxide of the first input stage. To sustain a higher CDM ESD level, the layout spacing of the lightly doped center region has to be reduced to lower the breakdown voltage and to decrease the ESD-generated heat on the polysilicon diodes. The polysilicon diode with a reduced spacing also has a smaller turn-on resis-tance to quickly discharge the ESD current. But the minimum breakdown voltage of the polysilicon diode in this smart-card application is limited to 12 V, due to the coupled maximum ac voltage. This requirement can be further achieved by arranging the polysilicon diodes into the multistage configuration [11],
Fig. 20. Picture showing the ESD failure location (indicated by the arrow) on the smart-card IC with the n-doped polysilicon diodes after a negative 700-V CDM ESD stress.
Fig. 21. Alternative input ESD protection design with the polysilicon diodes in a multistage configuration to achieve better ESD protection.
as shown in Fig. 21. The polysilicon diode in every stage has different layout spacing . The polysilicon diode close to the first input stage of the internal circuits has a narrower spacing , but the polysilicon diode close to the bond pad has a wider spacing . The resistance between every stage can be further reduced to improve CDM ESD level but without degrading its HBM ESD level.
B. Turn-on Verification
The – curve of the new proposed VDD-to-VSS ESD
clamp circuit with eight stacked n-doped polysilicon diodes is measured in Fig. 22. When the applied voltage across VDD and VSS is increased higher to bias the gate of Mn3 greater than its threshold voltage, the nMOS Mn3 is turned on to conduct current from VDD to VSS. So, the measured – curve in Fig. 22 has a sharp current increase when the applied voltage is greater than 5 V.
In order to investigate the turn-on efficiency of the polysil-icon diodes at pad1 (Fig. 8) with the help of the new proposed VDD-to-VSS ESD clamp circuit, a 0–8-V voltage pulse is di-rectly applied to pad1 with the VSS pin relatively grounded and the VDD pin floating. The original 0–8-V voltage pulse is gener-ated from a pulse generator with a pulse width of 4 s and a rise time of 10 ns, as the dashed line shown in Fig. 23. When such a voltage pulse is applied to pad1, it is clamped to the voltage level shown in Fig. 23. Because the polysilicon diodes of pad1 have a breakdown voltage around 12 V, the applied 8-V voltage does not cause any breakdown on the polysilicon diodes of pad1.
Fig. 22. Measured I–V curve from VDD to VSS of the new proposed VDD-to-VSS ESD clamp circuit with eight stacked n-doped polysilicon diodes.
Fig. 23. Measured voltage waveform at pad1 when a 0–8-V voltage pulse is applied to the pad1 with VSS grounded.
But, the 0–8-V voltage pulse is actually clamped to about 6.5 V in Fig. 23. This is due to the turn-on of the VDD-to-VSS ESD clamp circuit. Therefore, the overstress voltage on pad1 is dis-charged from pad1 to VDD through the forward-biased polysil-icon diode, and then discharged to VSS through the turned-on VDD-to-VSS ESD clamp circuit. This has successfully verified the effectiveness of the new proposed VDD-to-VSS ESD clamp circuit with stacked polysilicon diodes to significantly improve ESD level of the I/O pad.
VI. CONCLUSION
The device characteristics of the polysilicon diodes in CMOS process have been experimentally evaluated by process splits with different doping concentrations. The It2 of the polysilicon diodes under forward- and reverse-bias conditions and different layout parameters has been clearly investigated. The HBM ESD level of the smart-card IC with the polysilicon diodes as ESD protection devices has been successfully improved up to 3 kV in cooperation with a turn-on efficient VDD-to-VSS ESD clamp circuit. By adjusting the number of the stack diodes in the ESD detection circuit, the turn-on efficient VDD-to-VSS ESD clamp circuit can be applied in the IC with different VDD voltage levels. Such ESD-improved smart-card ICs have been in mass production with a large sale volume to offer smart-card manu-facturability without any ESD problem.
(a) (b)
(c)
Fig. 24. (a) ESD clamp circuit with stacked polysilicon diodes, and the equivalent circuits of (b) a diode, and (c) an nMOS, for model calculation.
APPENDIX
In Fig. 24(a), a diode string of polysilicon diodes is used to trigger the gate of nMOS. The equivalent circuit of each for-ward-bias diode is shown in Fig. 24(b), where the series resistor is the turn-on resistance of a polysilicon diode. The equiva-lent circuit of an nMOS is shown in Fig. 24(c) with the consid-eration of drain and source resistance, and , respectively. The current of each diode is
(A.1) The voltage drop on each diode ( ) is the same to each other. is the saturation current, is the thermal voltage, and the factor
generally has a value between 1 and 2. The total voltage drop across the stacked diodes and the resistor (connected between the gate of nMOS and VSS) can be expressed as
(A.2) where is the stacked number of diodes. This equation can be rewritten to find the as function of the gate voltage of nMOS as
(A.3)
where
(A.4) From the circuit connection of Fig. 8, the equals VDD. So, the number of stacked polysilicon diodes can be adjusted to reduce the total leakage current, when the IC is operating in normal condition. To limit the leakage current through nMOS, the gate voltage of nMOS has to be less than its threshold voltage
ESD clamp circuit can be expressed as
(A.6) where the leakage current through stacked polysilicon diodes can be obtained from (A.4), and the leakage current through the nMOS ( ) can be obtained from (A.5). Finally, the total leakage current ( ) can be further expressed as a function
of .
(A.7) where
(A.8) In these equations, the parameters of and are constant fac-tors for a CMOS process, and they are defined as
(A.9) and
(A.10) For a given CMOS process, the value of and can be deter-mined from process parameters.
From (A.3) and (A.7), the relation between and can be calculated with the specified factors of VDD, , diode pa-rameters, and nMOS dimension. First, some suitable series re-sistances are temporarily chosen to calculate the relation be-tween and from (A.3). The condition of choosing is considered to keep the gate voltage of nMOS smaller than its threshold voltage in the normal circuit operating con-dition. If nMOS is turned off, the leakage current will mainly appear through the diode string and resistor . For example,
when is smaller than 0.01 V, k can be chosen
to meet the condition of A. Secondly, the relation between gate voltage of nMOS and the total leakage cur-rent must be calculated to determine the exact value of
. From (A.2) and (A.4), the relation between , , and can be calculated. Using these values of , the total leakage current can be calculated from (A.7).
ACKNOWLEDGMENT
The authors would like to thank Sunplus Technology Com-pany, Ltd., Hsinchu, Taiwan, for the support to provide the test chips of the polysilicon diodes with different process splits.
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Ming-Dou Ker (S’92–M’94–SM’97) was born in Taiwan, R.O.C., in 1963. He received the B.S. degree from the Department of Electronics Engineering and the M.S. and Ph.D. degrees from the Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, in 1986, 1988, and 1993, respectively.
In 1994, he joined the VLSI Design Department, Computer and Communication Research Laborato-ries (CCL), Industrial Technology Research Institute (ITRI), Taiwan, as a Circuit Design Engineer. In 1998, he was a Department Manager in the VLSI Design Division of CCL/ITRI. Since 1994, he has also been a Research Advisor in the Integrated Circuits and Systems Laboratory, National Chiao-Tung University. In 1999, he became an Assistant Professor in the Department of Electronics Engineering, National Chiao-Tung University. In the field of ESD/latch-up in CMOS technology, he has published over 80 technical papers in international journals and conferences. He holds 30 U.S. patents on on-chip ESD protection design. He has been invited to teach or consult ESD protection design by more than 70 IC design houses or semiconductor companies in the Science-Based Industrial Park, Hsinchu, and in Silicon Valley, San Jose, CA. He has also served as a Member of Technical Program Committee in some international conferences and the EOS/ESD Symposium.
Tung-Yang Chen (S’00) was born in Taiwan in 1967. He received the B.S. degree from the Depart-ment of Physics, National Chung-Hsing University, Taichung, Taiwan, R.O.C., in 1991. He received the Master’s degree from the Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, in 1997. He is currently working toward the Ph.D. degree at the Institute of Electronics, National Chiao-Tung University.
He was on active duty at the Information Center of C.C.K., Taichung, Airforce of R.O.C., from 1991 to 1993. His work involved system analysis, system design, program coding, and maintenance of computer systems. His current research interests include ESD physics, semiconductor devices, and ESD protection design in deep-submicron CMOS technologies.
Tai-Ho Wang was born in Taiwan in 1967. He received the B.S. degree from the Department of Electrical Engineering, National Cheng-Kung Uni-versity, Tainan, Taiwan, R.O.C., in 1990, and the M.S. degree from the Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, in 1992.
In 1992, he joined the Electronics Research and Service Organization (ERSO), and in 1996, he joined the Computer and Communication Research Labora-tories (CCL), Industrial Technology Research Insti-tute (ITRI), Taiwan, as a Reliability Engineer. Since 1998, he has been Assistant Manager in the Department of Product Engineering, Sunplus Technology Company, Hsinchu. His research interests include relia-bility of ESD/latch-up, CMOS device reliarelia-bility, product engineering, failure analysis, and new process development with foundry companies. He has three patents in the field of semiconductors.
Chung-Yu Wu (M’88–SM’96–F’98) was born in 1950. He received the M.S. and Ph.D degrees from the Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., in 1976 and 1980, respectively.
From 1980 to 1984, he was an Associate Professor with the National Chiao-Tung University. During 1984–1986, he was a Visiting Associate Professor in the Department of Electrical Engineering, Portland State University, Portland, OR. Since 1987, he has been a Professor with the National Chiao-Tung University, where he is the Centennial Honorary Chair Professor. From 1991 to 1995, he served as Director of the Division of Engineering and Applied Science with the National Science Council. He has published more than 200 technical papers in international journals and conferences. He also has 18 patents, including nine U.S. patents. Since 1980, he has served as a Consultant to high-tech industry and research organizations, and has built up strong research collaborations with high-tech industries. His research interests focus on low-voltage low-power mixed-mode circuits and systems for multimedia applications, hardware implementation of visual and auditory neural systems, and RF communication circuits and systems. He is the Distinguished Lecturer of the CAS Society and one of the society representatives in the Neural Network Council. He has served on the Technical Program Committees of IEEE ISCAS, ICECS, APCCAS. He served as the VLSI Track Co-Chair of the Technical Program Committee of ISCAS’99, and General Chair of IEEE APCCAS’92. He also served as the Chairs of Neural Systems and Applications Technical Committee and Multimedia Systems and Applications Technical Committee of the IEEE CAS Society. He was one of the society representatives in the Steering Committee of IEEE TRANSACTIONS ONMULTIMEDIA. He served as a Guest Editor of the Multimedia Special Issue for IEEE TRANSACTIONS ON
CIRCUITS ANDSYSTEMS FORVIDEOTECHNOLOGYin August/October, 1997. He also served as an Associate Editor for the IEEE TRANSACTIONS ONVLSI SYSTEMSand IEEE TRANSACTIONS ONCIRCUITS ANDSYSTEMS—II. Currently, he is an Associate Editor of the IEEE TRANSACTIONS ONVLSI SYSTEMSand IEEE TRANSACTIONS ONMULTIMEDIA.
Dr. Wu was a recipient of the IEEE Third Millennium Medal, the Outstanding Academic Award by the Ministry of Education in 1999, the Distinguished Researcher in 1999 and the Outstanding Research Award in 1989–1990, 1995–1996, and 1997–1998 by the National Science Council, the Outstanding Engineering Professor Award by the Chinese Engineer Association in 1996, and the Tung-Yuan Science and Technology Award in 1997. He is a member of Eta Kappa Nu and Phi Tau Phi Honorary Scholastic Societies.
