高速音圈馬達位置控制之FPGA晶片研製

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(2) FPGA

(3) Design and Implementation of a FPGA Position Control Chip for a High Speed Voice Coil Motor. .

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(11) FPGA Design and Implementation of a FPGA Position Control Chip for a High Speed Voice Coil Motor. É |ÊË. : Wt. Student Advisor. É É. ¢ÌÍÎÏ ÐÑ"ÒÓkÔ t^_ A Thesis Submitted to Department of Electrical and Control Engineering National Chiao Tung University in partial Fulfillment of the Requirements for the Degree of Master in Electrical and Control Engineering June 2007 Hsinchu, Taiwan, Republic of China. Õ{¢Ö×ØØÙ. Po-Ming Wu Dr. Shir-Kuan Lin.

(12) FPGA

(13) : !"#$%& '(#) f^_)Ú5ÛÜÝÞßàáâ (FPGA) ãäåæçèéêdßà ãä" Nios II ë@ìeíîï FPGA ãä)ðñòóôõöZd÷ ÒÓêdßàãäø)ùúûüýþðñÿ êdì (A/D Converter) )*êdÿ ì (D/A Converter) Nios II ë@ ìø) C ýþðñóôõöZò2 PI ÒÓìQd÷ P ÒÓì)*d÷.

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(15) Design and Implementation of a FPGA Position Control Chip for a High Speed Voice Coil Motor. Student : Po-Ming Wu. Advisor : Dr. Shir-Kuan Lin. Department of Electrical and Control Engineering National Chiao Tung University. ABSTRACT In this thesis, a FPGA(Field Programmable Gate Array)-based Chip design is taken to implement a position control chip conceptual core for high speed voice coil motor(VCM) drive, and the control chip integrate digital logic IC and Nios II processer in single FPGA chip. The function of the digital logic IC includes analog/digital Converter and digital/analog Converter. And the function of Nios II processer includes speed-loop proportional-integration(PI) controller, position-loop proportional controller, ane position estimation algorithm. As for the experimental setup and related system collocation, it is construct from the Altera Cyclone II Nios II development board of the core concept for controlling a VCM, and peripheral circuit boards for motor drive, signal regulate, signal sample,and signal output function. Besides, it demonstrates the effectiveness of the proposed FPGA-based control system for the performance improvement for VCM drive can be achieved by adjustment of the conreol parameter and measurement and analysis of experimental data. The results of this study, the responsed time needs about 60. U 80 ms with the. 10% steady-state error; the 10% steady-state error is caused form the defects of the magnetic scale such as the variations of the amplitudes of the MR sensor signals. The maximum current consumption of the VCM in this study is about 30 milliampere (mA), this advantage can save more battery energy of the DVC.. ii.

(16) . i. . ii. . ii. . v. . viii.

(17) 1.1 1.2 1.3. 1. ½Ñ"7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6"ÔVü . . . . . . . . . . . . . . . . . . . . . . . . . . . ^_' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2.1 2.2 2.3. 1 2 3. 4. óôõöWdÒÓ' . . . . . . . . . . . . . . . . . . . . . . . . . XÔ' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . YZ[\]*^3 . . . . . . . . . . . . . . . . . . . . . . . . . iii. 4 4 6.

(18) 7_ 2.4. iv. Ô34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 8. 10. 3.1. Ôà. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10. 3.2. ALTERA Nios II Development Board . . . . . . . . . . . . . . . . . . .. 11. 3.3 3.4 3.5 3.6. 3.7. 3.8 3.9. óôõöÁ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bc±ì . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . @I ë@Ð$ . . . . . . . . . . . . . . . . . . . . . . . . . ÿ êdÐ$ (A/D Converter) . . . . . . . . . . . . . . . . . . . . 3.6.1 AD7896 ZdeJ"5fg . . . . . . . . . . . . . . . . . . êdÿ Ð$ (D/A Converter) . . . . . . . . . . . . . . . . . . . . 3.7.1 AD5445 Z5fg"½ehO . . . . . . . . . . . . . . . . . . A/DQD/A Converter Zð !"ij . . . . . . . . . . . . . . . . . óôõö½Ð$ . . . . . . . . . . . . . . . . . . . . . . . . . . . .. !"#$%& 4.1. 4.2. kú\]lmà . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 ãä\]kú -Quartus II . . . . . . . . . . . . . . . . . . . . 4.1.2 Nios II në@ì\]kú -SOPC BuilderQNios II IDE . . . Nios II ë@ìÝÞ . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 ij]êop . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 óôõöd÷]

(19) . . . . . . . . . . . . . . . . . . . . . . . .. ' ()$*+,-!./01 5.1. ÔX'. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13 14 15 16 18 19 21 22 23. 24 24 24 25 29 30 31. 36 36.

(20) 7_ 5.2 5.3. v. ÒÓì . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ðÁÂ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PI. 2 ,$3456 6.1 6.2. Á^ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . q\rs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 38 40. 43 43 44.

(21) 1.1 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 3.1 3.2 3.3 3.4 3.5 3.6 3.7. 3.8. Ô'tug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vÒwxg [16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . y PI ÒÓX' [16] . . . . . . . . . . . . . . . . . . . . . . . . Ôz{YZ| ìÒÓX' [16] . . . . . . . . . . . . . . . . YZ| ì}5xg [3] . . . . . . . . . . . . . . . . . . . . . . . . MATLAB ~XÔ1¾YZ[ [16] . . . . . . . . . . . g (A) åd÷ 5mm Ô34g (B) åL# Ïg [16] ÷ PI ÒÓÔD 3mm d÷ÒÓ34g [16] . . . . . . ÷z{YZ| ÒÓÔD 3mm d÷ÒÓ34g [16] Ôùú'g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ôðúg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nios II Development Board Ð$ðúg . . . . . . . . . . . . . . . . . Nios II Development Board Ð$'xg . . . . . . . . . . . . . . óôõöÁtug . . . . . . . . . . . . . . . . . . . . . . . . . . . bc±ìÐ$g . . . . . . . . . . . . . . . . . . . . . . . . . . . bc±ìrZij ( gåZrgå Zr ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ë@Ð$ . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi. 2 5 5 5 6 7 7 8 8 10 11 12 13 14 14. 15 15.

(22) gF7_ 3.9 ë@Ð$Z!"ij . . . . . . . . . . . . . . . . . . . . . 3.10 AD7896 Ð$g . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11 AD7896 d"xg . . . . . . . . . . . . . . . . . . . . . . .. vii 16 16 17. 3.12 Mode 1 Timing Operation Diagram for High Sampling Performance . .. 18. 3.13 Data Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 19. Ð$g . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.15 AD5445 d"xg . . . . . . . . . . . . . . . . . . . . . . . 3.14 AD5445. 3.16 AD5445 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .. Q Zð !"ij . . . . . . . . . . . . . . . . . 3.18 óôõö½Ð$tug . . . . . . . . . . . . . . . . . . . . . . . . 3.19 óôõö½Ð$!"ij . . . . . . . . . . . . . . . . . . . . . . 3.17 A/D D/A Converter. 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.1 5.2 5.3 5.4. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . System dependency page C . . . . . . . . . . . . . . . . . . . . . . . System Generation C . . . . . . . . . . . . . . . . . . . . . . . . . . Nios II IDE `C . . . . . . . . . . . . . . . . . . . . . . . . . . . ij]êopJNg . . . . . . . . . . . . . . . . . . . . . . . . x,g [16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A¨g [16] . . . . . . . . . . . . . . . . . . . . . . . . . . . i"A<=¨g [16] . . . . . . . . . . . . . . . . . óôõöd÷]

(23) JNg . . . . . . . . . . . . . . . . . . . . . System Contens. óôõöd÷ÒÓxg . . . . . . . . . . . . . . . . . . . . . . . . g (A) åd÷ 1mm Ô34g (B) åL# Ïg . . PI ÒÓìxg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Jde`C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 20 20 22 22 23 23 27 28 28 29 30 31 32 32 35 37 37 39 40.

(24) gF7_ 5.5 g (A) å ÷ PI ÒÓÔD 4mm d÷ÒÓ34gg (B) åL# Ïg . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 g (A) å ÷ PI ÒÓÔD 0.2mm d÷ÒÓ34g g (B) åL# Ïg . . . . . . . . . . . . . . . . . . . . . . . . . .. viii. 41. 42.

(25) 2.1 2.2 3.1 3.2 3.3 3.4 3.5 5.1. ÒÓÔcd÷ÒÓ34Ý0 . . . . . . . . . . . . . . . z{YZ| ìÒÓÔcd÷ÒÓ34Ý0 . . . . . . PI. ãäÝ . . . . . . . . . . . . . . . . . . . . . . . AD7896 cd0 . . . . . . . . . . . . . . . . . . . . . . . . . . ÿ êd0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AD5445 cd0 . . . . . . . . . . . . . . . . . . . . . . . . . . êdÿ 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EP2C35F672C6ES. fðñZ PI ÒÓÔcd÷ÒÓ34Ý0. ix. . . . . . .. 9 9 11 17 18 21 21 42.

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(33) 6 (Position Estimating Algorithm) \]

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(53) 6 (Position Estimating Algorithm) \]

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(55) ê 3 ë Ôùú'*x@à. 11. 3.2: ;: 3.2. ALTERA Nios II Development Board. f^_)Ú5ÛÜÝÞßàáâ (FPGA) ãäåæçèéêdßàãä " Nios II ë@ìeíîï FPGA ãä)ðñòóôõöZd÷ÒÓ ÔðñJ4 ALTERA Nios II Development Board åö\] rJK9rsóG FPGA ãäÛå Cyclone II EP2C35F672C6ES ?ï FPGA ãä4) 672 Id Fin eline BGA K±&LÝ0G 0 3.1 tK 5 3.1: EP2C35F672C6ES <=78 Ý Feature EP2C35F672C6ES ßàí Logic elements(LEs) 33,216 M4K RAM blocks (128 x 36 bits). 105. LMNúdê Total RAM bits. 920,448. Embedded 18x18 Multiplier Blocks. 35. O$ PLLS User I/O pins. 4 475.

(56) ê 3 ë Ôùú'*x@à 12 g 3.3å Nios II Development Board Ð$ðúgKîï FPGA ãä*î !":PÉ Flash memoryK 2. 2MBytes synchronous SRAMK 3. 32MBytes DDR SDRAMK 4. î Ethernet MAC/PHY ±÷" RJ45 Ã)QR$<STý!K 5. î Compact Flash(CF) Ã*îx 32MB CF CardK 6. î Mictor ÃÜ§¯kùúUK 7. î RS232 ÃÜ)VfâWK 8. ïXY"Zï LED V8 FPGA !"K 9. [\]tìK 10. JTAG ÃGJÜ()ý!~^8 FPGA ±÷K 11. îj 50MHz _àbìK 1. 16MBytes. 3.3: Nios II Development Board >?;:.

(57) ê 3 ë Ôùú'*x@à 13 ?cD\]dãäú"U,Ôe!Ù`C*%´ fghye67ãär5®KLÐ$'xgGg 3.4 tK. 3.4: Nios II Development Board >?

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(59) ê 3 ë Ôùú'*x@à. 14. 3.5: @ABCD 3.4. )*+,. bc±ìLöåij]êopH±óôõöZÿ½ 4m÷ö¯§®ZÝLÛå SG-290Ð$Gg 3.6 tÆóôõöZÿ½ ÷ö¯§®ZÝbc±ìÞªî j)ød8»ødZrrZijGg 3.7tK. 3.6: EFG>?HI.

(60) ê 3 ë Ôùú'*x@à. 15. 3.7: EFGJKLMNOP ( Q$RSNJKLMTU$VSNJ KLM ) 3.5. -./0123456. @I ë@Ð$ö4D@I ì!"§¯døè ø ì!""L!"n+§¯ .ø¡Ldøè8 0V() Ï*4iÐ$4Lo¬b Ï¡L()dø èGL Ï«,-åÿ êdÐ$ (A/D Convert er) !Üv Ð+,-LÐ$'Gg 3.8ty9ë@Ð$Ü)è n+dø*¡LÏMb4o¬L!"ijGg 3.9tK. 3.8: WLMXY>?.

(61) ê 3 ë Ôùú'*x@à. 16. 3.9: WLMXY>?NZ[OP 3.6. 7#8956 (A/D Converter). ÿ êdÐ$ (A/D Converter) ö4ødøè«Z@I ì !"§¯ÿ !båÜp Nios II në@ìqêd)L IC Ûå AD78964îï õò©£2å 12 drâJÿ êd ICÿ êdZòså 100KHz( t: 10 uvST )ÿ !,-å 0V 8 5 .5Vÿ &êd5®å 8 n:STq"ý !årâjJLÐ$Gg 3.10tK. 3.10: AD7896 >?HI.

(62) ê 3 ë Ôùú'*x@à 17 AD7896 w¹ 8 j Pin g 3.11å AD7896 d"xgcd hOG0 3.2tK. 3.11: AD7896 \%]^_

(63) 5 3.2: AD7896 6\%^_5 Pin No.. Description. 1 (VI N ). Analog input.The analog input range is 0V to VDD .. 2 (VDD ). Positive supply voltage. 2.7V to 5.5V.. 3 (AGND). Analog ground.. 4 (SCLK). Serial clock input.. 5 (SDATA). Serial data output.Serial data from AD7896 is provided at this output.. 6 (DGND). Digital ground.. 7 (CONVST) Convert start.Edge-triggered logic input. 8 (BUSY). The BUSY pin is used to indicate when the part is doing a conversion.. )e AD7896 4 12 dÿ êd IÇ9.ÿ !,-å 0V 8 3.3V«êd)Ltîdxå 0.81mV(3.3V/4096)0 3.3å AD7896 Zÿ êd0K.

(64) ê 3 ë Ôùú'*x@à. 18. 5 3.3: àb%cd5. 3.6.1. AD7896. Analog Input. Code Transition. 3.299194V. 111...110 to 111...111. 3.298389V. 111...101 to 111...110. 3.297583V. 111...100 to 111...101. 0.002417V. 000...010 to 000...011. 0.001611V. 000...001 to 000...010. 0.000806V. 000...000 to 000...001. !78(9$:;. w¹ÙdeJÉ(1) High Sampling Performance(2) Auto Sleep after ConversionfydeJå High Sampling PerformanceL 5fgGg 3.12t½ehOG~É AD7896. Æÿ !)«G CONVST d) high / lowAD7896 z7 K 2. 95 BUSY d) low / highz7§¯>#Ú5 8 n:ÆS T%{BUSY d) high / lowK 3. SCLK |" 16 jiz7§¯râqST½eK 1.. 3.12: Mode 1 Timing Operation Diagram for High Sampling Performance.

(65) ê 3 ë Ôùú'*x@à 19 AD7896 STqårâjJL5fgGg 3.13t½ehOG ~: |" 16 jiw,å[ 4 ji)*« 12 jij#À [jiå}STø~5®K 2. « 12 jiå SDATA etji|"îjdST)ªd ýK 3. L5!"då Tri-StateK 1. SCLK. 3.13: Data Read Operation 3.7. 987#56 (D/A Converter). êdÿ Ð$ (D/A Converter) ö4}\1e Nios II në@ ì«

(66) «êd)båÿ !"8óôõö½Ð$L IC Û å AD54454îïß¹o©£2å 12 dbâJêdÿ IC LÐ[e4,-å 2.5V 8 5.5V]Ð+,-Üö -10V 8 +10VSTq "ý!åbâjJ4îï·eGbâ`C (Parallel interface) êdÿ ICLÐ$Gg 3.14tK.

(67) ê 3 ë Ôùú'*x@à. 20. 3.14: AD5445 >?HI w¹ 20 j Pin g 3.15å AD5445 d"xgcd hOG0 3.4tK AD5445. 3.15: AD5445 \%]^_

(68) .

(69) ê 3 ë Ôùú'*x@à. 21. 5 3.4: AD5445 6\%^_5 Pin No.. Description. 1 (IOU T 1). DAC current output.. 2 (IOU T 2). DAC analog ground.. 3 (GND). Ground pin.. 4-15 (DB11-DB0) Parallel data bits 11 to 0. 16 (CS). Chip select input.Active low.. 17 (R/W). Read/Write pin.. 18 (VDD ). Positive power supply input. 2.5V to 5.5V.. 19 (VRE F ). DAC reference voltage input terminal.. 20 (RF B ). DAC feedback resistor pin.. AD5445. 4 12 dêdÿ ICL!"Ð+"]Ð+¨Jå : VOU T = (VRE F · D/2n−1 ) − VRE F. (3.1). L D å Input DataD=0 to 4095(12-bit AD5445)n=120 3.5 å AD5445 Zêdÿ 0K 5 3.5: b%àcd5 Digital Input. Analog Output. 1111 1111 1111 +VRE F (2047/2048). 3.7.1. ~:. AD5445. AD5445. 1000 0000 0000. 0. 0000 0000 0001. -VRE F (2047/2048). 0000 0000 0000. -VRE F (2048/2048). !:;$<8=>. STqåbâjJL5fgGg 3.16t½ehOG.

(70) ê 3 ë Ôùú'*x@à 22 1. Æ CS d" R/W d5å low ød5AD5445 z7qbâST (Parallel data) bøST Input LatchK 2. Æ CS då low ødR/W då high ød5AD5445 q DAC ì>¶)b&ÿ !"K. 3.16: AD5445 Timing Diagram 3.8. :. A/D D/A Converter. ;<0=>?@. g 3.174G* AD7896 )* AD5445 deZ5fgy Quartus II \]k úJZð a!"ijLtiì Channel 1 åªìª Zÿ ![Channel 2 å( A/DQD/A «!"Zÿ K. 3.17: A/DeD/A Converter N;Z[OP.

(71) ê 3 ë Ôùú'*x@à 3.9. A56. 23. óôõö½Ð$öåø D/A Converter !"ÿ ÒÓ §¯ Ï)e D/A Converter !"ÒÓåÔeÒÓÐ+Ï Mµ ®6ªÐNDóôõöô§¯½¸9yø Ïì \]åÐ+ÈìjJQªÏÐN!"ì (BUF634) ª ½ÐNDóôõöô'§¯½LÐ$tugGg 3.18 t!"ijGg 3.19tK. 3.18: @ABCfg>?. 3.19: @ABCfg>?Z[OP.

(72) + !,-./0 BCDE&'. 4.1. zrèjÔG÷kúå Quartus II èéAzrk úQNios II në@ì\]kú SOPC (System on a programmable chip)Builder ) * Nios II IDE(Integrated Development Environment)KLQuartus II kúö 4rs FPGA ãä5§¯JQàQãäúX*~ ^Þ)eLß¹ïÏèéÏAãäxÛ\]5Úeé& "5f,-}úãä5½eÜ Quartus II kúö&9: Quartus II ~ SOPC Builder kú Ü)ÝÞ"îï Nios II në@ì b"LxeVÁGÌèj\]3!Âb©¹3jAK Nios II IDE 4î \]d C/C++ Jýþb©à_8 Nios II në@ìkúK 4.1.1. ?@%&A -Quartus II. 4î ALTERA ÔzrkßkúÜ÷êXu Ó PLD õòàKb©¹ MAX+Plus II Ïy?kú\]d Quartus II. 24.

(73) ê 4 ë ÔZÝÞ"\] 25 %&Ü)A\]gQùúûüýþQÝÞVÁ_Q÷XeÊ51, -}keK Quartus II kúzrãäN,å\]!Qßàé&Q" QXQ5f,-QJÂ"~^ÝÞ}¦Lkúde6üG~É gÌÖhb\WGZ FPGA rsóÛK 2. §¯JÜùúûüýþG Verilog HDLQVHDL% &cjÝÞb!"åxggÌª,xg (*.bdf)bø¹Âxe"!!"V%&èj ãä\]K 3. øx!!"d" FPGA rsóÜÝÞdÝ ed \W½e)ÞDãä§¯ðúúK 4. z7§¯àGf%&ßàé&Q"QX*5f,½eà®<«ÞªîjÜ~^8 FPGA ãä>#^ (*.sof)é&"\ßàÓVJÜ) RTL Viewer \|)ú LÝÞJ4mØéÚ¬K 5. FPGA ðúú)[ÜDÖh<!!"ijXg% &ú75|ßà^3K 6. ijXú®<«ÞÜøJ~^8 FPGA §¯>ßàÓÝÞ bI* FPGA rsó,Ýtiì\úãäK 1.. 4.1.2. Nios II. BCD%&A -SOPC BuilderENios II IDE. åÔÜJãä, (System on a programmable chip) 6 K 9\]J4øßàÐ$QMNúQ IP "¡në@ì îjÜJ ßà ,KÜ)¢¹£6\]dõòzrª¤Û\]KALTERA Excalibur Ôâ¥4ønë@ì)kúÝùúJ÷Üãä ª"4 Nios ÔâÔenÒÓì Software IPÜQ]ê\ WÜ{\]dßàí:¦Ü)5÷!jnÒÓìî SOPC.

(74) ê 4 ë ÔZÝÞ"\] 26 à«Ì_³Ü~^÷ Nios rsó,zr4§¯úKALTERA Ôe\]Nzrª¹ SOPC Builder Quartus II kùú¦zrkßK 6þZSOPC Builder §4îgjÂkßkú¢\]dÜ)à¶·\ ]"78ÔãäÏÏ¨æ©\],ª«5®K SOPC Builder Ôrskß6Â¬A SOPC(System on a programmable chip) \]®Ky SOPC BuilderÔ\]dWFðñ %èÔKª5® ý SOC(System on a chip) \]7!K SOPC Builder " Altera Quartus II kúèéî FPGA \]dÌ³Ì ¯ArskßK SOPC Builder ST<&°É ë@ì (Processors)K 2. ±²³ª´ (IP) K 3. MNú`CK 4. ÎµK 5. ¶`C° Avalon ¶ AMBA 5¶ (AHB)K 6. êdë@ (DSP) K 7. kú K 8. 8FhK 9. ýþ½ìK 1.. Q SOPC BuilderÈÜ)DÚ¬y·në@ìFG ARM based CPU Ý ALTERA Nios CPULMy·N¶¸ì (Bridge) FG AHB to Avalon Bridge?kú;ÔeîcÎ¹ IPG SPIQUARTQ AHB EthernetMAº}LÄGMNúÒÓìMNú}Æ¸y·«»¼ {)\W¨]êö÷1½@£Ô1K%&«SOPC Builder Ü I*?c1]ê1½ªD4 VHDL Ý Verilog ùúûüýþJ ¾K.

(75) ê 4 ë ÔZÝÞ"\] 27 \]dÜ)z: Quartus II projecty5yí Tools SOPC Builder \z: SOPC Builder 5LG`C°~âÙCÉSystem Contens CQSystem dependency page C" System Genera tion CKÙChO G~É CÉ9C\WFÔ>¶Gg 4.1t¿C module pool â"¹ST< ¿C0â"4\] dy·Ô K. 1. System Contens. 4.1: System Contens hi CÉÆÀ{Á 8\]Ô5FGî j Flash memoryîjÀCÜ"ñ SOPC BuilderK?cC ¢ÇI*Ô \W]êKFGÇÜ)Ý, CPU "MNúZ ®¨¹ÂcMNú4eåJMNú¹ÂcMNú4eåST MNúGg 4.2 tK. 2. System dependency page.

(76) ê 4 ë ÔZÝÞ"\]. 28. 4.2: System dependency page hi CÉ9Cö4\ªÔÔª 9CÜÃ_ÔªÄGg 4.3tK. 3. System Generation. 4.3: System Generation hi.

(77) ê 4 ë ÔZÝÞ"\] 29 Æ\]dy SOPC Builder ÝÞ%îï Nios II në@ìb©"L xeVÁ)«ÞÜz: Nios II IDE 5 C/C++ Jýþb©à _8 Nios II në@ì§¯úL`CGg 4.4tK. 4.4: Nios II IDE jki 4.2. Nios II. 34,FGHI. fÝÞZ Nios II ë@ìö4y@I ìþóôõöÿ½ ½5ªI*kúJd÷

(78) 6\]

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(90) ÒÓì# À 4) FA,ÒÓì\DÔ§¯ÒÓK 4.2.1. FGHIJK. ij]êopJNgGg 4.5tÆ:½Å7Âij]êop N« ªîj8º¾Gõö ½÷7É ÷7 bc±ìÊr«J³/½Ð+Gõöªiº.Ë ½÷Ì2 ¯ÍÎªîj8º¾Gõö ÷7ÁÏÅ7Â ij]êopNK ½D@I ì ý§¯Ã_, -l)HÌHp"Ôij]ê¡LZªÏªM)yH ÌªÏªM)¨

(91) "ii"in+*¡LK. 4.5: OPlbmnopqo.

(92) ê 4 ë ÔZÝÞ"\]. 31. LMNOPQ&R. 4.2.2. Æ¯%ij]êopHÌii"in+*¡L«¤§ ¯WdÒÓy A/D Converter ¯±Ð7[@I ìii "ib()J 4.1J 4.2øL§¯8øÂGÐ÷ii* iL,-Ñ -1 * +1 Z®K xN A (n) =. xA (n) − bA XA. (4.1). xN B (n) =. xB (n) − bB XB. (4.2). L x åÐib åin+X åi¡L x åÐb ån+X å¡LK yii"i®ijd= 90 2ÏAÈÜ)ø8øÂ @I ,åj®Gg 4.6t)ii"irÍ CDÏM)eågWx,Hp8øK A. A. A. B. A. A. 4.6: r st [16].

(93) ê 4 ë ÔZÝÞ"\]. 32. √ 1/ 2 ⇒ REGION 1 √ xN A (n) ≥ 1/ 2 ⇒ REGION 2 √ xN B (n) ≤ −1/ 2 ⇒ REGION 3 √ xN A (n) ≤ −1/ 2 ⇒ REGION 4. xN B (n) ≥. yi®D¨ÜDÿ½ d÷§¯

(94) Ò\Íi BA@kj@2 (pole pitch) å 0.88 mm 1½D2Ü ½#Àt ½îjx û0ðÓ 0.22 mm7[x ½+ Di §¯AJ\]

(95) LA¨gGg 4.7ti"A <=¨gGg 4.8tK. 4.7: Iuvwxy [16]. 4.8: zO]Iuvw{I|}xy [16].

(96) ê 4 ë ÔZÝÞ"\] 33 )g 4.8ÜÈ()øi)AJ§¯d÷]

(97) LªÏ<=+ xri8 26 2zLÏMxå 5.3x10 Ô@kj@®K (pole pitch) Æ@kj@®K¥Õ ()AJ]

(98) "ðd÷øÜ3{ øÅK 9:Æÿ½ de75@I ìªjiÛ D¨b¯ÜÖ4deWF®7¸9]

(99) õöð d÷5×ÜG]

(100) "d÷Sªn +Èø9n +\Wå P D7de¯ REGION Ç1Lÿ½ P Ü()~â J¬ÌÉ −3. os. os. REGION 1 : √ pole pitch Pos = + 82 · pole pitch · xN A (0) 8 REGION 2 : √ pole pitch Pos = − 82 · pole pitch · xN B (0) 8. (4.3). REGION 3 : √ pole pitch Pos = − 82 · pole pitch · xN A (0) 8 REGION 4 : Pos =. √ pole pitch 2 + 8 8 · pole pitch · xN B (0). ]

(101) "7d÷n +«§Ü)()]

(102) é(xê (pass region) *7[xd "7d÷e .ÞÜ].

(103) ê 4 ë ÔZÝÞ"\]

(104) "7[ÿ½ d÷ D(n)GJ 4.4tÉ. 34. REGION 1 ÿ½ d÷ √ pole pitch D(n) = − Pos + 82 pole pitch · xN A (n) + PR 8. REGION 2 ÿ½ d÷ D(n) =. √ pole pitch 2 − P − os 8 8 pole pitch · xN B (n) + PR. (4.4). REGION 3 ÿ½ d÷ √ pole pitch D(n) = − Pos − 82 pole pitch · xN A (n) + PR 8. REGION 4 ÿ½ d÷ √ pole pitch D(n) = − Pos + 82 pole pitch · xN B (n) + PR 8. L PR =. pole pitch · pass region 4. (4.5).

(105) ê 4 ë ÔZÝÞ"\] 35 Q,ü¦³Ü]

(106) "ÿ½ 7[d÷ D(n)LJNgG g 4.9tK. 4.9: @ABC%&~opqo.

(107) 1 !234567,89:; 5.1. . MATLAB Xy MATLAB Simulink gÌóôõ öZò2 PI ÒÓìQd÷ P ÒÓìb¦(!Æed÷û0 ^H&'Zd÷)LvÒw P (s) ZêÛG 5.1JtÔZÒÓ xgGg 5.1tK n. Pn (s) =. 0.4145 (0.0012s + 32.8)(0.0018s + 0.005). 36. (5.1).

(108) ê 5 ë ÔX"ðÁÂZ,- .. 5.1: @ABC%&

(109) @:5 1mm d¦(÷~g 5.2å PI ÒÓÔZd÷34K. 5.2: (A) $%&'( 1mm )*+, (B) $-./01. 37.

(110) ê 5 ë ÔX"ðÁÂZ,- . 5.2. PI. ,. 38. fÒÓãäÒÓìå PI( FA, ) ÒÓì)!"Øê U (z) <=Øê E(z) )Ü¬"êdÒÓÔ,ÙÚ Øê G(z)É G(z) =. L K É Fê K ÉA,ê. U (z) Ki = Kp + E(z) 1 − z −1. (5.2). p. i. øJ (5.2) FÒÓ#,A,ÒÓ#,ÛzåÜÌÝb³&= ,JÜÌ~JÉ up (k) = Kp e(k) ui (k) = ui (k − 1) + Ki Ts e(k). ø FÒÓ!"Ý"A,ÒÓ!"Ý{\§Ü" PI ÒÓ ì=,JGJ (5.3) tG9ÞÜêdãä,ðñK u(k) = up (k) + ui (k) = Kp e(k) + ui (k − 1) + Ki Ts e(k). (5.3). L u(k). Éê k j 5®!" u (k) Éê k j 5® FÒÓ!" u (k) Éê k j 5®A,ÒÓ!" u (k − 1) Éê k − 1 j 5®A,ÒÓ!" e(k) Éê k j 5®<= p i i. ÒÓìãä>#ðñ6g 5.3 å PI ÒÓìxgø F ÒÓì"A,ÒÓì,Ùë@«<èé!"½eK PI.

(111) ê 5 ë ÔX"ðÁÂZ,- .. 39. 5.3: PI

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(114) ê 5 ë ÔX"ðÁÂZ,- . 5.3. <J(K. 40. y C ýþÔ'ÒÓJDÔðúÐ$§¯ÒÓLd e`CGg 5.4tK. 5.4: opki )78d÷!d÷ÒÓ:½J«()g 4.5*g 4.9tZN éÔÒÓ6 §¯ðúÐ$ÒÓK.

(115) ê 5 ë ÔX"ðÁÂZ,- . 41 g 5.5åy PI ÒÓÔÔå ÷CD~ 4mm d÷Ò ÓÔd÷34gK. 5.5: (A) $230& PI 4 4mm %& '(*+, (B) $ -./01 ÆÔîæKÙd÷ÒÓ\ .ÔDeæKÙÒÓ d÷34Ô ÷~DÔ! 0.2mm ÒÓPI ÒÓÔ d÷34Gg 5.6t)g 5.6ÜÈ³GÔæKÙ ½~; ¹./WdÒÓ¾K.

(116) ê 5 ë ÔX"ðÁÂZ,- .. 42. 5.6: (A) $230& PI 4 0.2mm %& '(*+, (B) $ -./01 WFÔ,Õ5®å¯§d÷ÒÓÏM 10% 8 90% Ú5 ® fy Nios II ðñZ PI ÒÓÔd÷34ÝG0 5.1t [16] ðñZz{YZ| ÒÓÔd÷34ÝG0 2.2t) 0 .Ü)rñfÔZ,Õ5®. [16] ðñZz{YZ| ÒÓÔ \õòK 5 5.1: ; N PI 6%& '(*+785 d÷ÒÓ ,Õ5® (ms) ªÏz+ (mm) ªÏz+X, 0.2mm. 77. 0.001554. 0.78. 1mm. 67. 0.001792. 0.18. 2mm. 74. 0.008415. 0.42. 3mm. 75. 0.009142. 0.31. 4mm. 79.5. 0.028234. 0.71. 5mm. 79. 0.034182. 0.68. (%).

(117) < 6=>?@ 6.1. (. f^_Dòóôõö§¯d÷ÒÓãäããäãrs Ô4GÜÒôÝÞ©úõò Altera Nios II Development Board eåÒ Óòrsóîï Altera Cyclone II EP2C35F672C6ES Ú5ÛÜ JÂßàáâ (Field Programmable Gate Array, FPGA) ãä)*LÄ é Quartus II èéArskú§¯ãäJQ)* úb FPGA >#ÝÞ"îï Nios II në@ì)ûüý DSP ë@ì K Ñ1½D2ÔWdõö»¼Ä¹34õQ«¬óMQ P»*£ø2}ÏAýG¦§JD2õö¸34ò2¨Q« ¬óÏ*yÑäåKý½JL£Å2*Pv÷*Ó®6¹ 5Ge(ÔK¸4zóiD2õö²¸¹5³´3 4Q«æó*£Å2EFµ)e&f½©«ª¹PøE» ªG¼¸9®6¿*GecÙÑÔfM 34ò2õ©«¬óMóôõö\\]1½D2Ôl)èóô õöôçè*@éô2 FØéÚ34ò2~§¯5I 43.

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