Strain enhanced DC-RF performance of
0.13 lm nMOSFETs on flexible plastic
substrate
A. Chin, H.L. Kao, C.H. Kao, C.C. Liao, Y.Y. Tseng and
C.C. Chi
A 14.3% saturation current Id,satimprovement and 0.75 dB minimum noise figure (NFmin) at 10 GHz were measured by applying 0.7% tensile strain for 16 finger, 0.13 mm RF MOSFETs with thin-body (40 mm) substrate mounted on plastic. These excellent results for mechanical-strain on DC-RF MOSFETs are better than those of SiN-capped 90 nm strained-Si nMOSFETs and consistent with device simulations.
Introduction: To integrate the Si-base RF integrated circuits (ICs) on high-resistivity Si substrate [1] is an important technology. Since the passive devices have a poor Q-factor [1–4] arising from the low resistivity (10 O-cm) VLSI-standard Si substrates, integrating RF ICs on insulating plastic provides better passive devices at lower cost than those on lossy VLSI-standard Si substrates. In addition, the thin-body Si IC on plastic is useful for flexible electronics, RF ID, wireless displays and system-on-plastic[5, 6]. The thin-body Si substrate provides flex-ibility for applying mechanical strain. In this Letter we report the DC and RF performance of 0.13 mm thin-body (40 mm) Si MOSFETs on plastic with mechanical strain. The saturation drain current (Id,sat) was improved
14.3% and a 0.75 dB lower minimum noise figure (NFmin) was obtained
at 10 GHz for 0.13 mm MOSFETs on plastic with 0.7% tensile strain. The excellent performance is better than that for SiN-capped, 90 nm node, strained-Si nMOS (11%)[7]. Such DC-RF performance improve-ments were confirmed by TMA simulations for strained 0.13 mm MOSFETs. They arise from the thin body thickness (tb) and high
flexibility, where the surface strain increases with 1=tb2 [8]. The RF
noise improvement fits well an analytical NFminequation[9], and is due
to the increase in the gmand the RF gain under strain.
Experiment procedure: In this study we used 180 mm low-cost, highly-insulating polyethylene substrates, which had a resistivity of 108–109O-cm. The multiple-gate-finger 0.13 mm RF MOSFETs with microstrip line layout were designed on 8-inch wafers at an IC foundry[9]. The multiple-gate-finger structure can reduce the thermal noise generated from gate resistance. The microstrip line layout can shield the RF noise generated in the lossy Si substrate network, instead of a conventional coplanar waveguide (CPW) structure[9]. To achieve integration onto plastic, we first thinned-down the Si substrate from 500 to 40 mm using the chemical mechanical polish (CMP) process and then glued it onto a 180 mm-thick plastic (Fig. 1a). Fig. 1bshows the large surface strain on 40 mm Si substrate. Owing to the flexibility of the thinned-down Si substrate, we can apply large mechanical strain onto the Si substrate without any cracking to measure the DC and RF characteristic. Furthermore, the surface strain can be calculated using ANSYS 8.0 simulation software and the device characteristics were simulated under various applied tensile strain using TMA process-device simulation software. The DC, S-parameters and noise figure were measured using HP4155C, a HP8110 network analyser and the ATN-NP5B noise parameter measurement system, respectively[9].
a b
Fig. 1 Image of die with multiple-gate-finger 0.13 mm RF MOSFET on transparent plastic, and high flexibility of 40 mm-thick Si substrate (tb) under mechanical strain
a Image of die with multiple-gate-finger 0.13 mm RF MOSFET on transparent plastic (held by hand)
Substrate of die thinned to 40 mm
b High flexibility of 40 mm-thick Si substrate (tb) under mechanical strain (proportional to 1=tb2)
Results and discussion: The DC characteristics of 16-gate-finger 0.13 mm RF MOSFETs on a VLSI-standard Si substrate, and on plastic, are shown inFig. 2. The IdVdcharacteristics show almost
identical before and after thinning and mounting on plastic. Similarly, little change appeared in the measured RF current gain jH21j2, as
depicted in Fig. 3. It is indicated that the thinned-down process did not damage the devices. This improvement over the previous ICP etching and thinning process[5]is due to the fact that CMP technique avoids plasma damage. In addition,Figs. 2and3show the modelling data using the TMA process-device simulations software. Good agreement between measured and simulated IdVdand jH21j2were
obtained using the accurate TMA process-device simulations on VLSI-standard Si substrate. 0 0.2 0.4 0.6 0.8 1.0 1.2 0 125 250 375 500 625 750 14.3% Id , m A/ m m Vd, V Lg=0.13mm, W = 2.5mm, 16 fingers on VLSI-standard Si substrate on plastic with 40mm Si
on plastic with tensile strain line: simulation by TMA
measure at Vgs=1.3 V
Fig. 2 Measured and simulated IdVd for 16-gate-finger 0.13 mm RF MOSFETs on VLSI-standard substrate and on plastic with 40 mm Si, with or without tensile strain
Solid lines are TMA-simulated data for VLSI-standard Si substrate and on plastic under 0.7% tensile strain
1 10 100 0 5 10 15 20 25 30 35 40 45 |H 21 | 2, dB frequency, GHz Lg = 0.13 mm, W = 2.5mm, 16 fingers on VLSI-standard Si substrate on plastic with 40 mm Si on plastic with tensile strain line: self-consistent modelling from TMA simulation
150
Fig. 3 Measured and simulated jH21j2against frequency for 16-gate-finger 0.13 mm RF MOSFETs on VLSI-standard substrate and on plastic with 40 mm Si with or without tensile strain
Line is modelled data
Because of the flexibility of the thinned-down Si substrate it can be subjected to large levels of strain. The large surface strain (e ¼ 3aF=btb2E)[8]results from the applied force (F) associated with
a bending distance (a) and width (b). We calculated the surface tensile strain using ANSYS 8.0 software, as shown in Fig. 4. The bending distance is about 0.17 cm when we applied 0.8 GPa stress on 40 mm Si substrate. Therefore, tensile strain is 0.7% ( ¼ 0.8 GPa=115 GPa) where the Young’s modulus of Si is 115 GPa.
In this condition, we measured the IdVd, S-parameter and NFmin. Figs. 2and3show the IdVdcharacteristic and RF current gain jH21j2
of 16-gate-finger 0.13 mm RF MOSFETs on plastic with and without tensile strain, respectively. The fTis extracted on RF current gain jH21j2
equal to 1. Under the applied 0.7% tensile strain on plastic, the Id,sat
increased 14.3% and the unity-gain cutoff frequency fTincreased from
103 to 118 GHz. Such improved Id,sat and fT under strain is also
confirmed by TMA simulation and also shown inFigs. 2and3. It is indicated that the increased Id,satand fTare the result of increased electron
mobility which is the result of the reduced intervalley scattering under tensile strain[10]. A large improvement occurred compared with SiN-capped 90 nm strained-Si nMOS (11%)[7], owing to the 1=tb2
depen-dence of the strain for thin-body Si.
a=0.17cm
stress=0.8GPa
bending distance
Fig. 4 Mechanical stress calculated using ANSYS 8.0 simulation software
Fig. 5 shows the NFminand associated gain of 0.13 mm transistors
under tensile strain. The NFmindecreased from 0.89 to 0.75 dB and the
associate gain increased from 14.2 to 15.3 dB at 10 GHz. The NFminis
lower than the unstrained case over the whole frequency range. The lower NFminfrom strain arises through[9]:
NFminffi1 þ 2gð1 þ gmRg=gÞ 0:5
f =fT ð1Þ
The close agreement between the measured and simulated NFmin, as
shown inFig. 5, indicates that the lower NFminarises from the
strain-improved fT. The NFminis better than those for 90 nm node SiN-capped
strained-Si nMOS[7]inFig. 5. The large DC-RF improvements with strain are some of the advantages of thin-Si-body flexible electronics on plastic. 0 5 10 15 20 0 0.5 1.0 1.5 2.0 2.5 90nm mode nMOS [7]
line: simulation using (1)
NF min, dB frequency, GHz 0 10 20 30 associate gain, dB Lg = 0.13 mm, W = 2.5mm, 16 fingers on plastic on plastic, with strain
NFmin GainASSO
Fig. 5 Frequency dependence of NFminand associate gain of body-thinned 16-gate-finger 0.13 mm RF MOSFETs on plastic under strain
Conclusion: High performance was achieved for thin-body 0.13 mm MOSFETs on plastic. These devices showed excellent low noise performance (0.75 dB at 10 GHz), high associated gain (15.3 dB)
and a 14.3% Id,satincrease. Such high performance RF transistors are
improved by thinning the substrate and making it flexible to apply tensile strain.
Acknowledgments: We thank the Chip Implementation Center (CIC) and G.W. Huang at the National Nano-Device Lab, Taiwan, for help with RF measurements.
#The Institution of Engineering and Technology 2006 17 April 2006
Electronics Letters online no: 20061035 doi: 10.1049/el:20061035
A. Chin, H.L. Kao, C.C. Liao and Y.Y. Tseng (Department of Electronic Engineering, National Chiao Tung Univeristy, Nano Science Technology Center, University System of Taiwan, Hsinchu 30050, Taiwan, Republic of China)
E-mail: [email protected]
C.H. Kao (Department of Accounting Information, Takming College, Taiwan, Republic of China)
C.C. Chi (Department of Physics, National Tsing Hua University, Hsinchu, Taiwan, Republic of China)
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