1 fF ESD protection device for gigahertz
high-frequency output ESD protection
J.-H. Lee, S.-C. Huang, Y.-H. Wu and K.-H. Chen
A mutual-protection scheme is proposed to achieve an ultra-low capacitance electrostatic discharge (ESD) protection device. The ESD protection device can not only dissipate ESD current, but also can make the vulnerable output transistor have the ESD protection capability. Namely, the output transistor can also protect ICs and help the ESD protection device to share the ESD current. Using this scheme can discharge more ESD current than the summation current of the two individual devices. From the ESD test result, it can achieve the required ESD level by using the ultra-low capacitance ESD protection device (1.2 fF).
Introduction: As technology advances to the nanometre regime, the thin gate oxide, short device channel length and ultra-shallow junction make the device more vulnerable to electrostatic dis-charge (ESD) stress than ever. Moreover, a transistor has the maximum loading capacitance limitation when it operates in the giga-hertz (GHz) region for high frequency (HF) or radio-frequency (RF) applications[1]. To meet this criterion, the output transistor often does not have any ESD protection capability. The ESD performance of this kind of output transistor relies on the ESD protection device size. This makes it hard for the output transistor to reduce its loading capacitance if it needs to meet the required ESD level, 1 kV human-body model (HBM) and 30 V machine-model (MM)[2]. It has been reported that there are several schemes[3 – 7]that can improve the ESD performance of the fully silicide n-MOSFET to an excellent level. However, they all have their own limitations. Using the long contact-to-contact space[3]
will increase the source/drain series resistance, which results in device RF characteristic degradation. The diode from I/O PAD to Vddmakes the substrate-trigger NMOS[4]and pnp-gate-driven NMOS[5] inap-plicable for failsafe operation [6]. With a gate-booting capacitor, the n-MOSFET of the substrate-pump NMOS [6]cannot be used as the output transistor.
The diode string (DIOS) has been successfully used to lower the trigger voltage (Vt1) of the silicon-control-rectifier[7]below the break-down voltage of the protected device. In this Letter, a DIOS is proposed to make the output transistor become the ESD protection device to share the ESD current with each other. So, this scheme is called the mutual-protection scheme.
Experiment: The technology used to fabricate the devices for this study is a 45 nm 1.1 V/2.5 V CMOS process and the architecture in this experiment is verified by using 1.1 V devices.
Structure:Fig. 1shows the layout and cross-section of the structure used to implement the mutual-protection scheme. This structure is com-posed of an n-MOSFET, a DIOS and a p+ guard-ring. The n-MOSFET is the output transistor, which is a multi-finger device with 2 mm finger width, 100 mm total width and located at the centre of the p+ guard-ring. The DIOS is the ESD protection device, which is composed of three diodes in series and located at either side of the p+ guard-ring. The p+ diffusion area for each diode is 0.528 (0.33 × 1.6) mm2. From the spice model, the total capacitance of the DIOS is nearly 1.2 fF.
p+ guard-ring (VSS) diode-string diode-string D1 D1 D2 D2 D3 D3 n+ p+ n+ p+ n+ p+n+ n+ n+ p+ p+ p+ n-MOSFET 2um
Fig. 1 Layout for DTNPN
Fig. 2shows the equivalent circuit of the structure inFig. 1. For a p+/ n-well diode fabricated on the p-substrate, it can be treated as a pnp bipolar transistor[8]. During the ESD zapping event, the pnp bipolar transistors of the DIOSs can provide the substrate currents to trigger the parasitic npn bipolar transistors of the n-MOSFET. Thus, this struc-ture is called the diode-triggered npn (DTNPN).
IDTNPN In2 Inc2 Isub2 Isub1 Ipc1 Ipc2 NW pnp -3 pnp -2 pnp -1 npn -1 npn -2 NW NW Ipc3 Vsub5 Vsub4 Vsub3 Vsub2
Vsub1 rsub2 rsub3 rsub4 rsub5
rsub1 Inc1 In1 IB1 IDIOS IB2 D3 p+ p+ n+ p+ n+ p+ n+ n+ n– n– n+n– n– n+ D2 D1 D1 p-substrate drain
Fig. 2 Equivalent circuit of DTNPN inFig. 1
DC IV characteristics: Fig. 3shows DC-IV characteristics of a total width 100 mm n-MOSFET, a DIOS and the DTNPN inFig. 1. Below 1.7 V, the currents of the total width 100 mm n-MOSFET and the DTNPN overlap each other and cannot be distinguished since the DIOS current is still too small to affect the current of the DTNPN. Above 2.1 V, the currents of the DTNPN and DIOS overlap each other and cannot be distinguished since the applied voltage is beyond the turn-on threshold voltage (VT) of the DIOS. This implies that the DIOS does not lead to an increase in the current of the DTNPN output transistor under the normal 1.1 V operation. Moreover, the DIOS can also provide a current path to dissipate ESD current and trigger on the parasitic npn bipolar transistor of the DTNPN output tran-sistor during the ESD zapping event.
10–3 10–4 10–5 10–6 10–7 10–8 10–9 10–10 10–11 10–12 10–13 0 0.5 1.0 1.5 voltage, V n-MOSFET DIOS DTNPN current, A 2.0 2.5 3.0 10–14
Fig. 3 DC-IV characteristics of n-MOSFET, DIOS, and DTNPN inFig. 1
High-current IV characteristics: Fig. 4shows high-current IV charac-teristics of a total width 100 mm n-MOSFET, a DIOS and the DTNPN under the 100 ns transmission-line pulse (TLP) stress events. The trigger voltage (Vt1) of the pure n-MOSFET is 5.5 V and its maximum current before device damage (It2) is 0 A and it cannot pass the smallest zapping voltage (HBM 50 V and MM 25 V). This implies that the pure n-MOSFET has no ESD protection capabilities. For DIOS, the current increases with the TLP voltage after its turn-on voltage VT(2.1 V). To minimise the device capacitance, the It2and Vt2of the DIOS is designed only beyond a little of the It1and Vt1 of the DTNPN. leakage current, A, at 1.2 V voltage, V 0 2 4 6 VSB Vt1,It1 Vt2,It2 snapbac k Vt1,It1Vt2,It2 8 10–11 0.6 0.5 0.4 current, A 0.3 leak. (n-MOSFET) leak. (DIOS) leak. (DTNPN) TLP (n-MOSFET) TLP (DIOS) TLP (DTNPN) 0.2 0.1 0 10–10 10–9 10–8 10–7 10–6 10–5 10–4 10–3
Fig. 4 High-current IV characteristics of n-MOSFET, DIOS, and DTNPN in Fig. 1
For DTNPN, the current of the DTNPN is nearly identical to the current of the DIOS below its Vt1 (5.2 V) since only the DIOS turns
on before the snapback occurs. FromFig. 2, the DIOS is composed of the pnp bipolar transistors and the base current of one transistor injects into the emitter of the next stage pnp bipolar transistor as the emitter current. Moreover, all collector currents of the DIOS flow into the p-substrate and through the substrate resistors to raise the substrate potential. As the substrate potential is increased beyond 0.9 V[9], the diode D1 between the source terminal of the n-MOSFET and p-substrate terminal is biased at the high-injection region. This induces the source terminal to inject a lot of electrons into the high-field drain terminal to give rise to the substrate current generation due to the impact ionisations. Subsequently, the generated substrate currents combined with the col-lector currents of the DIOS can sustain enough substrate potential to bias the source terminal at the high-injection region. Thus, the source can keep injecting the electrons to the drain terminal to generate the substrate current. These actions form a loop to cause the npn bipolar of the DTNPN n-MOSFET to turn on and drive it into the snapback region. The snapback voltage (VSB) and Vt1of the DTNPN are smaller than the Vt1of a pure n-MOSFET, about 2.1 and 1.2 V, respectively. This pre-vents the high voltage from damaging the DTNPN n-MOSFET during the ESD zapping event. Unlike the pure n-MOSFET, the DTNPN n-MOSFET is not damaged after the first snapback and its It2 (≃0.5 A) is apparently much higher than the DIOS It2 (≃0.16 A). This implies that the DIOS can make the DTNPN n-MOSFET have the ESD protection capability to resist the ESD damage. Furthermore, the DTNPN n-MOSFET can also protect the DIOS from ESD damage since the voltage drops down by about 0.9 V beyond its Vt1. Because of the npn bipolar turning-on, the voltage will be clamped at the low snapback voltage and will not damage the DTNPN until it rises beyond the Vt1 of the pure n-MOSFET. This phenomenon, that the DIOS and n-MOSFET protect each other alternately, is called the mutual-protection scheme. Using this scheme, the ESD protection device can be minimised since ESD will not damage the DIOS even though its It2is only slightly higher than the It1of the DTNPN. After turning on, the n-MOSEFT can dissipate most ESD current. From the ESD test result, the DTNPN can pass 1.0 KV HBM and 50 V MM even though the total capacitance of its ESD protection device is only 1.2 fF.
Conclusion: Using the conventional ESD protection scheme, it is very difficult to reduce the capacitance of the ESD protection device to the femtofarad range if it still needs to meet the required ESD level. The mutual-protection scheme provides an easy way to achieve the capaci-tance of the ESD protection device for the output transistor into the femtofarad range.
#The Institution of Engineering and Technology 2011 20 June 2011
doi: 10.1049/el.2011.1904
One or more of the Figures in this Letter are available in colour online. S.-C. Huang and K.-H. Chen (Institute of Electrical and Control Engineering, National Chiao Tung University, Taiwan)
E-mail: [email protected]
J.-H. Lee (ESD/Latch-up independent consultant for Richtek Technology Corporation and Realtek Semiconductor Corporation) Y.-H. Wu (Realtek Technology Corporation)
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