Abstract—A 2.4–5.4-GHz CMOS reconfigurable low-noise
am-plifier (LNA) is designed. It consists of two stages: a broadband input stage for a steady input matching and noise performance, and a reconfigurable band-selective stage which provides a wide-range frequency tuning from 2.4 to 5.4 GHz and a 12-dB stepped gain with linearity adjustment. The frequency tuning is conducted by a multitapped switching inductor and varactors. Careful design of the switching inductor achieves consistent performance among fre-quency configurations. The stepped gain and linearity adjustment are provided by a size-switchable transistor with a variable biasing. Fabricated in 0.13 m CMOS technology this LNA exhibits perfor-mance including up to 25 dB power gain, 2.2–3.1 dB noise figure and less than 5 mW power consumption under 1 V power supply.
Index Terms—Dual reactive feedback, low-noise amplifier
(LNA), multistandard, reconfigurable, switching inductor.
I. INTRODUCTION
M
ULTISTANDARD radio is a trend for next generation wireless systems. As wireless standards are evolving to meet the need in various scenarios, it is highly expected that a transceiver is reconfigurable in specification accommo-dating different standards. Such specifications for a receiver RF front-end include carrier frequency, bandwidth, voltage gain, noise figure, and linearity. Moreover, the power consumption shall be controllable accordingly.At the input of a reconfigurable receiver, a low-noise am-plifier (LNA) is expected to provide good input impedance matching, high voltage gain and low noise figure in dynam-ically specified frequency bands. The frequency operation of such an LNA can be in either concurrent multiband or tunable single band. To date there are several approaches for concurrent multiband operation. First proposed in 2002, an LNA utilizes dual-band LC-networks to provide concurrent dual-band input matching and output gain response [1]. This approach becomes
Manuscript received June 06, 2008; revised August 02, 2008. First published November 07, 2008; current version published December 05, 2008. This work was supported jointly by the National Science Council, Taiwan, under Grant NSC 95-2220-E009-034, the MediaTek Center, NCTU, and the ITRI JDR Center, NCTU.
C.-T. Fu and C.-N. Kuo are with the Department of Electronic Engineering, National Chiao-Tung University (NCTU), Hsinchu, 300 Taiwan (e-mail: ctfu@ieee.org; cnkuo@mail.nctu.edu.tw).
C.-L. Ko is with the Department of Electronic Engineering, National Chiao-Tung University (NCTU), Hsinchu, 300 Taiwan, and with National Chip Imple-mentation Center (CIC), Hsinchu, 300 Taiwan (e-mail: clko@ieee.org).
Y.-Z. Juang is with National Chip Implementation Center (CIC), Hsinchu, 300 Taiwan (e-mail: yzjua@cic.org.tw).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TMTT.2008.2006804
Fig. 1. Performance matrix for reconfiguration of LNA. In this study, the three corner states of low power and middle power are pursued.
cumbersome when handling multiple bands. The more ade-quate solution is a broadband design with comprehensive band coverage. Numerous broadband LNA design techniques have been developed by applying the input LC bandpass filtering [2], [3], the dual reactive feedback [4], the resistive/source–fol-lower feedback [5]–[7], and the common-gate topologies [8]. In compare with the tunable single band approach, the broadband input matching avoids the use of tunable devices in input network that easily degrades noise performance. The broadband gain response, however, is unfavorable because it allows undesired interferers to pass through such that stringent linearity is required in the succeeding stages (e.g., mixer). As such, a tunable single band gain response is preferred for out-of-band interferer suppression [9], [10].
Besides the frequency issues, the tradeoff between LNA per-formances can be outlined by the performance matrix as shown in Fig. 1, giving insight for performance reconfiguration. Typ-ically the higher gain provides the lower noise figure, whereas the lower gain brings the better linearity. Power consumption further affects the circuit dynamic range.1If higher performance
of a larger dynamic range is in need, the LNA shall be configured to consume more power to meet the requirement. For example, a large dynamic range demanding both low noise figure and high linearity is required in the ultra-wideband (UWB) system, whereas the low power consumption is of the primary concern in Bluetooth connection. Techniques including bias control, cur-rent steering, feedback switching, and attenuation switching can be used for gain control [11], [12].
This paper proposes a wide tuning-range performance-recon-figurable LNA. It consists of two stages featuring broadband input matching and low noise amplification at the first stage,
1The circuit dynamic range is defined as the allowed input power range,
typ-ically from its sensitivity to 1-dB compression point. 0018-9480/$25.00 © 2008 IEEE
Fig. 2. Proposed reconfigurable LNA.
TABLE I
DEVICEVALUES OF THEDESIGNEDLNA
and a wide tuning-range band-limited gain response with ad-justable performance at the second stage. The 0.13 m tech-nology CMOS LNA is designed to operate from 2.4 to 5.4 GHz. A new switched inductor configuration provides wide-range fre-quency tuning while gain and noise figure are maintained at the same level. With bias control and transistor size switching, performance is reconfigurable to approach the lower left three corner states as shown in Fig. 1. This paper provides theoretical extension for [13], including a related design concept for wide range tuning and switching inductor. The error of linearity per-formance listed in [13] is also amended.
This paper is constructed as follows. In Section II the pro-posed reconfigurable LNA design is discussed in detail. As the key component for wide tuning range, the design of switching inductor is discussed in Section III. Section IV demonstrates the chip implementation and shows measurement results. Finally, this work is concluded in Section V.
II. PROPOSEDRECONFIGURABLELNA
The schematic of the proposed reconfigurable LNA is as shown in Fig. 2. The first stage is a broadband amplifier with dual-reactive feedback, based on the circuitry in [4]. The second stage is a cascode amplifier providing gain, linearity, and wide-range frequency tuning. The output buffer stage is for measurement purpose. The parameters of key devices are listed in Table I and the design concepts of the first and the second stages are detailed as follows.
Fig. 3. Voltage gain and noise figure of the first stage in simulation result.
A. Broadband Amplifier With Controllable Output DC Level The first stage performs broadband low noise amplification and input matching. The basic amplifier is a CMOS inverter amplifier ( and ) featuring large trans-conductance and dc-current reuse. The gate bias of each transistor is fed via a 10 k resistor and isolated by capacitors and . By employing dual reactive transformer and capacitive feed-back along with an input shunt tank, this architec-ture can achieve broadband simultaneous noise and impedance matching as shown in [4]. The two reactive feedback networks facilitate impedance and noise matching at two different fre-quencies, extending the frequency band of simultaneous input power match and noise optimization [14]. In this project, this stage is designed for the entire 2–6 GHz frequency band. The input impedance matching is designed having less than 15 dB input reflection and the noise figure is very close to in this wide frequency range.
As to the voltage gain response, the provides a series peaking boosting the gain at the high frequency corner. At fre-quencies lower than 1-GHz introduces a low impedance path to ground thus suppressing out-of-band interferers. As the design result, the simulated frequency responses of voltage gain and noise figure of the first stage are shown in Fig. 3.
The biasing of and is separated to provide a con-trollable output dc level to bias transistor , conducting the performance reconfiguration at the second stage. The dc level,
grated receiver, the and the bias voltage can be configured by a current-mode DAC and a constant- bias circuit, respectively. In this prototype both of them are driven externally for laboratory test purpose.
B. Performance Reconfiguration by Switching Transistor Performance reconfiguration is realized by the common-source amplifier ( ) at the second stage, including gain and linearity control. The noise figure is generally correlated to the gain level; that is, higher gain brings a lower noise figure. The design target is implementation of three operation modes, one in high gain (HG) and two in low gain ( and ). Gain difference of at least 10 dB is expected between the high-gain and the low-gain modes. Besides, this LNA exhibits an improved linearity in mode while the even lower power consumption is achieved with degraded linearity in mode. Being the transconductor of the cascode amplifier at the second stage, is found to be the linearity bottleneck of this LNA. Its transconductance is the primary nonlinearity source as is loaded by a common-gate stage of low input impedance [15]. Hence, linearity control mainly relies on gate biasing. Linearity performance can be inspected by the second and third input interception point voltages, and
as
(1) and
(2) where the and the are the first and the second deriva-tive of , respectively. Because receives very wideband input, the second-order distortion is found as critical as the third-order in some application cases. Transistor linearity is charac-terized by the simulated results of , and
versus , as plotted in Fig. 4. As can be seen, larger gives higher gain , better , and larger drain current, while varies insignificantly. The second-order distortion is chosen as the primary linearity index to be improved in this LNA.
The actual design is according to Fig. 4. Gate bias is first chosen corresponding to different linearity performances in each operation mode. Then the transistor size is set regarding to gain requirement. The design result is summarized in Table II. The 12 dB stepping difference is produced on and between the HG and the modes. In practice the drain current , instead of , is controlled to alleviate the impact of process variation.
Fig. 4. Simulatedg =g and g of transistor M in response to V under different gain modes.
TABLE II
DESIGNPARAMETERS INEACHOPERATIONMODE
As shown in Fig. 2, the transistor actually consists of three transistors, , and with the size ratio of 1:2:4. Transistors and are switched on and off by the switches at their source nodes. This allows larger switch size for smaller on-resistance. The input capacitance of should not be changed significantly by size switching as it is an important parameter for LNA input matching, which is expected to be similar among all considered configurations. For the sake of this, the source nodes of and are ac bypassed to ground to alleviate the impact of switching to the input capacitance.
Switching transistor controls the voltage gain and lin-earity, as well as the power consumption. Compared to the con-ventional current steering variable-gain schemes in which gain is adjusted by the common-gate transistor , our approach is more power-efficient because at lower gain the LNA requires smaller drain current.
C. Frequency Tuning by Switching Inductor and Varactor Band-selective filtering is provided by an LC resonance tank at the second stage as shown in Fig. 2. The resonator consists of a multitapped switching inductor and two on-chip varactors. The former provides coarse frequency stepping, while the latter is for fine tuning. Coarse frequency stepping is realized by switching control of tapping points so as to obtain different inductances,
Fig. 5. Wide continuous frequency tuning by adjusting both the inductor and capacitor. (a) Practical circuitry. (b) Equivalent parallel resonance tank.
yielding to several sub-bands. This LC tank is demanded to be tunable over the entire frequency range of interest. Meanwhile it shall provide a quite consistent voltage gain for each tuned band. This calls for the quality factor requirement of the switching inductor as described as follows.
The resonator tank can be generally represented by an equiv-alent circuit as shown in Fig. 5(a), in which the inductance is switchable and the capacitance is tunable. The resistance in series to inductor includes the inductor parasitic resistance and the switch on-resistance, and dominates the quality factor of this tank. As the inductance is changed by turning on distinct switches, the value can actually be changed accordingly. To get the insight to achieve the aforementioned gain consistency requirement, the resonator circuit is transformed to the parallel RLC tank in Fig. 5(b), with the equivalent parallel inductance and resistance derived, respectively, as
(3) and
(4) Here stands for the quality factor of the switching inductor which equals to , and is the resonance frequency as
(5) The 3-dB bandwidth (BW) of this resonance tank is
in Hertz (6)
At resonance the voltage gain of this circuit can be expressed as (7) The design guideline is revealed from these equations. Given the typical condition of a flat response over the frequency range of interest, the voltage gain consistency fully corresponds to the frequency dependency of . In discussion of the fine ca-pacitance tuning, the switching inductor is assumed frozen with a fixed inductance. As , it leads to the frequency dependency of for consistent from (4) as
Fig. 6. Quality factor profile of switching inductor as required for good voltage gain consistency.
(8) This condition can be partially met by a practical inductor, of which quality factor declines in the frequency region higher than the peak- frequency. Note that a consistent BW calls for the condition of by (6), opposite to (8). For LNA the consistency on voltage gain is more important than bandwidth so the design generally follows (8). Nevertheless, the bandwidth variation is still acceptable if the frequency range of each sub-band remains small enough.
The condition for consistent among coarse inductance stepping can also be obtained from (4), by freezing the tuning of , as
(9) That is, when inductance is switched smaller for a higher res-onance frequency, the corresponding quality factor of switching inductor should be proportionally higher, which necessitates a smaller . In general this can be fulfilled by design of the switch on-resistance for each inductance.
Combined together, the conditions in (8) and (9) give the quality factor requirement of the switching inductor as the pro-file shown in Fig. 6. In practical implementation of the on-chip switching inductor, the rule of (9) is actually difficult to realize because it demands an unacceptable large switch transistor for the smallest inductance. To overcome this difficulty, an alter-native switching configuration for the inductor is proposed, as discussed in the next section.
III. MULTITAPPEDSWITCHINGINDUCTOR
A. Switching Configuration
The basic idea of inductor switching is to enable or disable sections of inductor coils to obtain different inductance values. The conventional switching configuration for a multitapped in-ductor is shown in Fig. 7(a) [16], [17]. Both ends of the coil are directly connected to the application circuit at the nodes and . Switches are attached to the tapping nodes, of which one can be turned on to bypass the remaining coils. The switch on-resis-tance is known to degrade the inductor quality factor. The degra-dation becomes worse in a spiral configuration that all the coil sections are winded together with magnetic mutual coupling. This coupling magnifies the degrading effect of switch on-re-sistance. An alternative switching configuration is proposed as
Fig. 7. Different switching configurations for multitapped inductor. (a) Con-ventional. (b) Proposed.
Fig. 8. Equivalent circuits of double-tapped inductor in different switching configurations. (a) Conventional. (b) Proposed.
shown in Fig. 7(b), in which an additional switch is attached at the end node of the coil to convert the difficulty that the con-ventional configuration faces.
Consider the representative case of double-tapped switching inductor, i.e., in Fig. 7. When the inductors in Fig. 7(a) and (b) are switched for the smaller inductance, they can be modeled as circuits shown in Fig. 8(a) and (b), respectively. The is on-resistance of the switch at node , typically much larger than the intrinsic resistance of coil. The in Fig. 8(b) is parasitic capacitance of the switch at node in OFF state. The two sections of coil, and , form a transformer with coupling factor of .
In the desired ideal case without effect of and , only the primary loop of and is considered such that the inductor quality factor is limited by as
(10) When and are considered, the input impedance in the conventional case of Fig. 8(a) can be derived as
(11) in which
(12) The issue of can be addressed in twofold. At the low fre-quency that , the inductance approximates to
Fig. 9. Calculated results compared for the test cases in the conventional (0000) and the proposed configurations (0000). The ideal switch operation of only the primary loop (0 0 0) is included as a reference. (a) Effective inductance. (b) Quality factor.
, equal to inductance of the entire coil and hence the in-ductance switching function fails. At the high frequency that
, the can be derived as
(13)
which is less than the for .
On the other hand, the input impedance in the proposed configuration can be derived as
(14) in which . As the frequency approaches to
(15)
becomes as , independent of , and thus
the quality factor is limited only by the intrinsic resistance of coil. The quality factor boosting conducted by the auxiliary resonance of and is therefore obtained in the high frequency region around .
A test case compares these two configurations. Set and as 1 and 2 nH along with parasitic resistances 2 and 4 , respectively. The coupling factor is 0.5, is 10 , and is 0.3 pF. The calculated results are shown in Fig. 9(a) and (b). Also included is as a reference. The calculated of (15) is 5.58 GHz. The by the proposed configuration is boosted near , close to the intrinsic coil quality factor and much larger than .
B. Tuning Ratio of Resonance Frequency
When the switching inductor is applied to an LC resonator with a capacitor, the wide-range resonance frequency tuning is the primary expectation. The frequency tuning ratio is mainly determined by the inductance tuning ratio provided by the switching inductor. In the case using conventional switching configuration, the frequency tuning ratio is unlimited because the effective inductance can be switched to an arbitrarily small value, though the quality factor can be severely degraded to
Fig. 10. Equivalent model to calculate the achievable frequency tuning ratio.
unusable. In the use of the proposed configuration, however, the frequency tuning ratio is limited as the consequence of quality factor boosting by the auxiliary resonance.
The analysis of the limited tuning ratio is by using the equiv-alent model of LC resonance tank as shown in Fig. 10, in which the is the effective inductance of switching inductor and the is the external capacitor to resonate with . This model discusses the two extreme cases of the maximum and minimum with the switching of and . The switch on-resis-tance is chosen to be ignored in this analysis so as to identify the primary limiting factor.
When the is open and the is short, the maximum effective inductance is
(16) in which is the magnetic coupling factor between and . On the other hand, when the is short and the is open, the minimum inductance can be derived as
(17) which is frequency dependent. When resonating with , the and give the minimum and maximum reso-nance frequencies and , respectively. The can be easily derived as
(18)
The can be obtained by solving the equation
(19) of which solutions are
(20) The solutions in (20) indicate two resonance frequencies at which peak value of can be found. As discussed in the Appendix , the lower frequency applying the minus sign in (20) is the one of interest for .
Fig. 11. Frequency tuning ratio of the proposed switching inductor configura-tion in differentC =C ratio. The dotted horizontal asymptotes are located at the maximum value of tuning ratio given in (21).
Fig. 12. Designed switching inductor using PMOS as switches.
Fig. 13. Simulation results of the designed switching inductor with designed PMOS switches.
The frequency tuning ratio is defined as . As the is inductance of the remaining coil bypassed by , the intuitive design of a smaller with a larger cannot always promise a larger frequency tuning ratio because the increase of can also decrease the . The optimal
arrange-ment for maximum depends on and ratio.
It is difficult to derive directly but can be traced from the calcu-lation results, as shown in Fig. 11. Also included is the special case of as discussed in Appendix .
Fig. 11 reveals important insight. First, for a given
ratio the peak value of is constant for .
Second, a smaller ratio allows a larger peak
value. What of interest is the relationship between the peak value and the ratio as a design guide for the switching inductor. This can be obtained by finding the peak
Fig. 14. Micrograph of the fabricated reconfigurable LNA under test.
Fig. 15. Measured input and output reflection ratio (S and S ) of the LNA in all listed configurations under test.
Fig. 16. Measured power gain of LNA under typical bias condition.
(21) Therefore, the primary factor limiting the achievable frequency tuning ratio in the proposed switching inductor is identified to be ratio, and can be designed according to (21). C. Switching Inductor Design of This LNA
The switching inductor in this project is implemented by a spiral inductor with three additional tapping points, as shown in Fig. 12. The simulation results with the designed switches are shown in Fig. 13. The bold faced section of the inductances and
Fig. 17. Measured noise figure for the five frequency configurations in HG mode. Most of them are lower than 3 dB.
Fig. 18. Continuous frequency tuning with coarse inductor switching and fine varactor tuning.
Fig. 19. Measurement result of the second-order intermodulation distortion and the gain desensitization at 5.2 GHz because of the 2.6 GHz interferers.
quality factors correspond to the sub-bands they are employed. The proposed switching configuration improves the quality factor, allows a smaller size of the and , and ensures the quality factor increased as the inductance switched smaller for higher frequency operation. The for (15) is the parasitic capacitance of in OFF state as 115 fF, leading to a quality factor boosting at about 4.5 GHz. The quality factors for each sub-band has been quite close to the required profile depicted in Fig. 6, except the local profiles of inductance and affected by the boosting. As to the frequency tuning ratio, the
and for (21) are, respectively, 324 592 and 115 fF, in which the is a variable capacitance. The actual designed
TABLE III PERFORMANCESUMMARY
frequency tuning ratio in this LNA is 2.3 with sub-bands over-lapped, which ensures a full coverage over the entire tuning range and a less than 3-dB gain variation.
IV. CHIPIMPLEMENTATION ANDMEASUREMENTRESULTS
This LNA is designed with 1.0 V supply voltage and fabri-cated in TSMC 0.13 m RF CMOS process. Fig. 14 shows the micrograph of the LNA under test. The core circuit without pads occupies 0.49 mm chip area. RF signals are measured with on-wafer probing while all dc voltage is provided via bonding wires. In the test cases, small signal -parameters are obtained with Agilent 8364B network analyzer, and noise figure from Ag-ilent 8974A noise figure analyzer with cable loss compensation. Two-tone tests are performed to test the linearity performances of and . The accurate power level at LNA input is cal-ibrated by use of a power meter.
Performances of this LNA are measured in three configured performance modes in five frequency bands, carrying out 15 test cases. The five frequency bands include the designed upper and lower tuning limits and three MB-UWB mode-1 bands, listed as 2.4, 3.43, 3.96, 4.49, and 5.4 GHz. The performance modes in-clude one 20-dB high-gain mode (HG) and two 10-dB low-gain modes ( , and ), representing the three operation modes shown in Fig. 1, in which the mode is for better linearity, whereas the mode toward the lowest power consumption. The -parameter test results are shown in Figs. 15 and 16. The broadband input/output reflection performances for the 15 configurations are successfully kept consistent. The power gains at the HG mode are in the range from 22 to 25 dB whereas at the and the modes from 10 to 13 dB. Gains at different frequency bands for each gain configuration are within 3-dB variation and approximately consistent. Noise figures are lower than 3.1 dB for HG mode and lower than 5 dB for and modes. The tested curves for the HG mode are shown in Fig. 17 as representative. The capability of continuous frequency tuning is verified as shown in Fig. 18, in which to represent the different switched inductance values.
The linearity of this LNA is characterized by the two-tone test for and . For the test two CW interferer tones are input at the frequencies of 2.599 and 2.601 GHz, while the LNA
Fig. 20. Performance corner matrix withIIP as the linearity indicator.
Fig. 21. Performance corner matrix withIIP as the linearity indicator.
is configured to operate at 5.2 GHz where the lands. The output is measured and referred to the input by dividing the measured power gain at 5.2 GHz to calculate the corresponding . The measurement results are shown in Fig. 19, in which the gain desensitization at 5.2 GHz due to the two 2.6 GHz inter-ferers is also included. The measured and both range from 21 to 5 dBm, depending on which gain mode is chosen. The control for the three gain modes is consistent with the design in Fig. 4.
The measured performance is summarized in Table III. The performance corner matrices are shown in Figs. 20 and 21, using
and as the linearity indicator, respectively. Perfor-mances at the five representative frequencies with the same per-formance configuration are grouped. With the linearity control on the Fig. 20 shows a nearly consistent result as illus-trated in Fig. 1. Therefore the performance reconfiguration con-ducted by switching transistor with bias control is verified. Fi-nally, Table IV compares works of multistandard LNAs pub-lished to date.
V. CONCLUSION
A 2.4–5.4-GHz wide tuning-range performance reconfig-urable LNA is demonstrated. The broadband input stage is verified to be adequate in providing steady input matching and noise performance. The performance reconfiguration on gain, linearity, and power consumption is achieved. By use of the proposed inductance switching configuration, the multitapped switching inductor can be well designed to provide wide tuning range with good performance consistency. The pro-posed switching configuration is advantageous with the quality factor boosting but suffers from limited frequency tuning ratio. This limitation has been identified and the design reference is given in (21). As a result, this prototype has proven the high performance flexibility and wide-range tuning of LNA within the below-average low power consumption.
APPENDIX
As the in Fig. 10 is switched to , the can
be derived as
(A1)
in which two poles and one zero can be found on the posi-tive -axis. The two poles are located at frequencies as solved in (20). We can determine which pole frequency is our case by testing their continuity to as is approaching
, by setting and . In this test
the higher pole frequency can be found approaching infinity whereas the lower pole meets the . Therefore the minus sign is applied in (20).
There are two singular cases not applicable to the above dis-cussion, and . In the case of , i.e., no mutual coupling between coil sections, the pole dominated by is cancelled by the zero in (A1) so that the resonance frequency is determined only by . Thus the frequency tuning ratio dis-cussed in Section III-B is unlimited as the can be designed arbitrarily small. In the case of , the denominator in (A1) is diminished contributing only one pole, which makes the in Section III-B to be
(A2) Given a fixed , the achievable frequency tuning ratio in this case is limited by the complementary relationship between and in (16). These two special cases, though not practical to this work, also roughly show how the mutual coupling affects the frequency tuning ratio in the use of the proposed switching inductor.
ACKNOWLEDGMENT
The authors wish to thank Prof. T.-H. Sang, NCTU, for helpful discussion, Dr. S. S. Taylor, Intel Corporation, for proofreading, the National Center for High-Performance Computing (NCHC) for software support, and the Ansoft Corpoation for technical support of EDA tools including HFSS and Designer.
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Chang-Tsung Fu (S’00) received the B.S. degree
in communication engineering and M.S. degree in electrical engineering from National Chiao Tung University, Hsinchu, Taiwan, in 1996 and 2001, respectively, and is currently working toward the Ph.D. degree at National Chiao-Tung University, Hsinchu, Taiwan. His doctoral research is focused on broadband matching theory and techniques for RF front-end circuitry.
In 2006, he was an Intern with the Intel Corpora-tion. His research interests include research and de-sign of integrated circuitry for wireless communication systems.
Chun-Lin Ko (S’03) received the B.S. and M.S.
de-grees in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1998 and 2000, respec-tively, and is currently working toward the Ph.D. de-gree at the National Chiao Tung University, Hsinchu, Taiwan.
From 2000 to 2004, he was a Circuit Design Engi-neer with the Soc Technology Center (STC), Indus-trial Technology Research Institute (ITRI), Hsinchu, Taiwan. In 2005, he joined the National Chip Imple-mentation Center (CIC), National Applied Research Laboratories (NARL). His previous research has focused on CMOS front-end circuits for GSM and WLAN systems. His research interests include design and analysis the CMOS RF and millimeter-wave integrated circuits for wire-less communication systems.
Chien-Nan Kuo (S’93–M’97) received the B.S.
degree in electronic engineering from National Chiao Tung University, Hsinchu, Taiwan, in 1988, the M.S. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1990, and the Ph.D. degree in electrical engineering from the University of California at Los Angles (UCLA), in 1997.
In 1997, he joined ADC Telecommunications, San Diego, CA, as a Member of Technical Staff with the Mobile System Division, during which time he was involved in wireless base-station design. In 1999, hhe joined Broadband Inno-vations Inc. In 2001, he joined the Microelectronics Division, IBM. In 2002, he joined the faculty of National Chiao Tung University, as an Assistant Professor. His research interests include reconfigurable RF circuit and system integration design, low-power design for the application of wireless sensor networks, and development of circuit-package co-design in the system-in-package (SiP) tech-nique.
Dr. Kuo was a corecipient of the 2006 Best Paper Award presented at the 13th IEEE International Conference on Electronics, Circuits and Systems.
Ying-Zong Juang (S’93–M’98) received the M.S.
and Ph.D. degrees in electrical engineering from Na-tional Cheng Kung University, Taiwan, in 1992 and 1998, respectively.
In October 1998, he joined the institute of Chip Im-plementation Center (CIC), Hsinchu, Taiwan, during which time he was involved with RF circuit design and device modeling. From 1999 to 2000, he was in-volved with a project to create a new process flow to implement the BCD devices on the same chip. He is currently a Researcher and Director of CISD/CIC, where he has organized several projects, including top-down design platform for RF transceiver and 0.35/0.18m CMOS/microelectromechanical systems (MEMS) design environment. His interested topics include RF/MEMS module design, CMOS bio MEMS, and mixed-signal design for RF front-end.
