Power-Tracking Embedded Buck–Boost Converter
With Fast Dynamic Voltage Scaling for the
SoC System
Yu-Huei Lee, Student Member, IEEE, Shao-Chang Huang, Shih-Wei Wang, Wei-Chan Wu, Student Member, IEEE,
Ping-Ching Huang, Student Member, IEEE, Hsin-Hsin Ho, Yuan-Tai Lai,
and Ke-Horng Chen, Senior Member, IEEE
Abstract—A power-tracking embedded buck–boost converter with a fast dynamic voltage scaling (F-DVS) function is proposed to power the system-on-a-chip (SoC) system. To meet the power request of the SoC for different operation functions, fast up/down-tracking is implemented to achieve the F-DVS function. Recycling energy is also derived to minimize power dissipation during the down-tracking period. In addition, the peak current control and valley current control methods are utilized in the buck and boost operations, respectively, to minimize the effect of switching noise in high switching operation for compact solution. Moreover, the self-tuning pulse skipping mechanism extends the effective duty cycle to achieve voltage regulation and improves efficiency when the input voltage is close to that of the output. Through F-DVS, the tracking speed from 3 to 2 V and vice versa are 15 and 20 μs, respectively, with a high switching frequency of 5 MHz.
Index Terms—Buck–boost (BB) converter, dc–dc converter, dy-namic voltage scaling (DVS), peak current control (PCC), power tracking, pulse skipping, system-on-a-chip (SoC), valley current control (VCC).
I. INTRODUCTION
S
YSTEM-ON-A-CHIP (SoC) system is a design trend in to-day’s consumer portable devices. Power management mod-ule is demanded to have high efficiency, low output voltage rip-ple, and fast transient response at the same time. To effectively power the battery-operated portable system, dc–dc converter is utilized to provide a constant output voltage over a wide input voltage range from the Li-ion battery [1]–[3]. The buck–boost (BB) converter [4]–[20] can operate in either the buck or boost operation to convert a regulated output voltage according to the input voltage condition. However, the transition between theseManuscript received September 1, 2010; revised November 29, 2010; ac-cepted December 13, 2010. Date of current version February 7, 2012. This work was supported by the National Science Council, Taiwan, under Grants NSC 97-2221-E-009-172 and NSC 97-2220-E-009-027. Recommended for publication by Associate Editor Y. C. Liang.
Y.-H. Lee, S.-W. Wang, H.-H. Ho, and K.-H. Chen are with the Institute of Electrical Control Engineering, National Chiao Tung University, Hsinchu, 300 Taiwan (e-mail: khchen@cn.nctu.edu.tw).
S.-C. Huang is with eMemory Technology, Hsinchu 30265, Taiwan. W.-C. Wu and P.-C. Huang are with Richtek Technology Corporation, Hsinchu 30288, Taiwan.
Y.-T. Lai is with Material Science Center, National Tsing Hua University, Hsinchu 30013, Taiwan.
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2010.2101085
Fig. 1. System application of the PTE-BB converter for the SoC system in portable devices.
two different operations may result in large output voltage ripple due to their different operated characteristics. Thus, it is impor-tant to ensure smooth transition between the two operations in BB converter. As reported in [8], a three-mode dual-frequency two-edge modulation scheme is implemented to handle the tran-sition when the input voltage level is close to that of output. In addition, the feedforward control scheme is utilized to improve the mode transition and the line transient response in voltage-mode BB converters [10]–[12]. The transient response should be taken into consideration owing to the diffident power requests from the distinct operation modes in the SoC system. Although a digital control scheme is proposed to enhance the transient re-sponse [13], a digital signal processing unit is needed to provide the control signals.
Fig. 1 shows the system application of the proposed power-tracking embedded BB (PTE-BB) converter. To power the func-tion blocks in the SoC system, the PTE-BB converter can au-tomatically switch the operation modes to generate a regulated output voltage VO U T with different input voltage VBAT. For example, high-efficiency RF power amplifier is a critical part of the SoC system. The required power depends on the different operation mode, such as the demands for a large power sup-ply to achieve data transmission [15]–[19]. In the conventional dynamic voltage scaling (DVS) design [21]–[24], the settling time for achieving output voltage position is determined by the system loop response. However, the slow voltage tracking speed deteriorates the performance of the RF circuit, since the supply power is insufficient at the beginning of the data transmission pe-riod. As a result, the proposed PTE-BB converter presents a fast DVS (F-DVS) function that can achieve fast voltage-tracking re-sponse and precise voltage position through the signal Vcontrol sent from the SoC system. The optimum value of Vcontrolis gen-erated from the processor and converted by the digital-to-analog 0885-8993/$26.00 © 2010 IEEE
Fig. 2. Operations of the F-DVS function in the data transmission periods of the RF circuit in the SoC system.
converter (DAC) to indicate the different energy request of the SoC system to power management. Thus, high performance and high efficiency can be simultaneously achieved.
The operation of the proposed F-DVS function is shown in Fig. 2. When the data transmission period is activated, the signal
Vcontrolstarts up-tracking response in the PTE-BB converter to raise the output voltage for improving the driving capability. In addition, a larger power request is obtained by the busy series data transmission. VO U Tis returned to its nominal value when the data transmission period is over in order to minimize the power consumption for extending the battery life. Similarly, the signal Vcontrolalso enables the down-tracking response to meet the power demand in the standby period. Therefore, the F-DVS function of the PTE-BB converter achieves both fast voltage-tracking and adjustable output voltage. Moreover, to avoid the effect of system instability resulting from the switching noise in high switching operation, the PTE-BB converter utilizes the dual-mode operation, which includes the peak current control (PCC) [25] in the buck operation and the valley current control (VCC) in the boost operation, respectively. The self-tuning pulse skipping (SPS) mechanism is also implemented to achieve the smooth mode transition in the BB converter when the value of
VBAT is closed to that of VO U T.
In this paper, the structure of the proposed PTE-BB converter is described in Section II. The system operation is illustrated in Section III. Detailed circuit implantation is presented in Section IV. Experimental results are shown in Section V. Finally, the conclusion is made in Section VI.
II. PROPOSEDBB CONVERTERSTRUCTURE
The structure of the PTE-BB converter is shown in Fig. 3. The current-mode control is utilized to achieve fast transient response, better line rejection capability, and on-chip system compensation scheme at the same time. In addition, the output voltage ripple is minimized especially for some noise-sensitive blocks, such as the RF circuits in the SoC system. Using the high switching frequency in dc–dc converter can decrease the output voltage ripple and reduces the value of off-chip inductor to further reduce the printed circuit board area.
Fig. 3. Proposed structure of the PTE-BB converter with the F-DVS function.
The power stage in the PTE-BB converter contains six power switches, MA–MF, to achieve the energy transition and the F-DVS function. The signal VT R generated by the hystere-sis comparator enables the F-DVS function through the rising and falling edge triggers to achieve the up-tracking and down-tracking of the output voltage, respectively. The resistors R1and
R2form the voltage feedback to regulate the output voltage. The error signal VEAgenerated by a high-gain error amplifier makes a comparison with the summing signal, which is the summation of the current-sensing signal VS and the slope compensation signal, in order to generate the control duties, VBU and VBT, for the buck and boost operations, respectively. Besides, the current-sensing circuit realizes the high-speed current sensing at the high switching operation.
The dynamic slope compensation (DSC) circuit produces the slope compensation signals, Ibuck(com p) and Ib o ost(com p), to avoid the subharmonic oscillation in the PCC or VCC meth-ods, respectively. The mode detector circuit is used to determine the operation mode by generating the VBBsignal in the PTE-BB converter based on the conditions between the battery and the output. The master and slave control scheme is implemented with the SPS mechanism to ensure smooth mode transition. As such, the signal VBB with a low value indicates the buck operation, while the boost operation is utilized when VBB is forced to high. Moreover, the dual-mode proportional-integral (PI) compensator [26] guarantees the on-chip compensation through the system pole-zero cancellation in the current-mode control. The clock generator carries out the system clock Vclk with 5 MHz for high switching pulse width modulation (PWM) operation. The dead time and driver circuit, which are sup-plied by the supply voltage Vdrivegenerated through the maxi-mum power selector, produce the control signals SWA–SWF to drive the power switches, MA–MF, respectively, thereby enhancing the driving ability and avoiding the shoot-through current.
Fig. 4. F-DVS function contains fast (a) up-tracking and (b) down-tracking.
III. SYSTEMOPERATION
A. F-DVS Function
Fast transient response and short settling time are necessary to achieve the F-DVS function in the PTE-BB converter for the SoC system. Particularly, a high voltage supply is needed to provide better driving capability during the data transmission period. Fig. 4(a) shows the operating scheme of fast up-tracking with energy delivering path defined in the F-DVS function. The up-tracking process is divided into two steps in order to effec-tively control the inductor current. In step I, if VBAT is larger than VO U T, the PTE-BB converter operates in pure buck oper-ation with a maximum charging current control. Furthermore, a direct charging path, which is composed of the power switches with ME and MD, is adopted to accelerate the tracking speed, especially under the condition wherein only a small voltage dif-ference between VBAT and VO U T is derived at the beginning of the tracking response. In addition, once VO U T exceeds the value of VBATin the up-tracking response, the control scheme ends the direct charging path and enters into step II with a pure boost operation. The operation is switched to the boost opera-tion and uses a maximum charging current control until VO U T approaches the desired regulated voltage. Thus, with the two-step up-tracking procedure, VO U T can be raised up rapidly to meet the power request of the SoC system.
On the other hand, when the data transition ends, the sys-tem returns to the standby mode for power saving. The F-DVS
Fig. 5. Duty cycle modulation considers the noise effect in the BB converter when the value of VB ATis close to that of VO U T. (a) VCC method in the buck
operation. (b) PCC method in the boost operation.
function provides a fast down-tracking scheme as shown in Fig. 4(b). The down-tracking process is also divided into two steps to effectively achieve voltage tracking. The PTE-BB con-verter operates the reversed buck operation in step I to transfer the excessive energy back to the input through inductor when
VO U Tis larger than VBAT, achieving a fast down-tracking re-sponse and the minimized power dissipation. Moreover, step II is activated when VO U T is lower than the value of VBAT that the PTE-BB converter can deliver the energy from CO U T to battery through the maximum charging current control. Finally, step II ends until the value of VO U Tis close to the desired value. The power dissipation is minimized because of the recycled energy procedure during the down-tracking period. Therefore, the proposed PTE-BB converter simultaneously improves the voltage-tracking speed while extending the battery life.
B. PCC and VCC Methods for PTE-BB Converter
In the design of BB converter, it is difficult to maintain a low output voltage ripple when the value of VO U T is close to that of VBAT. If VBAT is a little larger than VO U T, the duty cycle of the buck operation would approaches nearly 100%, which is difficult to guarantee through the system control scheme be-cause of the interference in duty modulation generated from the switching noise and the driver delay. Similarly, the duty cycle in the boost operation is also hard to approaches 0% when the value of VBAT is a little smaller than that of VO U T.
The current-sensing method in the current-mode control in-cludes the PCC and VCC methods. If the VCC method is con-sidered as the modulation method in the buck operation, the switching noise would have a serious influence on the duty mod-ulation when VBATand VO U Tare nearly equal. Fig. 5(a) shows the instability caused by the switching noise effect in the buck operation with the VCC method, which leads to the increase of output voltage ripple. With the VCC method, the inductor starts to discharge through the positive trigger of the system clock
Vclk. The switching noise results in the instability due to the short inductor discharging period, which is limited by the large duty cycle. The large output ripple worsens the supply quality
Fig. 6. (a) Control method decision circuit. (b) Indication of the PCC method, VCC method, and SPS mechanism with different input/output voltage condi-tions.
of the BB converter. In commercial products, the blanking time used in the current-sensing circuit can prevent the interference with the undesired switching noise, but it induces a minimum value for the duty cycle. This means that the blanking time re-stricts the BB converter to extend the duty cycle once the value of VBATis close to that of VO U T. As a result, the PCC method is more suitable than the VCC method in the buck operation.
As VBAT decreases, the operation changes from the buck operation to the boost operation when VBAT becomes smaller than VO U T. Thus, the duty cycle is reset from 100% to 0%. Fig. 5(b) shows the PCC method used in the boost operation. The switching noise causes system instability due to the short inductor charging period. The blanking time technique is also applied to solve the instability issue caused by the switching noise in high switching operation. However, it fails to work correctly once the duty cycle approaches 0%, indicating that the VCC method must be adopted in the boost operation.
C. Control Method Decision and SPS Mechanism
The BB converter aims to work properly with a small voltage difference between VBATand VO U T. Nevertheless, the selection of either the PCC or VCC modulation methods determines the stability of BB converter shown in Fig. 5. The settling time of the voltage-tracking response may be extended due to the improper control method when the desired regulated voltage is set near
VBAT that deteriorates the performance of SoC systems. Thus, the proposed PTE-BB converter combines both the PCC and VCC methods in the buck and boost operations, respectively, to derive a stable operation in the wide input voltage range as well as a small output voltage ripple.
The control method decision circuit shown in Fig. 6(a) modu-lates the duty cycle from the error signal VEA, the sensing signal
Fig. 7. Proposed PTE-BB converter uses the SPS mechanism. (a) PCC method in the buck operation. (b) VCC method in the boost operation.
VS, and the slope compensation signal VC O M. VC O M is derived from the compensation currents, Ib cuk(com p) and Ib o ost(com p), in the buck and boost operations, respectively, to prevent sub-harmonic oscillation. Consequently, VBU and VBTcan be used to trigger the buck and boost operations, respectively. As shown in Fig. 6(b), the PCC method operates in the buck operation because the VCC method suffers from the problem of having a short inductor discharging period if the value of VBATis close to that of VO U T. Moreover, utilizing the VCC method in the boost operation is a better choice since the PCC method has a short inductor charging period when the low-duty cycle issue occurs.
The SPS mechanism depicted in Fig. 7 is utilized to extend the effective duty cycle, and thereby improving the regulation performance, minimizing the output voltage ripple, as well as eliminating the random transition between the two operations when the value of VBATis close to that of VO U T. As a result, the power conversion efficiency can be enhanced. The PCC method in buck operation shown in Fig. 7(a) defines a 10% duty cycle at the end of a PWM switching cycle. When VBAT decreases to reach VO U T with an increasing duty cycle, the switching would be bypassed by means of prohibiting the inductor dis-charge period in order to extend the duty cycle. Therefore, the effective duty cycle is stretched so as to ensure the summing signal intersecting with the signal VEA within the period of the 90% duty cycle at the next PWM switching cycle. It can allevi-ate the instability of the BB converter and the switching noise derived from the power stage. Similarly, as shown in Fig. 7(b), the VCC method in the boost operation is achieved with the SPS mechanism to regulate the output voltage if VBAT con-tinuously decreases to become much smaller than VO U T. The effective duty cycle can be extended to overcome the challenge of low-duty condition. In addition, the mode transition would occur if the continuous counting of the skip number exceeds an auxiliary value, leading to the achievement of the optimal transi-tion boundary in the proposed PTE-BB converter. The blanking time is also used in the current-sensing procedure to abate the effect resulted from the switching noise; this is because the SPS mechanism can extend the effective duty cycle in the PTE-BB converter. Given that the reduction of the switching period can
also improve the power conversion efficiency and guarantees the voltage regulation at the same time.
D. System Compensation in the PTE-BB Converter
The current-mode PTE-BB converter can be achieved using both the PCC and VCC methods. However, the system loop compensation network must be adjusted according to the distinct control methods. The control-to-output transfer function [27] of the PCC method in the buck operation Tbuck is expressed as, as shown (1), at the bottom of this page, where Gbuck is the loop gain, Mbuckis the inductor current slope, and Mcom p buck is the slope compensation signal. The current-mode control can separate the complex poles generated by the off-chip inductor and capacitor at power stage so as to derive only a single low-frequency pole ωp 1(buck), which is load-dependent and inversely proportional to the output load resistance RLOA Dand the output capacitor CO U T. The first nondominant pole ωp 2(buck)is located near to the switching frequency because of the current-mode control. The utilization of the slope compensation can determine the location of ωp 2(buck). The equivalent series resistance (ESR) on the output capacitor also contributes a left-half plane (LHP) zero ωz (buck). The expressions of ωp 1(buck), ωp 2(buck), and
ωz (buck) are expressed in (2). As a result, the PI compensator can be adopted to compensate the system in the PCC method buck operation: ωp1(buck) = 1 CO U TRLOA D ωp2(buck) = Mbuck
(Mbuck+ Mcom p buck)DbuckT
ωz (buck) =
1
RESRCO U T
. (2)
In addition, the control-to-output transfer function of the VCC method in the boost operation Tb o ost is expressed as, as shown (3), at the bottom of this page, where Gb o ost is the loop gain.
Mb o ost and Mcom p b o ost are the inductor current slope and the slope compensation signal, respectively. Similarly, the current-mode control in the boost operation generates a load-dependent pole ωp 1(b o ost)and a nondominant pole ωp 2(b o ost) that are af-fected by the slope compensation. However, a right-half plane (RHP) zero is derived at the power stage in the boost
opera-Fig. 8. Frequency response of the proposed PTE-BB converter with both the buck and boost operations under different load conditions.
tion, which deteriorates the system phase margin. However, it can be moved from RHP to LHP if the ESR on the output ca-pacitor is carefully selected. Nevertheless, a large ESR, which may increase the output voltage ripple, is not suitable for SoC applications. Hence, a high-frequency RHP zero exists in the boost operation of the PTE-BB converter because the interfer-ence on the system bandwidth is alleviated by using the small off-chip inductor with high switching operation. The respective expressions of ωp 1(b o ost), ωp 2(b o ost), and ωz (b o ost) are shown as follows: ωp1(b o ost)= 2 CO U TRLOA D ωp2(b o ost)= Mb o ost
(Mb o ost+ Mcom p b o ost)Db o ostT
ωz (b o ost)=
1
(CO U TRESR/(1− Db o ost))− (L/(1 − Db o ost)RLOA D)
.
(4)
The control-to-output frequency responses of the PTE-BB con-verter with the PCC method in buck operation and the VCC method in boost operation are shown in Fig. 8. The proposed dual-mode PI compensator can be used to achieve system com-pensation to ensure a large system bandwidth and an adequate phase margin.
Tbuck(s) = Gbuck(s)
1 + sRESRCO U T
(1 + sCO U TRLOA D) (1 + s(Mbuck+ Mcom p buck)DbuckT /Mbuck)
= Gbuck(s) 1 + (sωz (buck)) 1 + (sωp1(buck)) 1 + (sωp2(buck)) (1) Tb o ost(s) = Gb o ost(s)
1 + s (CO U TRESR/(1− Db o ost)− L/(1 − Db o ost)RLOA D)
(1 + s(CO U TRLOA D/2)) (1 + s(Mb o ost+ Mcom p b o ost)Db o ostT /Mb o ost))
= Gb o ost(s) 1 + sωz (b o ost) 1 + (sωp1(b o ost)) 1 + (sωp2(b o ost)) (3)
Fig. 9. Slope compensation (a) in the buck operation with the PCC method and (b) in the boost operation with the VCC method.
Fig. 10. Schematic of the DSC circuit.
IV. CIRCUITIMPLEMENTATION
A. DSC Circuit
Slope compensation is required to prevent subharmonic os-cillation, and thereby ensuring system stability when the duty cycle in the current-mode control is larger than 50%. To com-pensate for the PCC and VCC methods in the buck and boost operations, respectively, two distinct slope compensation signals were utilized in the proposed PTE-BB converter. The slope com-pensation schemes for the PCC and VCC methods are shown in Fig. 9(a) and (b), respectively. The slope compensation co-efficient ma PC C for the PCC method must be proportional to
VO U T in the buck operation. On the other hand, VBAT is pro-portional to the slope compensation coefficient ma VC Cfor the VCC method in the boost operation. As a result, the proposed DSC circuit can generate the slope compensation coefficient, which is adjusted by the VBATand VO U Tfor the PCC and VCC methods, respectively. It can minimize the interference on the bandwidth of the current loop resulted from the variations of
VBAT, VO U T, or the switching noise.
Fig. 10 shows the DSC circuit, which generates the slope com-pensation signal according to the different operation modes. The voltage-to-current (V–I) converter consisting of the operational amplifier M1 and the resistor R1 converts the current IC A us-ing VO U Tand VBAT in the PCC method of the buck operation and the VCC method of the boost operation, respectively. Vclk resets the charge on the capacitor CA when it is set to high at the beginning of every switching cycle. When Vclk is set to
Fig. 11. Schematic of the mode detector circuit with the SPS mechanism.
low, IC A starts to charge the capacitor CA, which carries out a sawtooth waveform at node V2. The voltage across the capacitor
CAis approximately equal to the voltage across the resistor R2 since the source–gate voltages of M6and M8are approximately equal. Hence, the MOSFET M8 and the resistor R2 form an-other V–I converter to generate a sawtooth current IC B. In the PCC method of the buck operation, the slope compensation sig-nal Ibuck(com p)is derived from the current mirror structure IC B which is proportional to VO U T owing to the wide range duty cycle, as follows: Ibuck(com p)= IC B = R6 (R5+ R6)· VO U T· Δt R1· R2· CA . (5)
Similarly, to achieve the system slope compensation, IC A must be proportional to VBATin the VCC method of the boost opera-tion. Thus, the slope compensation signal Ib o ost(com p)is derived as
Ib o ost(com p)= Ioff set−
R4
(R3+ R4)·
VBAT· Δt
R1· R2· CA
. (6)
In addition, as IC A increases, the voltage V2 decreases due to the discharge of capacitor CA. Thus, the compensation currents,
Ibuck(com p) and Ib o ost(com p), would increase and decrease, re-spectively, so as to dynamically adjust the slope compensation signal to improve the system response.
However, at the moment of transition between the buck and boost operations, the output voltage ripple may be increased because of the different operation modes. The slope compen-sation signal is added to the current-sensing signal in the PCC method, but is subtracted to the current-sensing signal in the VCC method owing to the opposite duty modulation scheme in order to achieve a stable current-mode operation. Thus, a volt-age gap is realized, in which the summing signal becomes dis-continuous and causes an abnormal operation and large output voltage ripple at the mode transition point. To achieve a smooth mode transition, the offset current Ioff set, as defined in (7), is
Fig. 12. Flow chart of the SPS mechanism in the proposed PTE-BB converter.
introduced to reduce the output voltage variation [28]. Ioff set depends on the input and output voltages, which is adopted in the DSC circuit. The summing coefficients, k1 and k2, are proportional to VO U Tand VBAT, respectively:
Ioff set= k1VO U T+ k2VBAT =
R6 (R5+ R6)· VO U T R1 + R4 (R3+ R4) ·VBAT R1 . (7)
B. Mode Detector Circuit
The mode detector circuit with the SPS mechanism shown in Fig. 11 is implemented to determine either the buck or the boost operation according to the relationship between VBATand
VO U T. To achieve an accurate mode transition between the two operations over a wide load range for minimizing output voltage ripple, the on-resistance RSW of each power MOSFET must be considered. Consequently, the theoretical boundary condition of the mode transition is depicted in
VBAT− 2(Iload× RSW) = VO U T, if LX1 = LX2. (8) The operation of the mode transition is divided into the master and the slave controls. The master control works when VBAT and VO U Tdiffer significantly from each other, operating with the simultaneous on state of power switches, A and D, and deciding the operation mode by comparing LX1 and LX2 directly. The two pairs of common-gate amplifiers form a comparator that realizes a push–pull stage at its output node in order to enhance the transient speed.
The slave controller consists of two counters and logic gates to improve the transition accuracy through the pulse-skip func-tion when the value of VBATis extremely close to that of VO U T. Unlike some prior arts including the BB mode as a buffer oper-ation for smooth mode transition, the proposed SPS mechanism can skip energy paths automatically to extend the effective duty cycle to overcome the boundary condition in the BB converter over a wide voltage range.
In the buck operation, a pulse signal defined as 90% of the whole PWM duty cycle is triggered by the system clock Vclk.
Counter I calculates the number of skipping pulses to determine
the mode transition for power saving. Detector I would output a reset pulse signal, which is derived from theNORoperation of the control signal SWAand the 90% duty cycle when the buck duty cycle exceeds the effective value to enable Counter I to prepare for mode transition. As a result, the PTE-BB converter switches from the buck operation to the boost operation when the number of skipping pulses exceeds the designed value. Similarly, the operation in the boost operation is also controlled by the same mechanism controlled by the Detector II and Counter II. It can also ensure the smooth mode transition when the value of VBAT is extremely close to that of VO U T. The flow chart of the SPS mechanism is depicted in Fig. 12. The variable ITRP represents the interconnection of the error signal and the summing signal. The 90% duty cycle in the PCC method of the buck operation and the VCC method of the boost operation are represented by KBuck and KBo ost, respectively. The variable Z is the designed value in the counter that determines the activity of mode transition between the buck and the boost operations.
C. Current-Sensing Circuit
A simple way of current sensing is achieved by inserting the sensing resistor into the series of the inductor current path. However, the efficiency is seriously deteriorated at the heavy load conditions. The proposed current-sensing circuit depicted in Fig. 13 can reduce unnecessary power loss without using power-dissipated sensing resistor.
The transistor MS produces the sensing current Isenseduring the turn-on period of the power switch MA. The source-to-drain voltages of MA and MS are approximately equal because of the implementation of the common-gate amplifier, which is composed of M3–M7. M1isONand M2isOFFduring the turned-on period of MA. Bias current IBresults in the current difference between the sensing currents, Isenseand Isense1. To enhance the current-sensing accuracy, transistor M9, which has the same
Fig. 13. Schematic of the current-sensing circuit.
Fig. 14. Dual-mode PI compensator.
aspect ratio as the current mirror structure of M3 and M4, is added to provide a compensative current IB. Consequently, the current-sensing signal is produced by the voltage signal VS across the resistor R1. On the other hand, VS would be reset to
VBAT by the multiplexer and the MOSFETs M10 and M11 at the charging period of the boost operation to achieve the VCC method.
D. Dual-Mode PI Compensator
As shown in Fig. 14, the proposed internal dual-mode PI compensator can maintain a stable closed-loop response in both the buck and boost operations compared with a conventional PI compensator [26]. The capacitor multiplier technique utilized to on-chip compensation achieves with only a small capacitor
Cp that reduces the silicon area [29]. It generates the system dominant pole to ensure stability in both the buck and boost operations. In addition, when the PTE-BB converter operates in the PCC method of the buck operation, the switch is turned off to generate a low-frequency compensation zero to cancel the effect of the system pole ωp 1(buck). Aside from this, the system load dependent pole in the boost operation ωp 1(b o ost) moves to higher frequencies compared with the buck operation under the same output load condition. The VBBsignal forces the switch on in order to reduce the compensation resistance at the PI compensator. This means that the compensation zero in the boost operation is tracked to the higher frequencies in order to achieve the pole-zero cancellation for improving system stability. Thus,
Fig. 15. Measured steady-state operation of the PTE-BB converter. (a) Buck operation with load current of 120 mA when VB AT = 4.2 V and VO U T =
3.3 V. (b) Boost operation with load current of 220 mA when VB AT = 2.6 V
and VO U T= 3.3 V.
in both the buck and boost operations, the proposed dual-mode PI compensator carries out the same crossover frequency to achieve better performance even at the mode transient period.
V. EXPERIMENTALRESULTS
The proposed PTE-BB converter with F-DVS function was fabricated by 0.25-μm CMOS process. Supply voltage VBAT is set in the range of 2.5–4.5 V defined by the range of Li-ion battery. The typical output voltage is 3.3 V, regulated by the switching frequency of 5 MHz so that the off-chip inductor and capacitor can be utilized with 1 μH and 0.88 μF, respectively. The small-size off-chip output filter can minimize the volume of the power module in portable devices. Fig. 15 shows the steady-state operation of the proposed PTE-BB converter. The regulated output voltage of 3.3 V under 4.2 V input voltage supply with a 120-mA load current is shown in Fig. 15(a). The switching frequency is kept at 5 MHz with a duty cycle of 78%. The boost operation is demonstrated in Fig. 15(b) with a regulated output voltage of 3.3 V under input voltage of 2.6 V. With duty cycle of 21% and 220-mA load current, the 5-MHz high switching operation is achieved.
Fig. 16 shows the SPS mechanism in the buck operation with the PCC method. When VBAT is close to VO U T in the PTE-BB converter, the SPS mechanism can ensure the smooth transition response and avoid system instability resulting from high switching noise. When VBAT is lowered to 3.5 V with a fixed VO U Tof 3.3 V as shown in Fig. 16(a), the SPS mechanism
Fig. 16. Measured SPS mechanism in the buck operation with load current of 120 mA. (a) If VB AT = 3.5 V and VO U T= 3.3 V, the skipping number is 1.
(b) If VB AT= 3.35 V and VO U T= 3.3 V, the skipping number is 4.
is activated to skip the switching numbers at the power stage in order to extend the effective duty cycle. At this time, the PTE-BB converter operates in the transition region from the buck operation to the boost operation. Similarly, if the VBAT further decreases to 3.35 V as shown in Fig. 16(b), the number of the skip operation is increased during every effective switching cycle. Thus, the stable operation of the proposed high switching PTE-BB converter is guaranteed, and an adequate duty cycle is derived when the value of VBATis close to that of VO U T.
Fig. 17 shows the SPS mechanism in the boost operation with the VCC method. The switching number is decreased when the PTE-BB converter enters the transition region from the boost operation to the buck operation. The smaller voltage difference between VBATand VO U Tis derived, the more skipping number of the SPS mechanism is achieved. The equivalent duty cycle can yield the correct operation for the high switching PTE-BB converter. If the skipping number exceeds the defined value in the mode detector circuit, the operation mode can be switched from the boost operation to the buck operation in order to achieve a smooth transition response and enhance efficiency.
Fig. 18 shows the F-DVS function for the SoC system. The up-tracking response shown in Fig. 18(a) demonstrates that VO U T arises from 2 to 3 V with the settling time of 20 μs. The signal
Vcontrol, which is generated by the DAC according to the demand from processor in the SoC, activates the tracking response for F-DVS function. The maximum charging current control works in both pure buck and boost operations. It helps regulate the inductor peak current and avoid the overcharge at the up-tracking response. Fig. 18(b) shows the down-tracking response when
Fig. 17. Measured SPS mechanism in the boost operation with load current of 220 mA. (a) If VB AT= 3.1 V and VO U T= 3.3 V, the skipping number is
1. (b) If VB AT= 3.2 V and VO U T= 3.3 V, the skipping number is 2.
Fig. 18. Measured F-DVS function. (a) Up-tracking response. (b) Down-tracking response.
TABLE II
COMPARISON OF THEPREVIOUSBB CONVERTERMETHODOLOGIES
VO U T decreases from 3 to 2 V with a settling time of 15 μs. The measured inductor current waveform indicates the work of reversed buck and boost operations to accelerate the tracking response. Additionally, the recycled energy procedure during the down-tracking period minimizes the power dissipation in the proposed PTE-BB converter.
Fig. 19 shows the chip micrograph and the prototype of the proposed PTE-BB converter. The occupied silicon area is about 4.86 mm2 owing to the use of six power switches to achieve the F-DVS operation for the SoC system. Fig. 20 shows the measured output voltage ripple with different skipping numbers when the value of VBAT is close to that of VO U T. The maximum skip number in the SPS mechanism is five in the proposed design. The output ripple in both the buck and boost operations is derived below the allowable value for improving the performance of the SoC system. Fig. 21 shows the power conversion efficiency with a peak value of 91%. The SPS mechanism skips the switching cycle in the mode transition period to extend the equivalent duty cycle, and thereby enhancing the power conversion efficiency. When
VBAT is very close to VO U T, the SPS mechanism can even achieve an almost direct conduction from VBATto VO U T. Thus, the switching number of power stage is reduced that the peak efficiency can be derived shown in Fig. 21. However, owing to the nonideal power loss, such as the conduction loss, in power stage, the actual mode transition point between the buck and the boost modes would become larger than that of the ideal value. Therefore, the measured peak efficiency of the proposed
Fig. 19. (a) Chip micrograph. (b) Prototype of the proposed PTE-BB converter.
PTE-BB converter with VO U T = 3.3 V is derived at VBAT = 3.6 V, rather than that at VBAT = 3.3 V. The detailed design specifications are listed in Table I. Moreover, the comparisons of the prior BB converters are shown in Table II. The proposed
Fig. 20. Measured output voltage ripple with different skipping numbers in SPS mechanism.
Fig. 21. Measured power conversion efficiency of the proposed PTE-BB converter.
PTE-BB converter with the current-mode control can achieve the F-DVS operation, which is suitable for the SoC system.
VI. CONCLUSION
The proposed high switching current-mode PTE-BB con-verter with F-DVS function was fabricated by 0.25-μm CMOS process. To effectively power the SoC system, the F-DVS func-tion rapidly adjusts the output voltage value to meet the differ-ent power request. In addition, when a small voltage difference exists in VBATand VO U T, the utilization of the PCC and VCC methods in the buck and boost operations, respectively, can elim-inate the system instability caused by switching noise to ensure a stable voltage regulation. Moreover, compared with the tradi-tional method, the SPS mechanism helps to extend the effective duty cycle using pulse skipping to obtain a regulated output volt-age in mode transition and enhance power conversion efficiency. The DSC circuit and the dual-mode PI compensator are pro-posed to stabilize the system in both buck and boost operations. The fast-tracking response and the recycling energy are achieved in the F-DVS function with a switching frequency of 5 MHz.
ACKNOWLEDGMENT
The authors would like to thank Richtek Technology Corpo-ration and Chunghwa Picture Tubes, Ltd., for their help.
REFERENCES
[1] B. Sahu and G. A. R. -Mora, “A low voltage, dynamic, non-inverting, synchronous buck-boost converter for portable applications,” IEEE Trans.
Power Electron., vol. 19, no. 2, pp. 443–452, Mar. 2004.
[2] S. Zhou and G. A. R. -Mora, “A high efficiency, soft switching DC–DC converter with adaptive current-ripple control for portable applications,”
IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 4, pp. 319–323, Apr.
2006.
[3] W. R. Liou, M. L. Yeh, and Y. L. Kuo, “A high efficiency dual-mode buck converter IC for portable applications,” IEEE Trans. Power Electron., vol. 23, no. 2, pp. 667–677, Mar. 2008.
[4] Datasheet “TPS63000: High Efficient Single Inductor Buck-Boost Con-verter with 1.8A Switches,” Texas Instruments, 2008.
[5] Datasheet “LTC3440: Micropower synchronous buck-boost DC/DC con-verter,” Linear Technol. Corp., 2001.
[6] Datasheet “LTC3454: 1A Synchronous Buck-boost High Current LED Driver,” Linear Technol. Corp., 2005.
[7] P. Midya, K. Haddad, and M. Miller, “Buck or boost tracking power converter,” IEEE Trans. Power Electron. Lett., vol. 2, no. 4, pp. 131–134, Dec. 2004.
[8] X. Ren, X. Ruan, H. Qian, M. Li, and Q. Chen, “Three-mode dual-frequency two-edge modulation scheme for four-switch buck-boost con-verter,” IEEE Trans. Power Electron., vol. 24, no. 2, pp. 499–509, Feb. 2009.
[9] J. Chen, D. Maksimovic, and R. W. Erickson, “Buck-boost PWM convert-ers having two independently controlled switches,” in Proc. IEEE Power
Electron. Spec. Conf. (PESC), 2001, pp. 17–21.
[10] P.-C. Huang, W.-Q. Wu, H.-H. Ho, and K.-H. Chen, “Hybrid buck-boost feedforward and reduced average inductor current technique in fast line transient and high-efficiency buck-boost converter,” IEEE Trans. Power
Electron., vol. 25, no. 3, pp. 719–730, Mar. 2010.
[11] H.-J. Yang, K.-H. Chen, and Y.-P. Lee, “Feed-forward pulse width modu-lation for high line regumodu-lation buck or boost converter,” in Proc. IEEE Int.
Symp. Circuits Syst., May 2007, pp. 785–788.
[12] B. Arbetter and D. Maksimovic, “Feed-forward pulse-width modulators for switching power converters,” in Proc. IEEE Power Electron. Spec.
Conf. (PESC), 1995, pp. 601–607.
[13] Y.-J. Lee, A. Khaligh, A. Chakraborty, and A. Emadi, “Digital combina-tion of buck and boost converters to control a positive buck-boost converter and improve the output transients,” IEEE Trans. Power Electron., vol. 24, no. 5, pp. 1267–1279, May 2009.
[14] F. Luo and D. Ma, “Design of digital tri-mode adaptive-output buck–boost power converter for power-efficient integrated systems,” IEEE Trans. Ind.
Electron., vol. 57, no. 6, pp. 2151–2160, Jun. 2010.
[15] B. Sahu and G. A. R. -Mora, “A high efficiency WCDMA RF power amplifier with adaptive dual mode buck-boost supply and bias-current control,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 3, pp. 238– 240, Mar. 2007.
[16] J. N. Kitchen, C. Chu, S. Kiaei, and B. Bakkaloglu, “Combined linear and Δ-modulated switch-mode PA supply modulator for polar transmitters,”
IEEE J. Solid State Circuits, vol. 44, no. 2, pp. 404–413, Feb. 2009.
[17] W.-Y. Chu, B. Bakkaloglu, and S. Kiaei, “A 10 MHz bandwidth, 2 mV ripple PA regulator for CDMA transmitters,” IEEE J. Solid State Circuits, vol. 43, no. 12, pp. 2809–2819, Dec. 2008.
[18] M.-K. Nguyen, Y.-G. Jung, Y.-C. Lim, and Y.-M. Kim, “A single-phase Z-source buck–boost matrix converter,” IEEE Trans. Power Electron.,
vol. 25, no. 2, pp. 453–462, Feb. 2010.
[19] R. Paul, L. Corradini, and D. Maksimovic, “Modulated digitally con-trolled non-inverting buck-boost converter for WCDMA RF power ampli-fiers,” in Proc. IEEE Appl. Power Electron. Conf. Expo., Feb. 2009, pp. 533–539.
[20] F. Gao, P. C. Loh, R. Teodorescu, F. Blaabjerg, and D. M. Vilathgamuwa, “Topological design and modulation strategy for buck-boost three-level inverters,” IEEE Trans. Power Electron., vol. 24, no. 7, pp. 1722–1732, Jul. 2009.
[21] M. Barai, S. Sengupta, and J. Biswas, “Digital controller for DVS-enabled DC–DC converter,” IEEE Trans. Power Electron., vol. 25, no. 3, pp. 557– 573, Mar. 2010.
[22] S. Xiao, W. Qiu, G. Miller, T. X. Wu, and I. Batarseh, “An active compen-sator scheme for dynamic voltage scaling of voltage regulators,” IEEE
Trans. Power Electron., vol. 24, no. 1, pp. 307–311, Jan. 2009.
[23] A. Soto, A. D. Castro, P. Alou, J. A. Cobos, J. Uceda, and A. Lotfi, “Analysis of the buck converter for scaling the supply voltage of digital circuits,” IEEE Trans. Power Electron., vol. 22, no. 6, pp. 2432–2443, Nov. 2007.
[24] S. Das, D. Roberts, S. Lee, S. Pant, D. Blaauw, T. Austin, K. Flautner, and T. Mudge, “A self-tuning DVS processor using delay-error detection and correction,” IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 792–804, Apr. 2006.
[25] J. E. -Marti, E. S. -Kilders, E. Maset, A. Ferreres, J. M. Blanes, A. Garrigos, J. Jordan, and V. Esteve, “Phase margin degradation of a peak current controlled converter at reduced duty cycle,” IEEE Trans. Power Electron., vol. 25, no. 4, pp. 863–874, Apr. 2010.
[26] K.-H. Chen, C.-J. Chang, and T.-H. Liu, “Bidirectional current-mode capacitor multipliers for on-chip compensation,” IEEE Trans. Power
ward the Ph.D. degree at the Institute of Electrical Control Engineering, National Chiao Tung Univer-sity, Hsinchu, Taiwan.
He is a Faculty Member at the Mixed Signal and Power Management IC Laboratory, Institute of Elec-trical Control Engineering, National Chiao Tung Uni-versity. His current research interests include the power management integrated circuit design, light-emitting diode driver IC design, and analog integrated circuits.
Shao-Chang Huang received the B.S. and M.S.
degrees in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, in 1994 and 1996, respectively.
From 1996 to 1998, he was an Officer in national compulsory military service. From 1998 to 1999, he was involved in thin-film-transistor device at ERSO in ITRI, Taiwan. From 1999 to 2006, he worked on ESD/Latch-up/IO research in UMC, Ltd., HBA, Ltd., TSMC, Ltd., and NOVATEK, Ltd. As a UMC Engi-neer, he worked on 90-nm process ESD solutions at IBM, Fishkill, NY, in 2001. In 2006, he joined eMemory Technology, Hsinchu, Taiwan, where he is currently the ESD/IO Department Manager. He is the author or coauthor of more than eight papers published in journals and conferences, and holds more than 20 patents. His current research interests include ESD/Latch-up devices and circuits, and I/O related circuits.
Shih-Wei Wang was born in Hualien, Taiwan, in
1980. He received the B.S. degree from the Depart-ment of Electrical Engineering, National Taiwan Uni-versity of Science and Technology, Taipei, Taiwan, in 2006, and the M.S. degree from the Department of Electrical and Control Engineering, National Chiao Tung University, Hsinchu, Taiwan, in 2010, where he is currently working toward the Ph.D. degree at the Institute of Electrical Control Engineering, National Chiao Tung University, Hsinchu, Taiwan.
His research interests include the design of switch-mode power converters, linear regulators, analog integrated circuits, and mixed-signal integrated circuits.
Wei-Chuan Wu (S’09) was born in Changhua,
Taiwan. He received the B.S. and M.S. degrees from the Department of Electrical and Control Engineer-ing, National Chiao Tung University, Hsinchu, Tai-wan, in 2007 and 2009, respectively.
He was a member of the Mixed Signal and Power Management IC Laboratory, National Chiao Tung University. He is currently with Richtek, Ltd., Hsinchu. His research interests include the design of power management circuit, LED driver ICs, and the analog integrated circuit designs.
Hsin-Hsin Ho was born in Taipei, Taiwan. She
received the B.S. degree in electrical and control engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2006, where she is currently working toward the Ph.D. degree in electrical and control engineering.
Her research area contains many projects of LED driver ICs and power management ICs at Low Power Mixed Signal Laboratory. Her interests include power management circuit designs, LED driver ICs, and analog integrated circuit designs.
Yuan-Tai Lai received the B.S. degree in applied
chemistry from Providence University, Taichung, Taiwan, in 2000, the M.S. degree in chemistry from Chung Yuan Christian University, Jhongli City, Tai-wan, in 2002, and the Ph.D. degree in chemical and materials engineering from National Central Univer-sity, Jhongli City, in 2008.
He is a Project Manager at the Material Science Center, National Tsing Hua University, Hsinchu, Tai-wan. He has been involved in the design and analysis of magnetic components, integration of inductors and semiconductors for 3-D-system-in-package.
Ke-Horng Chen (M’04–SM’09) received the B.S.,
M.S., and Ph.D. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1994, 1996, and 2003, respectively.
From 1996 to 1998, he was a part-time IC Designer at Philips, Taipei. From 1998 to 2000, he was an Ap-plication Engineer at Avanti, Ltd., Taiwan. From 2000 to 2003, he was a Project Manager at ACARD, Ltd., where he was involved in designing power manage-ment ICs. He is currently an Associate Professor in the Department of Electrical Engineering, National Chiao Tung University, Hsinchu, Taiwan, where he organized a Mixed-Signal and Power Management IC Laboratory. He is the author or coauthor of more than 80 papers published in journals and conferences, and also holds several patents. His current research interests include power management ICs, mixed-signal circuit designs, display algorithm and driver designs of liquid crystal display (LCD) TV, red, green, and blue color sequential backlight designs for optically compensated bend panels, and low-voltage circuit designs.
