Watermarking based IP core protection

Watermarking Based IP Core Protection

Yu-Cheng

Fan and Hen- Wai

Tsao

Integrated System Lab

Department of Electrical Engineering and Graduate Institute of Electronics Engineering

National Taiwan University, Taipei, Taiwan, 10617,

R.O.C.

E-mail

:

d9921004@ee.ntu.edu.hv

ABSTRACT

This paper presents a watermarking technique for intellectual property

(IP)

core protection. We propose a method for embedding a watermark into

IP

core. In this work, we establish principles for development of new watermarking-based IP protection procedures. This technique is applicable to IP-based design. The proposed technique successfully survives synthesis, placement and routing. ARer the chip has been packaged, it's still easy to detect the ownership rights of the

IP

provider.

1.

INTRODUCTION

The advance of semiconductor processing technology has led to a rapid increase in IC design complexity. 1P-based design has become a major concem in IC industries [I]. Design reuse has led to the development of intellectual property protection techniques. The protection of virtual components becomes more and more important. One potential solution for claiming the ownership is to use watermarks. Watermarking is a technique traditionally used to securely identify the authenticity of the source of image, video or audio. Recently, a number of watermarking-based IP protection techniques have been proposed. In the literature, several techniques have been developed for

IP

core protection. Although

some researchers have investigated into the physical design level, few researches have been done on behavioral design level. In [Z], Andrew developed the protocols for IP protection at the physical design level, using the concept of constraint-based watermarking. In [3], Naveen Narayan proposed a method for embedding a watermark by modifying the number of vias or bends used to mute the nets in a design. All of these techniques embed watermark at the physical design level [4][5][6][7]. After synthesis, placement and routing, layout of the soft IP Core will be changed. These techniques are therefore not enough to protect the ownership rights of the soft IP Core. Besides, we must look at the photomicrograph if we want to check the ownmhip rights. These methods are not only complicated but also inconvenient. It's very difficult to detect the ownership rights ofthe IP provider after the chip has been packaged.

In order to solve these problems, we propose a method for embedding a watermark into soR IP c o x The watermark is embedded into the test circuit. The generality of soft

IPS

will keep the test circuits aRer integrating IPS into full SOCs[8]. The designer provides the test vectors (input and output vectors) IO

detect the packaged-chipr91. After integrating

IPS

into full SOCs,

the only signal in IP that we can trace is the test signal. If we combine test circuit with watermark generating circuit, we can secure ownership rights of the IP provider easily. It's also easy to detect the ownership rights of the IP provider. Afler the chip has been packaged, any IP in the chip may he observed and tested. In test mode, the appointed IP sends output test panems and watermark sequence. We can get ownership rights of the IP provider according to watermark sequence. The IP provider is able to trace a company for unauthorized resold copies of the IP. Because the waterhark generating circuit has been designed on behavioral level, the proposed embedding technique can survive the synthesis, placement and routing.

The paper is organized as follows. IP-based design flow with watermark is described in Section 2. ,Section 3 describes experimental results and discussions. In Section 4, the conclusion of this paper is stated. The references are shown in Section 6 .

2. IP

BASED DESIGN FLOW WITH

WATERMARK

We propose a new watermarking technique to solve the copy detection problem. Figure 1 describes the IP-based design flow with watermark. We use the digital watermarks with visually recognizable panems. The owner of the IP tries to design a

uniquely identifying watermark that may be a personal seal, an organization logo, or designer's signature. First of all, the watermark is generated as a binary pattem and then permuted to disperse the spatial relationship according to some pseudorandom order. We design a watermark generating circuit to generate the watermark bit-streams.

ARer the watermark generating circuit has been designed, we combine test circuit with watermark generating circuit. When the chip is in test mode, the chip will send out watermark sequence and test pattems. According to the watermark sequence, we can get ownership rights of the IP provider. How to combine test circuit with watermark generating circuit is very important. We propose five methods to combine test circuit with watermark generating circuit and analyze the advantage and the disadvantage ofeach method:

a) Headed Watermark Sequence Method: When the chip is in test mode, the chip sends out watermark sequence first. After sending out all watermark sequence, the chip sends output test pattems. (Fig. 2(a)) The watermark sequence is like the header

+Watermark

I

Circuit

Watermark

Figure 1. "Watermarking Based 1P Core Protection'' Design Flow

of a bit-stream. Therefore, we call this scheme "Headed Watermark Sequence Method." This method extracts the watermark simply. The drawback of the method is that the watermark is easy to detect or remove.

b) Periodic Watermark Sequence Method When the chip is in test mode, the chip will send out watermark sequence and test pattern alternately. (Fig. 2(b)) The watermark sequence appears periodically. Therefore, we call the proposed this scheme "Periodic Watermark Sequence." We can extract the watermarlr at any time. It is also easy to detect because the watermark appears periodically.

c) Cyclic Redundancy Watermark Sequence Method: When the chip is in test mode, the chip sends n-bit output tcst pattems. (Fig. Z(c)) After the output test pattems are sent, tho chip sends one bit watermark data. The chip sends n-bit output test pattems and one bit watermark data altemately. The watermark sequence and output test patterns appear cyclically. The watermark data is like the redundancy bit near the test pattern every n bits. Therefore, we call the proposed this scheme "Cyclic Redundancy Watermark Sequence Method." We cafl extract the watermark every n bits output test pattems and detect the ownership rights from the watermark sequence. It is easy to extract the watermark and hard to destroy ownership rights. d) Random Watermark Sequence Method We try to generate a

pseudorandom sequence and store it in the memory first. According to the random order, the chip sends watermark data. For example, if the random sequence is 1

.

5

.

2

.

4 ~ 7, the

chip sends one bit output test pattern, one bit watermark data, five bits output test pattems, one bit watermark data, two bits output test pattems, one bit watermark data

,

and so on. (Fig. 2(d)) This method has high security. It is hard to be detected and

removed. The drawback of the method is that high hardware complexity.

e) Operational Watermark Sequence Method: To perform exclusive-or (XOR) operation on the watermark sequence and output test pattems to obtain new pattems. (Fig. 2(e)) When the chip is in test mode, the chip sends the new patterns. We can extmct the watermark after exclusive-or (XOR) operation on the new pattems and test patterns to get a watermark sequence. This method has high security. It is hard to be detected and removed. The drawback of the method is that if some bits are in error, we could not recognize which circuit is fail (watermark generating circuit or test circuit).

010011100000

...

lllololooooooo

I

--

I

I

watermark Test Pattcms sequence

(a) Headed Watermark Sequence Method

Watermark

Watermark Test Pattems

Sequence Sequence

@) Periodic Watermark Sequence Method

Watermark W a l e m k

( c ) Cyclic Redundancy Watermark Sequence Method

Watermark

f

I

Bi; ... 101101011000000000

...

I

U

U

U

U

Interval: I 5 2 4 Test Panems

(d) Random Watermark Sequence Method

OlWl I I W D O W O (Watermark) XOR lllOlOlOOOOOW CrestPamems

~oioo~ooonowo (N- paaemr)

Watermark Sequence Extract:

I

ioicmiooooocmo MW Pancms)

XOR I I

~o~oiooooooo

(~cstpanems) OlOOllmdDdwO (Watermark) (e) Operational Watermark Sequence Method

Figure 2. We propose five methods to combine test circuit with watermark generating circuit

I

n

I

-b _Panem! Output

Figure 3. Architecture of the watermark generating circu! (Headed watermark sequence method)

We can choose one of the above methods depending on our requirement. For example, we use the “Headed Watermark Sequence Method.” We design the watermark generating circuit and combine the test circuit with watermark generating circuit. The architecture of the circuit is shown in Figure 3. When someone uses this chip in test mode, the “test mode signal” control the watermark generating circuit and test circuit. The watermark generating circuit is composed of PIS0 (parallel in serial out register) and several inverter gates. The parallel watermark data is generated when the test mode signal is active. The PIS0 translates the parallel watermark data into the serial watermark sequence. At the same time, test patrems input into the chip. In this method, the chip sends out watermark sequence first and sends out test pattem later. According to the watermark information, the IP provider is able to rearrange the watermark sequence using the predefined pseudorandom order. The IP provider is able to trace a dishonest company for unauthorized resold copies of the IP. We don’t need to look at ihe photomicrograph if we want to check the ownership rights. This method is easier than conventional methods.

3. EXPERIMENTAL RESULTS AND

DISCUSSIONS

We have performed a set of experiments to evaluate the effectiveness of the “watermarking bascd IP core protection”. In order to verify the properly of the architecture proposed, we present five IPS to validate this approach in this section.

3.1

Results

To verify the feasibility of the architecture proposed, we present some results of experiments. Watermarking results for the synthesis experiments are summarized in Table 1

.

We report synthesis results for each IP. These results provide the hardware cost overhead. We design five kinds of watermark generating circuits that can generate 20 bits watermark sequence separately. The Headed Watermark Sequence Method needs 207-223 gates. The Periodic Watermark Sequence Method needs 349-371 gates. The Cyclic Redundancy Watermark Sequence Method needs 297-314 gates. The Random Watermark Sequence Method needs 509-533 gates. The Operational Watermark Sequence Method

needs 625-641 gates. We just increase area no more than five percent to add watermark-generating circuit. Our proposed methods are low hardware cost.

Table

II

summarizes the results of synthesis, placement and routing. Because we embed the watermark into the test circuit at the front-end, the watermark function is not changed after synthesis. No maner what kind of constraint is used, we still can extract the watermark sequence correctly. Afler placement and routing, we can still detect ownership rights according to the watermark sequence.

Table

Ill

summarizes the results of gates tampering and P&R tampering. Because the watermark generating circuit is hidden in the whole chip, it cannot render visible artifact in Synopsys schematic view. If attacks want to modify the watermark generating circuit from synthesis circuit or chip layout, they destroy the normal

1P

function at the same time. We attempt to temper synthesis circuit and layout. The normal function ofthe IP has distortion simultaneously. We still can extract the greater part ofwatermark sequence even though the IP is destroyed.

The experimental results demonstrate that our proposed embedding technique can indeed survive the tampering, synthesis, placement and routing.

3.2 Discussions

From the experimental results, the design does achieve the goal. Our proposed methods are low hardware cost. It is also easy to implement. Because the watermark generating circuit has been done on behavioral design level, the proposed embedding technique can survive the tampering, synthesis, placement and routing. The watermark is embedded into the test circuit, The generality of soil IPS will keep the test circuits afler integrating IPS into full SOCs. We can trace test signal and verify ownership rights afler integrating IPS into full SOCs. It’s also easy to detect the ownership rights of the IP provider after the chip have been packaged.

4.CONCLUSIONS

We have developed, for the first time, an intellectual propel?, (IP) core protection method that embeds watermark into test circuit. We establish principles for development of new watermarking- based IP protection procedures in this paper. On real designs, we show proofs of authorship with the watermark sequence. After the chip have been packaged, it’s still easy to detect the ownership rights of the IP provider. The experimental results show the proposed embedding technique can survive the tampering, synthesis, placement and routing. We don’t need to look at the photomicrograph if we want to check the ownership rights. This method is easier than conventional methods. This is a very convenient and feasible scheme.

5.ACKNOWLEDGMENT

The authors gratefully acknowledge NSC Chip Implementation Center (CIC), for supplying the technology models used in the circuit simulations. The authors wish to thank the anonymous reviewers for useful comments.

Table I Watermarking results

for

the

synthesis experiments. IP I p ~ l I p ~ 2 I p ~ 3 Ip-4 Ip-5

Table

E

Watermarking results

for

gates tampering

and

Watermark Case Original Circuit Headed W.S.M. Periodic W.S.M. Cyclic W.S.M. Random W.S.M. Operational W 3 . M Original Circuit Headed W.S.M. Periodic W.S.M. Cyclic W.S.M. Random W.S.M. Operational W.S.M Original Circuit Headed W.S.M. Periodic W.S.M. Cyclic W.S.M. Random W.S.M. Operational W X M Original Circuit Headed W.S.M. Periodic W.S.M. Cyclic W.S.M. Random W.S.M. Operational W.S.M Original Circuit Headed W.S.M. Periodic W.S.M. Cyclic W.S.M. Random W.S.M. Watermark IP Case

1

Operational W.S.N Gates P&R Analysis Tampering (5%) Tampenng(5%) Gate Count 15236 211 349 297 509 625 25965 207 355 302 515 640 32571 218 361 309 519 637 39870 221 352 308 524 626 43012 223 371 314 533 641 ncrease Gates ... 1.38 % 2.29 % 1.95 % 3.34 % 4.10%

...._

0.80 % 1.37 % 1.16% 1.98 % 2.46 % ... 0.67 Yo 1.10% 0.95 Yo 1.59 % 1.96% ... 1.55 % 0.88 % 0.76 % 1.31 % 1.57 Yo

...

0.52 % 0.86 % 0.73 % 1.23 % 1.49 %

Table

II

Watermarking results

for

synthesis,

placement

and

routine.

(Unit: number

of

bit error)

Area Timing Optimization Optimization IP

I

Watermarkcase

1

I

I

P&R

I

Headed W.S.M. Periodic W.S.M. Cyclic W.S.M. Random W.S.M. 0 0 0 Operational W.S.M. 0 I

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