Abstract— A new bandpass amplifier which performs both functions of low-noise amplifier (LNA) and bandpass filter (BPF) is proposed for the application of 900-MHz RF front-end in wire-less receivers. In the proposed amplifier, the positive-feedback Q-enhancement technique is used to overcome the gain low-Q characteristics of the CMOS tuned amplifier. The Miller-capacitance tuning scheme is used to compensate for the process variations of center frequency. Using the high-Q bandpass am-plifier in the receivers, the conventional bulky off-chip filter is not required. An experimental chip fabricated by 0.8-m N-well double-poly-double-metal CMOS technology occupies 2.62 2.0 mm2 chip area. Under a 3 V supply voltage, the measured quality factor is tunable between 2.2 and 44. When the quality factor is tuned atQ = 30, the measured center frequency of the amplifier is tunable between 869–893 MHz with power gain 17 dB, noise figure 6.0 dB, output 1 dB compression point at030 dBm, third-order input intercept point at014 dBm, and power dissipation 78 mW.
Index Terms— Bandpass amplifier, bandpass filter, CMOS technology, integrated inductor, low-noise amplifier, mobile communication, radio frequency, wireless receiver.
I. INTRODUCTION
I
N recent years, the rapid growth of mobile radio sys-tems has led to an increasing demand of low-cost high-performance communication IC’s. The operational frequency bands of the modern mobile systems such as advanced mobile phone service (AMPS) and Pan European Group special mobile (GSM) are 900 MHz, and 1.9 GHz for the personal communication network (PCN) and digital European cordless telephone (DECT) [1]. In such a high-frequency band, the complete systems often contain many IC’s and discrete ele-ments to obtain the maximum performance/cost ratio. Typical implementation of the systems uses silicon bipolar or BiCMOS IC’s as the RF/IF sections [2]–[7] and CMOS IC’s as the baseband section [8]–[10]. In order to obtain a small-size low-weight handheld system, a single-technology scheme is preferred for the maximum integration level. To realize this scheme, low-cost high-integration all-CMOS implementation is one of the most attractive solutions [11].The key factor to obtain an all-CMOS system is the avail-ability of high-performance CMOS RF components, which include low noise amplifiers (LNA’s), bandpass filters (BPF’s), mixers, voltage control oscillators (VCO’s), and power
ampli-Manuscript received March 29, 1996; revised July 30, 1996. This work was supported by the National Science Council (NSC), Taiwan, R.O.C., under Grant NSC-83-0416-E-009-016.
The authors are with the Integrated Circuits and Systems Laboratory, Institute of Electronics, National Chiao-Tung University, Taiwan 300, R.O.C.
Publisher Item Identifier S 0018-9200(97)01132-3.
fiers (PA’s). Recent progress in IC technology has brought the cut-off frequencies of CMOS devices beyond the GHz range, but implementing the GHz-range CMOS components is still a great challenge due to the existence of inherent limiting factors in CMOS technology. The limiting factors encountered in the CMOS RF design include:
• low device transconductance; • large device terminal capacitances;
• not available high-precision high-quality on-chip passive components;
• not available precise high-frequency CAD model. Recently, much effort has been devoted to the integration of RF components in CMOS technology. With the special tech-niques developed to overcome some of the limiting factors, the proposed CMOS LNA [12], [13], mixer [14], [15], synthesizer [16], and PA [17] have good high-frequency performance. However, the CMOS BPF has not been reported. Thus, the external passive filters such as ceramic filters or surface acoustic wave (SAW) filters are still required [18]. In order to obtain the maximum integration level, the BPF’s have to be on-chip integrated with other CMOS RF components.
In this paper, a new 900 MHz CMOS bandpass amplifier is proposed, which performs the functions of LNA and BPF simultaneously. As compared with the design of separate LNA and BPF, the proposed bandpass amplifier can retain the same features of low noise, high gain, and high . Moreover, it has the advantages of low cost, low power consumption due to the high integration level, and the reduction of extra matching elements between LNA and BPF.
The typical system requirements of RF front-end circuits in mobile systems are given in Section II. The design methodol-ogy of the proposed bandpass amplifier is given in Section III. In Section IV, design considerations and simulation techniques are presented. In Section V, experimental results are described. Finally, the conclusion is given in Section VI.
II. SYSTEM REQUIREMENTS
The RF front-end circuit is an important building block in the wireless receivers because it determines the RF sensitivity and intermodulation immunity of the overall receivers. A typical block diagram of the RF front-end circuit is shown in Fig. 1, which consists of a band filter, an LNA, an image filter (required in a dual-conversion receiver), and a downconversion mixer with the associated local oscillator (LO). The object of this design is a bandpass amplifier providing the functions of band filter and LNA, therefore, the specifications of band
filter and LNA must be met simultaneously. The essential features are center frequency, quality factor, power gain, noise figure, linearity, impedance matching, stability, and power consumption.
The major function of the band filter is to remove the out-of-band noise, which also contributes to the rejection of image signals. In the modern 900 MHz mobile systems, the signal bandwidth is 25 MHz (AMPS, GSM) or 35 MHz (E-GSM). Thus, a band filter of is required.
The power gain of the front-end pre-amplifier is an impor-tant parameter in the receivers. Its value should be high enough to reduce the noise contribution of the subsequent stages, but not so high to overdrive the subsequent mixer. The power gain is featured by (transducer power gain) of the amplifier. Its typical value is about 10–20 dB.
Both noise figure (NF) and third-order input intercept point (IIP ) are also important features. They determine the mini-mum detectable signal and the RF sensitivity of the receivers. For a GSM receiver, the GMSK modulation scheme requires the minimum signal-to-noise ratio of 12 dB when a 102 dBm signal is received [19], which is equivalent to the maximum NF of 7 dB in the front-end circuits. Assume the total NF of the stages subsequent to the bandpass amplifier is less than the gain of bandpass amplifier. Then the required NF of the bandpass amplifier is about 6 dB. However, the NF of the bandpass amplifier should be kept as low as possible to ease the NF requirements of other stages in the receiver.
The linearity of a receiver is characterized by the IIP because the intermodulation of two signals in the adjacent channels may appear in the desired channel to degrade the signal-to-noise ratio. For a better intermodulation rejection, the value of IIP should be as high as possible. Typical specification of the IIP is about 18 dBm [20]. Moreover, large-level signals may also occur at the input terminal of the receivers, thus the 1 dB compression point (P ) used to measure the power handling capability of the amplifier is also an important factor. The value of P should be as large as possible.
The impedance matching at input and output terminals are also important features. The matching characteristics are characterized by and , whose values should be as low as possible to avoid the use of external matching elements. In addition, the amplifier should also be a stable two-port network. Its stability factor used to measure the tendency of oscillation must be considered. Finally, the power dissipation of the circuits should be kept low to extend the available service time of the battery-operated portable systems.
(a)
(b)
Fig. 2. (a) Circuit diagram and (b) simplified small-signal equivalent circuit of the RF tuned amplifier.
III. DESIGN METHODOLOGY
A. RF Tuned Amplifier
The design of the bandpass amplifier is originated from the RF tuned amplifier shown in Fig. 2(a), which consists of a cascode stage driving an resonator and an output buffer driving a low-resistance load. Generally, the tuned amplifier is a popular structure for high-frequency amplifiers. In the RF tuned amplifier of Fig. 2(a), the resonator acts as a high-impedance load for the cascode stage at the resonant frequency. Thus, the circuit gain at resonant frequency can be boosted. A simplified small-signal equivalent circuit of the am-plifier is shown in Fig. 2(b), where is the transconductance of the MOSFET is the equivalent parallel inductance of the inductor is total capacitance at the node including the capacitor and the terminal capacitances of the MOSFET , and is the total conductance at the node including the output conductance of the cascode stage and the equivalent parallel conductance of the inductor . From Fig. 2(b), the voltage gain at the resonant frequency can be derived as
(1) where is the voltage gain of the buffer. As seen in (1), the key factor to obtain high circuit gain is to decrease the value of , or equivalently increase the value of the inductor .
Unlike the integrated inductors in the GaAs monolithic microwave integrated circuit (MMIC) technology with gold
Fig. 3. Measured inductance and quality factor versus frequency of a four-turn spiral inductor with optimum performance around 1 GHz.
metallization layer on thick dielectric substrate, the inductors in CMOS technology suffer from the resistive losses of met-allization layer and substrate resistance. Thus, the inductors’ quality factor and self-resonant frequency are limited [21], [22]. Investigations show that a four-turn square spiral inductor with 24- m line-width, 8- m line-space, and 314- m outer-dimension has the maximum quality factor around 1 GHz. The measured inductance and quality factor of this inductor are shown in Fig. 3. As may be seen from Fig. 3, the inductance and quality factor at 900 MHz are 3.7 nH and 2.9, respectively. This low-quality-factor inductor prevents the direct realization of CMOS tuned amplifier in Fig. 2(a).
The required power gain described in the previous section is 10–20 dB. Assume the design goal is dB. Then the required voltage gain is 10 dB in 50 systems. Since the driving capability of the CMOS buffer is limited and its loss is about 6 dB, the required is 16 dB 6.3. The value of depends on the resistive loading of the node . Because the output resistance of the cascode stage is often very high, the value of is dominated by the parallel con-ductance of the integrated inductor. The parallel concon-ductance of the optimized CMOS integrated inductor is about 1/78 at 900 MHz. Thus the required is 6.3
. Such a high transconductance requires a large ratio device operated at high dc current. Simulation
shows that an NMOSFET with operated
at mA is required. At V, the dc power dissipation would be 156 mW. Such a high power dissipation would prevent its applications in modern portable systems.
Since the intrinsic characteristics of CMOS devices can not easily be modified, improving techniques on integrated inductors must be developed to realize the RF tuned amplifier. Recently, large suspended inductors on silicon substrate have been proposed [12] which use an extra mask to etch substrate material under the inductors. The -enhancement techniques are also proposed to enhance the quality factors of the inte-grated inductors [23]–[25]. In this design, the -enhancement technique is employed.
Fig. 4. Circuit used to generate negative conductance.
B. -Enhancement Circuit
The basic principle of the -enhancement technique is to add a negative conductance to the resonator so that the inductor resistive losses can be compensated. With the negative conductance connected in parallel with the resonator, the total conductance in Fig. 2(b) becomes
(2) where is the parallel conductance of the inductor which is equal to 1/78 at 900 MHz in this design. As in (2), is decreased by the presence of negative conductance . As is decreased, the value of the circuit can be increased and the required circuit gain can be obtained with a lower value of .
The negative conductance can be generated from a positive feedback network. In this design, the negative conductance is generated by a source follower with a common-gate stage as the positive feedback element as depicted in Fig. 4. In Fig. 4, the transistor acts as the source follower whereas the transistor as the common-gate stage. The effective negative conductance of this combination can be derived as
(3) where the transconductances and of and , respectively, are determined by the bias current of the tran-sistor . Thus, the negative conductance can be tuned through the tuning of . Since is tunable, is also tunable. Thus, the circuit gain and quality factor become tunable.
C. Center-Frequency Tuning Circuit
Since the center frequency of the tuned amplifier is deter-mined by the integrated resonator which has inevitable variations in the IC fabrication process, the value of center frequency may suffer from a deviation from the desired one. A method to overcome this drawback is to post-tune the values of or after the chip has been fabricated. Thus, the variation of center frequency can be compensated through the post-tuning process.
In this design, a Miller-capacitance tuning scheme is used to post-tune the value. The scheme is illustrated in Fig. 5
Fig. 6. Circuit diagram of the voltage amplifier in the center-frequency control circuit.
where is the feedback capacitor of the voltage amplifier with the voltage gain . Due to the Miller effect, the effective capacitance at the input terminal of the voltage amplifier becomes . By tuning the value of , the effective capacitance can be tuned to compensate for the deviations of the center frequency.
In the design of the voltage amplifier, tuning range of should be large enough to obtain the desired tuning range of center frequency. In addition, the output impedance of the voltage amplifier should be kept low to minimize its resistive loading to other stages. The voltage amplifier in this design is shown in Fig. 6 where a resistor-load common-source stage is connected to a resistor-load source follower. The voltage gain of the amplifier is
(4) where is the gain of the source follower and and are the load resistance and transconductance of the common-source stage, respectively. The voltage gain can be tuned through the tuning of , which is accomplished by changing the source control voltage of the transistor . It is noted that both the source of and the resistor are connected to to realize the tuning and reduce the power dissipation.
IV. DESIGN CONSIDERATIONS A. Design Equations
The block diagram of the proposed bandpass amplifier is illustrated in Fig. 7 where the -enhancement circuit and center frequency control circuit are connected in parallel between tuned amplifier and output buffer. The corresponding
circuit diagram is shown in Fig. 8 where the circuits introduced in Section III are used. In Fig. 8, the bias transistors and are used to bias the tuned amplifier. The transconductance of and the output resistance of determine the input resistance of the circuit. Since , the contribution of to both input resistance and noise figure can be neglected. and are antenna termination resistance and dc blocking capacitor, respectively. The output buffer formed by two cascaded resistor-load source followers has a voltage gain of . The tuning of center frequency and quality factor are realized through the tuning of bias voltages and , respectively.
The center frequency , quality factor , input resistance , voltage gain at , and noise factor at can be derived under the first-order approximation as
(5)
(6)
(7) (8)
(9) where is the transconductance of the transistor , and is 4.1 nH at 900 MHz. Note that (5)–(9) give sufficient accuracy for hand calculation and can be used as the design guidelines to determine or adjust the parameters in the circuit simulations.
In the above design equations, consists of the tunable capacitance and the parasitic capacitance , and the terminal capacitance of the MOS devices. Thus
(10) Due to the strong dependence of on the parasitic capacitance , more precise simulation with the parasitic capacitances extracted from the circuit layout is necessary.
The advantage of incorporating the -enhancement circuit with the bandpass amplifier can be seen by evaluating the value
Fig. 8. Overall circuit diagram of the bandpass amplifier.
of from (5)–(8). At the center frequency of 900 MHz, the required value of is 7.62 pF from (5). Under the
specifications dB at and nH in
this design, the resultant is 1.43 10 in (6). Then
substituting , , ,
and into (8), the resultant is 1.8
10 . This value of is 4.4 times lower than that required in the amplifier without -enhancement circuit as calculated in Section III. Thus, high and high gain can be obtained with a lower value of . Although the -enhancement circuit consumes power too, the total power dissipation is still lower than that without -enhancement circuit.
B. Simulation Techniques
The circuit simulations based on the conventional device model have been found to have limited accuracy in the 900 MHz frequency band. In order to obtain more accurate simulation results, an extended wide-channel MOS model is employed [26] which replaces each large MOS device by ten smaller MOS devices connected by the gate polysilicon resistances of MOS devices. The major difference between channel model and conventional model is that the wide-channel model takes into account the effect of gate poly resis-tances of MOS devices, which produce considerable thermal noise and are important in the noise performance simulations. Thus, the noise simulations with the conventional model could lead to inflated results.
The simulation model of the inductor is based on an extended multisection equivalent circuit model developed by the authors [22], which has been proved to have high accuracy in modeling the high frequency behavior of the inductors on silicon substrate. In the whole circuit simulations, the parasitic capacitances extracted from the circuit layout are considered. To determine the component values and transistor dimensions of the circuit, many trade-offs among , and power dissipation should be encountered. Therefore, iterative tuning and simulation of each circuit component is necessary to obtain the optimal performance. After the optimization, the component values and device dimensions are summarized
TABLE I
COMPONENTVALUES ANDDEVICEDIMENSIONS OF THEBANDPASSAMPLIFIER
in Table I. From the simulation results, it is shown that the proposed bandpass amplifier has tunable center frequency between 933–966 MHz, 10 dB power gain, and 5.8 dB noise figure when tuned at .
C. -Tuning Limit
The -tuning limit encountered in this circuit is caused by the instability of the positive feedback network for negative conductance generation. As in (2), the total conductance is the sum of the negative conductance and the parallel conductance of the inductor. If is tuned to be equal to is zero and is infinite as in (6). Thus, the amplifier starts to enter the unstable region. If , the value of becomes negative and the transfer function of the amplifier has right-half-plane (RHP) poles and expressed as
(11) In this case, the amplifier is unstable.
Fig. 9. The microphotograph of the fabricated bandpass amplifier.
Since the values of and are frequency dependent, so is . When the amplifier is tuned to the high condition, at the center frequency . Under this condition, the amplifier is stable at . But at some
frequency around could occur
and the total conductance becomes negative. In this case, the input impedance of the amplifier is also negative and is higher than 0 dB. Since a stable circuit requires both and below 0 dB at all frequencies, the maximum stable quality factor of the amplifier is the value of when dB occurs. Note that the high-frequency spurious signals in the circuit may have positive feedback and become unstable. This may further degrade the maximum stable quality factor.
D. Layout Consideration
The chip layout plays an important role in the high-frequency circuits design. The unsuitable circuit layout may drastically degrade the circuit performance due to the increasing induced or coupled noise. To obtain the desired performance, the following guidelines are followed in the layout design.
• All active devices are surrounded by grounded p guard rings to minimize the substrate noise and reduce the coupling among the devices.
• All interconnections are made by metal layer to minimize parasitic resistance.
• All MOS devices have minimum gate length of 0.8 m to reduce the terminal capacitances.
• Ground connections are carefully routed to prevent the ground loop.
Furthermore, in order to reduce inductive parasitics of the power lines, all voltage bias or power supply nodes are connected with large on-chip bypass capacitors which are made by connecting many unit interpoly capacitors in parallel to reduce terminal series resistances. Since the capacitors may occupy large chip area, the value of each bypass capacitor is optimized through simulations to obtain the maximum performance/area ratio. The bypass capacitances at the nodes
(a)
(b)
Fig. 10. The measured (a) S21 magnitude and (b) S11 magnitude of the fabricated amplifier tuned at differentQ values.
, and the gate bias of are 796, 46.4, 29, and 69.6 pF, respectively.
V. EXPERIMENTAL RESULTS
The bandpass amplifier was fabricated by 0.8- m N-well double-poly-double-metal CMOS technology. The resistors – in the circuit are implemented by poly resistors. The microphotograph of the experimental chip is shown in Fig. 9. The measurements were performed by wafer probing systems with on-chip calibration technique. The nominal supply volt-age of the fabricated amplifier is 3 V. As the supply voltvolt-age is below 3 V, both circuit gain and linearity are degraded.
The measured and of the fabricated amplifier tuned at different values are given in Fig. 10(a) and (b), respectively. In these measurements, the center frequency control circuit is disabled and the -enhancement circuit is tuned by increasing the -tuning bias voltage from 0.7–1.08 V. When V, the -enhancement circuit is disabled and the inherent is 2.2, which is lower than the value (2.9) of the integrated inductor because of the resistive parasitics in the circuit. As increases, both quality factor and amplifier gain are increased due to the increased positive feedback. However, the peak of is also increased at the same time. In Fig. 10(b), the peak crosses 0 dB
Fig. 11. The measuredQ and Q-tuning sensitivity 1Q=1VQ(mV) versus tuning voltageVQof the fabricated bandpass amplifier.
when the quality factor is 44 with V. This means the circuit is unstable if and the maximum stable is 44.
A plot of the measured and -tuning sensitivity (mV) versus is shown in Fig. 11. As seen in Fig. 11, is more sensitive to the variation of when the is tuned higher. In the measurement of , the required accuracy of is 10 mV. Both threshold voltage and resistance variations in the circuit affect the accuracy of tuning voltage. The measurement results have shown that, under a fixed tuning voltage V, the variation of among 40% chips is 15%. The chip-to-chip variations can be reduced by proper layout technique. Moreover, both -tuning sensitivity and variations can be reduced by using the current tuning through a current mirror to adjust the voltage .
Since the bandpass filtering function of the proposed am-plifier has second-order characteristics, the out-of-passband attenuation is not so high as that in high-order filters. As can be seen from Fig. 10(a), the amplifier gain at the frequencies smaller than 800 MHz or greater than 1 GHz is below 0 dB, and it changes slightly as is varied. Thus, when the bandpass amplifier is applied to a dual-conversion receiver with 70–100 MHz IF, the image filter is still required.
As is tuned from 2.2–30, the peak gain increases from 3.4 to 17 dB, the center frequency decreases from 951 MHz to 893 MHz, and the total dc current increases from 13.9 to 24.1 mA. Because the amplifier characteristics strongly depend on , the following measurement results are obtained with fixed at 30. In some cases, the measured results with tuned at ten are also given for comparison.
The measured noise figures of the fabricated amplifier with and are shown in Fig. 12. As seen from Fig. 12, NF is about 6.0 dB around the center frequency. As decreases, NF increases. This is because the decreased leads to the decreased amplifier gain. Thus, the noise
Fig. 12. The measured noise figures of the fabricated amplifier tuned at Q = 30 and Q = 10.
Fig. 13. The measured frequency response of the fabricated amplifier tuned at maximum and minimum center frequencies with the sameQ of 30.
contributed by the devices after the gain stage is increased and NF is increased. Comparing the measured NF (6.1 dB) to the simulated value (5.8 dB) under the same gain of 10 dB, the deviation is 4.8%.
The center-frequency tuning range of the fabricated am-plifier is illustrated in Fig. 13 where the measured at maximum and minimum with the same of 30 are given. As seen from Fig. 13, the tunable range is 24 MHz from 869–893 MHz. If is decreased to ten, can be increased to 905 MHz and the tunable range of remains almost the same. Comparing the measured maximum frequency (893 MHz) to the simulated value (966 MHz) at , the deviation is 8.2%. Note that the tuning of is dependent upon that of . Therefore, iterative tunings of and are required to obtain a specified set of and .
(a)
(b)
Fig. 14. The measured POUT and PIM3 versus Pin of the fabricated amplifier tuned at (a)Q = 30 and (b) Q = 10.
The linearity measurement results of the circuit tuned at and are given in Fig. 14(a) and (b), respec-tively. These plots are obtained by applying two sinusoidal signals of equal power and different frequencies and to the amplifier and measuring the output power spectra at frequencies and at versus input power . In the measurement of (10), the two-tone frequencies and are 893 (905) MHz and 897 (909) MHz, respectively, and the third-order intermodulation frequency
is 901 (913) MHz. Note that all the frequencies and fall in the passband of the amplifier. In Fig. 14(a) and (b), the corresponding 1 dB compression points and third-order intercept points IP are indicated. As can be seen from the figures, the measured output 1 dB compression point
(a)
(b)
Fig. 15. The measured (a)S11andS22and (b)K and j1j of the fabricated amplifier tuned atQ = 30.
and third-order input intercept point IIP at
(10) are 30 ( 23) dBm and 14 ( 12) dBm, respectively. The linearity is degraded with the increased because of the increased positive feedback.
The dynamic range of the circuit is measured by the input 1 dB compression point ( ). In Fig. 14(a) and (b), the
values of at and are 47 and
31 dBm, respectively. The dynamic range of the active -enhancement circuit is limited by the inherent of the circuit [24], which is 2.2 as in Fig. 10(a). Higher dynamic range can be obtained by increasing the inherent , which can be done by using a high- inductor or reducing the resistive loading of the circuit. In most cases, the of integrated inductors cannot be increased without modifying the fabrication process. Thus, the only way to improve the dynamic range is to reduce the resistive loading. In the circuit of Fig. 8, reducing the value of decreases the resistive loading. However, the tuning range of is also decreased. Thus, one should trade off between dynamic range and tuning range of . In this case, dBm is obtained with the tuning range of 24 MHz.
The measured matching characteristics and and stability factor and of the circuit tuned at
are given in Fig. 15(a) and (b), respectively. As seen in Fig. 15(a), is below 13 dB at all frequencies. This means the output impedance is well matched to 50 . As
is tuned, is only slightly changed due to the good output isolation offered by the double-buffer output stage. On the other hand, the input terminal is not well matched due to the trade-off between and NF. As in (7), good input matching requires the transconductance . This value of would produce considerable noise and degrade the overall noise figure as in (9). In order to keep the NF within the specification, the value of is set to a lower value to reduce the noise effect. Therefore, the external input matching circuit is required to obtain the minimum input return loss. An network contains a series inductor of 11 nH and a parallel capacitor of 6 pF at the source end can be used as the external matching circuit to match the input impedance. The simulation results have shown that with the input matching circuit, is lower than 12 dB in the passband. The other parameters such as , gain, and NF change slightly after adding the matching network because the response of the amplifier is mainly determined by the internal circuit and the lossless elements do not contribute thermal noise. As shown in Fig. 15(b), the required conditions for an unconditional stable system, and , are met in this design. The measurement results of the fabricated CMOS bandpass amplifier are summarized in Table II.
VI. CONCLUSION
A bandpass amplifier has been successfully designed and fabricated by using 0.8- m CMOS technology. Incorporating both -enhancement circuit and center-frequency control cir-cuit with the tuned bandpass amplifier, the limiting factors in CMOS RF design can be overcome and the amplifier perfor-mance can be improved. In performing high-frequency circuit simulation for the proposed amplifier, wide-channel MOS model and multisection inductor model are used to minimize the simulation errors. The performance of the experimental chip has been verified, which can meet the requirement of 900 MHz wireless receivers. Thus, the proposed bandpass amplifier can perform the functions of LNA and band filter in conventional 900 MHz front-end circuits. Moreover, it is quite feasible to use the amplifier in the high-integration all-CMOS receivers.
In the future, high-order bandpass amplifier design and the integration of other RF components in CMOS will be conducted.
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ics Engineering, National Chiao-Tung University, Hsinchu, Taiwan, in 1976 and 1980, respectively.
From 1980 to 1984, he was an Associate Profes-sor in the National Chiao-Tung University. During 1984 to 1986, he was a Visiting Associate Professor in the Department of Electrical Engineering, Port-land State University, OR. Since 1987, he has been a Professor in the National Chiao-Tung University, Hsinchu, Taiwan. From 1991 to 1995, he was rotated to serve as Director of the Division of Engineering and Applied Science in the National Science Council. He has published more than 69 journal papers and 94 conference papers on several topics, including digital integrated circuits, analog integrated circuits, computer-aided design, neural networks, ESD protection circuits, special semiconductor devices, and process technologies. He also has 17 patents including nine U.S. patents. His current research interests focus on low-voltage low-power mixed-mode integrated circuit design, hardware implementation of visual and auditory neural systems, and RF integrated circuit design.
Dr. Wu is a member of Eta Kappa Nu and Phi Tau Phi. He was awarded the Outstanding Research Award by the National Science Council in 1989 and 1995 and the Outstanding Engineering Professor by the Chinese Engineer Association in 1996. Currently, he is the Centennial Honorary Chair Professor at the National Chiao-Tung University.
