IEEE ELECTRON DEVICE LETTERS, VOL. 26, NO. 10, OCTOBER 2005 761
Electron Mobility Enhancement Using Ultrathin
Pure Ge on Si Substrate
Chia Ching Yeo, Byung Jin Cho, Senior Member, IEEE, F. Gao, S. J. Lee, Member, IEEE, M. H. Lee, C.-Y. Yu,
C. W. Liu, L. J. Tang, and T. W. Lee
Abstract—We demonstrate enhancement of electron mobility in nMOSFET using an ultrathin pure Ge crystal channel layer di-rectly grown on a bulk Si wafer. A thin Si crystal layer is also grown on top of a Ge crystal channel layer as a capping layer. Using the Si/Ge/Si structure, a maximum 2.2X enhancement in electron mo-bility is achieved while good gate dielectric properties and junction qualities of bulk Si devices are maintained.
Index Terms—Effective electron mobility, Ge, high- gate di-electric.
I. INTRODUCTION
R
EPLACEMENT of SiO with high- gate dielectrics has highlighted new challenges such as channel mobility degradation [1], [2]. Recently, MOSFET on Ge substrate is extensively investigated as it can offer two times and four times higher electron and hole mobilities, respectively [3]. However, integration of bulk Ge into CMOS processes has encountered several critical problems, such as poor mechanical properties and limited supply of raw material. Unlike Si, the low thermal stability of Ge and water-solubility of GeO has hindered the realization of good interfacial quality with gate dielectric [4], [5]. In addition, smaller bandgap of Ge has resulted in high source/drain junction leakage current [4], [6]. In this letter, we propose and demonstrate a simple device structure to exploit the advantage of high carrier mobility of Ge channel, while utilizing other excellent properties of Si substrate, such as good mechanical properties, excellent integrity with gate dielectric and good on-off ratio of junction current.II. DEVICESTRUCTURE
Due to 4% lattice constant mismatch and surface energy dif-ference between Ge and Si, formation of islands and three-di-mensional clusters have been observed if Ge is grown directly on Si [7]. Nevertheless, growth of continuous and defect free crystal Ge layer on Si crystal is indeed still possible if the Ge
Manuscript received July 8, 2005. The review of this letter was arranged by Editor B. Yu.
C. C. Yeo, B. J. Cho, F. Gao, and S. J. Lee are with the Silicon Nano Device Laboratory, Department of Electrical and Computer Engineering, National University of Singapore, Singapore 119260, Singapore (e-mail: [email protected]).
M. H. Lee, C.-Y. Yu, and C. W. Liu are with the Electronics Research and Ser-vice Organization, Industrial Technology Research Institute, Chutung, Hsinchu 310, Taiwan, R.O.C.
L. J. Tang is with the Institute of Microelectronics (IME), Singapore 117685, Singapore.
T. W. Lee is with the Jusung Engineering Company, Ltd., Kyunggi–Do 464-892, Korea.
Digital Object Identifier 10.1109/LED.2005.855420
Fig. 1. (a) Schematic diagram of Si/Ge/Si (SGS) MOSFET. Majority part of the S/D is in the Si substrate and a thin Ge layer lies at the channel region. (b) XTEM image of 3.4 nm of Ge epitaxially grown on Si substrate, with a thin Si capping layer of 2.3 nm.
layer grown is thinner than critical thickness, a thickness in which dislocations or islands starts to form when strain is re-laxed. It is reported that the critical thickness of Ge on Si is below 10 nm, depending on the process conditions [8], [9]. Quantum mechanical behavior of the inversion electrons has shown that the electron concentration peaks at a distance of 1 to 2 nm from the gate dielectric/Si interface, with the whole inversion layer depth extends to several nm into the substrate, depending on the surface electric field. For the exploitation of advantage of high channel mobility, therefore, it is not neces-sary for high mobility channel to be thick. Considering such, we propose to use an ultrathin crystal Ge layer directly on Si substrate, with its thickness thinner than critical thickness. On top of this Ge layer, we grow an additional ultrathin Si epi layer. MOSFETs are then fabricated on this Si/Ge/Si (SGS) substrate, as shown in Fig. 1(a). In such transistor, carrier transport can occur in the Ge layer while majority part of source/drain junc-tion is still in Si substrate. The electron populajunc-tion distribujunc-tion will mainly reside in the Ge layer when the Si capping layer is very thin ( nm). Gate dielectric is formed on top of silicon surface. Therefore, we can achieve high channel mobility of Ge devices while maintaining other properties of Si devices.
III. DEVICEFABRICATION
A Si buffer layer of 44 nm was epitaxially grown at 525 C on a p-type Si (100) substrate (15–25 cm) by UHV/CVD method, using SiH as precursor. A pseudomorphic Ge layer was then epitaxially grown with GeH precursor, followed by growth of a thin Si capping layer. Fig. 1(b) shows the cross-sectional transmission electron microscope (TEM) image of as-deposited Si/Ge/Si (SGS) layers, with thickness of Ge and Si capping layer of 3.4 and 2.3 nm, respectively. From the cross-sectional TEM
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762 IEEE ELECTRON DEVICE LETTERS, VOL. 26, NO. 10, OCTOBER 2005
image, no dislocations and defects are observed at the Ge/Si in-terfaces. The root mean square of surface roughness is 0.516 nm as measured by atomic force microscopy, indicating no sign of Ge island formation on top of Si substrate. For the MOSFET fabrication, Si capping layer thickness was further reduced just before gate dielectric deposition by repeating wet chemical ox-idation and stripping process using SC1 (NH OH:H O : DIW) and diluted HF at room temperature. Three different final Si cap-ping layer thicknesses of 2.3 nm, 1.5 nm, and 0.7 nm were pre-pared. HfAlO was deposited as gate dielectric at 450 C, fol-lowed by a post deposition annealing at 500 C for 60 s in a N ambient. TaN was used as gate electrode. For source/drain (S/D) formation, a method of amorphization and solid-phase epitaxy (SPE) re-growth at a low temperature was employed. Arsenic ions were implanted with a dose of cm at 32 keV and then annealed using furnace at 550 C for 10 min in a N ambient for SPE regrowth. Finally, Al metallization process for contact and forming gas annealing were implemented.
IV. RESULTS ANDDISCUSSION
Fig. 2 shows the capacitance–voltage (C–V) characteristic of SGS nMOSFET with Si capping layer thickness of 2.3 nm. Unlike the C–V curve of Ge MOS capacitors [5], no apparent generated is observed in SGS MOS capacitors. A small plateau was observed during weak accumulation (
V), attributed to holes confinement in the Si/Ge/Si heterostruc-ture, as depicted in the inset of Fig. 2. The holes confinement in this potential well effectively increases the equivalent oxide thickness (EOT) during weak accumulation. Accumulated holes only occur at the Si capping/HfAlO interface during strong ac-cumulation ( V). When the Si capping thickness is thinner, this effect becomes less prominent. Whereas during in-version , electron will populate the HfAlO/Si capping interface.
Fig. 3(a) shows the leakage current density versus EOT,
both for SGS and bulk Si nMOSFETs. The SGS nMOSFET has shown comparable leakage current to those of other high-on bulk Si devices obtained by other research groups [10], [11]. Fig. 3(b) shows the n S/D junction properties of the SGS nMOSFET as compared to junction properties of bulk Si nMOSFET and bulk Ge nMOSFET [4]. Bulk Si nMOSFET implanted with arsenic with a dose of cm at 100 keV and activated by rapid thermal anneal (RTA) at 900 C for 30 sec is included for comparison. As majority of the S/D area is in the Si substrate, the reversed leakage current for the SGS MOSFET is about three orders of magnitude lower than reported data for n S/D of Ge substrate at reversed bias of V [4]. However, the reversed leakage current of SGS nMOSFET is more than one order of magnitude higher at V, compared to bulk Si nMOSFET with high temperature RTA, which requires further optimization of S/D activation process for SGS devices.
Fig. 4(a)–(c) shows the – characteristics of SGS nMOSFET for different Si capping thickness, compared with Si nMOSFET. The SGS nMOSFET shows distinct en-hancement of 19.4%, 35.7%, and 47.5% compared to bulk Si nMOSFET, for the Si capping layer thickness of 2.3 to
Fig. 2. C–V characteristics of TaN/HfAlO for SGS MOSFET with Si capping
layer thickness of 2.3 nm. Inset shows the band diagram for SGS substrate, with Si capping layer of 2.3 nm, indicating confined holes in the Ge valence well, resulting in thicker EOT during weak accumulation.
Fig. 3. (a) Gate dielectric leakage current (J at V –V = 01 V) versus EOT, showing HfAlO on SGS nMOSFET has comparable leakage current with that on bulk Si MOSFET in this letter and other reported high-K on bulk Si [10], [11]. (b) S/D junction properties of SGS, bulk Si, and bulk Ge MOSFET [4].
1.5 and 0.7 nm, respectively. The electron mobility in SGS nMOSFET, indicated in Fig. 4(d), measured using split C–V method, also shows significant enhancement of 1.4, 1.8, and 2.2 times in peak mobility for the different Si capping layer thicknesses, respectively. The mobility enhancement depends both on the electron population distribution across the SGS structure during inversion and its straining behavior. When the electrons reside mainly in the Ge layer, as for the case of 0.7 nm of Si capping layer SGS nMOSFET, the channel mobility
YEO et al.: ELECTRON MOBILITY ENHANCEMENT USING ULTRATHIN PURE Ge 763
Fig. 4. I –V characteristics for SGS MOSFET with Si capping layer thickness of (a) 2.3, (b) 1.5, and (c) 0.7 nm. W/L of the MOSFET= 320/8 m. Each curve is forV –V of 00:2 to 1.2 V, in increments of 0.2 V. (d) The effective mobility versus vertical effective field for SGS and bulk Si MOSFET with HfAlO gate dielectric. (e)I –V characteristics for SGS nMOSFET, as compared with Si nMOSFET.
is greatly enhanced, compared to bulk Si nMOSFET. It is well known that the electron mobility in bulk Ge is two times of that of bulk Si. In this letter, 2.2 times enhancement in electron mobility is demonstrated. The additional enhancement may be attributed to strain in the channel layer, which will be further explored later.
Fig. 4(e) compares the – characteristics of SGS and Si nMOSFETs. The subthreshold swing for SGS nMOSFET with Si capping thickness of 2.3 and 1.5 nm is approximately 95 mVdec . This is relatively comparable to that of Si nMOSFET fabricated simultaneously, indicating no interface states density degradation. However, the subthreshold swing is slightly de-graded to 110 mVdec when Si capping layer is 0.7 nm, prob-ably due to diffusion of Ge through the ultrathin Si to the dielec-tric/Si interface.
V. CONCLUSION
In this letter, we have demonstrated SGS nMOSFET with high- gate dielectric, showing a maximum mobility enhance-ment of 2.2 times than bulk Si nMOSFET. Although further optimizations on thickness combination and thermal processes need to be done, the SGS MOSFET shows a good feasibility as a new way for carrier mobility enhancement, with minimal modification to current CMOS process flow.
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