用於管線式類比數位轉換器之數位背景校正技術

全文

(1)»ñø;. é

(2) .é@~X }ÿ¡Z ES. A. àyÑaPvfó»ð óeÿlÑ* 1896 Digital Background Calibration of Pipelined ADCs. @~ß : oM¡ ¼0>0 : Ò+/ ºÓ»ÜèâOÚ`.

(3) àyÑaPvfó»ð óeÿlÑ* Digital Background Calibration of Pipelined ADCs. ES. A. @~ß : oM¡ Student : Jen-Lin Fan ¼0>0 : Ò+/ Advisor : Jieh-Tsorng Wu »ñø;. é^.o é

(4) . é@~X }ÿ¡Z 1896 A Dissertation Submitted to Department of Electronics Engineering & Institute of Electronics College of Electrical and Computer Engineering National Chiao-Tung University in partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy in Electronics Engineering July 2009 Hsin-Chu, Taiwan, Republic of China. ºÓ»ÜèâOÚ`.

(5) àyÑaPvfó»ð óeÿlÑ* .ß : oM¡. »ñø;. é

(6) . é@~X ` ES. A. é^.o. ¼0>0 : Ò+/. 1896. ½ %Ý M MOS éþÝ;¼÷¼÷yéþÝØß[T ô.h 9ø|è>ÍE®>|C;6£¬Î. ;¼Ý¹yô¸ÿéþÝí (ª±¨². ÷¼÷ßÝ oxide R Ý-Ýê

(7) ®éDô ìª. í (

(8) ®éDÝ ª±¸ÿvfé'p|ÿÕ{¦Ç|CVPÝO9°.ôK¸ ÿvfé'Ýp÷¼÷{¯vféÝ[«Û&Ý éDPÝ6ðéÑaPvfó»ð êGÂ½Ý¸à. Í3º®` Þ×Í{¦ÇÝºÕw E®3]0ÝÏV¸ÿÍ»ð©P|¾Õ{a P|C{ã@ÝO¬Î. Ýé<gTïÎb§¦ÇÝºÕw º3vfó»ð ÝíCW&aPÝ´Ë|êG CMOS Ý%*é Ý<g|¯vfó»ð ¾Õ 10-12Bit ¼Ý¬Î %Q¸ÿ '×Í{¦Çw Ýpÿ8 Ý{É¸¾Õ¦ÇÝ'O¬Î Q??º ºÕw ÝE®>X|A¢¿à×Í{>±¦ÇÝºÕw i.

(9) '×Í{[Ývfó»ð ÎÍS¡ZÝ¥F ÍS¡Zà×ÍTàyÑaPvfó»ð úeÿlÑ*Ey× Í6ðéPÝÑaPvfó»ð &Æ|6vÝíáãøé¬v ÞBó¿à6vÝéáxÝGríáÝBó|¿àvf ó»ð Ýí|³ã¼Ah-|Å(Õvfó»ð ÝÑð

(10) ®¾ÕlÑÝêÝ¿àóá8nÝBó®ßµ|¸ÿvfó»ð Ý

(11) ®mÜ²ÝíY». A. &Æ@¨Ý×Í 65 {[éþ%Ý 12-Bit 80 MHz 32mW ÑaPvfó»ð ¸¿à±ÝeÿlÑ*Þvfó»ð XCW Ý&aP|lÑÍtÝÞ¦Ç|Cgóvf»ð |lÑ²?. ×MÞºÕw &aP¦ÇXCW&aP´Ë|ÑÑ&ÆXèÝ* ÎúvºåÕ-<gÝÅ(¨²ômÜ²ÝíY». & ES Æ3DvféXmÝã@aPOX||¿àf´¬v6é Ý]P¼@¨vfé&Æ@¨Ývfó»ð 3íá 2 MHz Ý<®¬ v

(12) ®3 80MS/s `|¾Õ 67 dB Ý SNDR 81 dB Ý SFDR 1896. ¨²&Æè×Í6v;¼Ývfó»ð Úx¼3KlÑXmÝ` 9Í6v;¼vfó»ð ãËÍ×øÝvfó»ð XàW¸Æ #[8!ÝíáGr¬Î¿à!ÝBó¼ lÑ&Æ3lÑ£]³ ãGÞËÍvfó»ð Ýí|f´¬vÞÓG|tAh-| »ª±XmÝlÑ` 3hS¡Z&ÆÞXèÝÚx¿à§¡5 Ùÿa|J. ii.

(13) Digital Background Calibration of Pipelined ADCs Student : Jen-Lin Fan. Advisor : Jieh-Tsorng Wu. Department of Electronics Engineering and Institute of Electronics A. National Chiao-Tung University ES Abstract 1896 Following the progress of advanced technology, the channel length of MOS transistor is smaller and the parasitic is also reduced. These characteristics make the transistor be able to be operated in higher frequency and lower power dissipation. However, the output impedance of MOS transistor reduces with the channel length. In addition to the output impedance, the thickness of gate oxide also becomes thinner than a long channel device. For device reliability issue, supply voltage scales down with channel length. The reduced output impedance and supply voltage make analog circuits can not be designed with high gain and large dynamic range. These features make the design of high performance analog circuits more difficult. Voltage-mode switched-capacitor (SC) pipelined ADC is widely used. This circuit is operated with high gain operation amp (opamp) and configures in negative feedback. The negative feedback circuit can achieve high linearity and high accuracy at the same time. iii.

(14) However, with capacitor mismatch and finite opamp’s dc gain, the output of a pipelined ADC may contain servere nonlinearity. The capacitor matching with present CMOS technology can be used to design a pipelined ADC with 10-12 bit resolution. But it’s hard to design a high gain opamp with high unit-gain frequency in deep-submicron technology. The main purpose of this thesis is to design a high performance pipelined ADC in deepsubmicron technology. This thesis presents a background calibration scheme for pipelined analog-to-digital converters (ADCs) that is robust. For a SC pipeline stage, by splitting its input sampling capacitor, a random sequence can be injected into the ADC’s signal path, and then calibration data can be extracted from the ADC’s digital output without interrupting its normal conversion operation. Using an input-dependent scheme to generate the calibration ransignal.. ES. A. dom sequence, no additional signal range is required to accommodate the extra calibration. A 32-mW 12-bit 80-MS/s pipelined ADC was fabricated using a 65 nm CMOS tech1896 background technique, which corrects nology. The ADC demonstrates a new digital. pipeline stage nonlinearity as well as gain and sub-DAC errors. The proposed technique is robust and immune to device mismatches, and does not need extra signal range. Since the accuracy and linearity requirements are mitigated, analog circuits with less complexity and power can be used. The ADC achieves 67 dB SNDR and 81 dB SFDR at 80 MS/s sampling rate with a 2 MHz sinewave input. In addition, a split-channel ADC architecture is proposed to reduce the calibration time. The split-channel ADC consists of two A/D channels that receive the same analog input but employ different random sequences for calibration. The calibration time can be greatly reduced by comparing the digital outputs from both channels and then removing the embedded perturbations before extracting the calibration data. The proposed calibration techniques are analyzed by using both theoretical formulation and system-level simulation.. iv.

(15) Acknowledgements. A. ´&E&Ý¼0>0>Ò+/>0lîtÝÝ ¯ 3&} ÿ° Íì2&¼0ÜÃ|C@~§FîÝ£[9°Å(K¸& åÇ9¬vÕßp #½& @Ý.!.Æ39¿O &&9Ý¼0nï3vféÙ@ÝÚOY &9. !.Ýï)3hlî05Ý ¨² ¬éì's"

(16) Ý ÜÃ¯&È5¿WþnÝ%® 3O.ÄßÀÎ&Ýt·ÞßY ES Ö3h=T2 Æ t¡GÞ&Ý¡Z¤&tÝÝlÒ 1896. J EN -L IN F AN National Chiao-Tung University 2009, July. v.

(17) A. ES. 1896. vi.

(18) Contents Z`. i. English Abstract. iii v ES. List of Tables. A. Acknowledgements. List of Figures 1. 2. xi xiii. 1896. Introduction. 1. 1.1. Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1. 1.2. Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5. Overview of Pipelined ADC. 7. 2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7. 2.2. Quantization Feedforward Architecture . . . . . . . . . . . . . . . . . .. 7. 2.3. A 2.5-bit Pipeline Stage . . . . . . . . . . . . . . . . . . . . . . . . . . .. 14. 2.4. Opamp Gain and Capacitor Matching . . . . . . . . . . . . . . . . . . .. 17. 2.5. Opamp Speed Requirement . . . . . . . . . . . . . . . . . . . . . . . . .. 19. 2.6. Thermal Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 20. 2.6.1. Sampling Thermal Noise . . . . . . . . . . . . . . . . . . . . . .. 20. 2.6.2. Thermal Noise of Opamp . . . . . . . . . . . . . . . . . . . . . .. 22. 2.6.3. Thermal Noise of Rs . . . . . . . . . . . . . . . . . . . . . . . .. 23. 2.6.4. Thermal Noise of Rf . . . . . . . . . . . . . . . . . . . . . . . .. 24. vii.

(19) 2.6.5 2.7. 4. 25. Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 27. Gain/DAC Calibration. 29. 3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 29. 3.2. Gain and DAC Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 29. 3.3. Digital Foreground Calibration . . . . . . . . . . . . . . . . . . . . . . .. 33. 3.4. Correlation-Based Technique . . . . . . . . . . . . . . . . . . . . . . . .. 36. 3.5. Prior Arts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 38. 3.5.1. Randomization of sub-ADC and sub-DAC . . . . . . . . . . . . .. 39. 3.5.2. Capacitor-Swapping Technique . . . . . . . . . . . . . . . . . .. 41. 3.5.3. Calibration with Reference ADC . . . . . . . . . . . . . . . . . .. 42. 3.5.4. Split-Capacitor Technique . . . . . . . . . . . . . . . . . . . . .. 43. 3.6. Proposed Split-Capacitor Configuration . . . . . . . . . . . . . . . . . .. 46. 3.7. Principle of Gain/DAC Calibration . . . . . . . . . . . . . . . . . . . . .. 50. 3.8. Input-dependent q Generation . . . . . . . . . . . . . . . . . . . . . . .. 52. 3.9. Correlation-Based Calibration Data1896 Extraction . . . . . . . . . . . . . . .. 53. 3.10 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 56. Stage Nonlinearity Calibration. 57. 4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 57. 4.2. Nonlinearity Modeling and Correction . . . . . . . . . . . . . . . . . . .. 59. 4.3. Prior Arts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 60. 4.3.1. Statistic-based Distance Estimation . . . . . . . . . . . . . . . .. 60. 4.3.2. Harmonic Distortion Correction . . . . . . . . . . . . . . . . . .. 62. 4.4. Definition of Linear System . . . . . . . . . . . . . . . . . . . . . . . . .. 63. 4.5. Split-Capacitor SC Stage with Dual q . . . . . . . . . . . . . . . . . . .. 64. 4.6. Calibration Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .. 67. 4.7. Harmonic Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 68. 4.8. Harmonic Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 70. 4.9. Multiple Harmonics Calibration . . . . . . . . . . . . . . . . . . . . . .. 72. 4.10 Calibration under z-ADC Offset . . . . . . . . . . . . . . . . . . . . . .. 74. ES. viii. A. 3. Total Noise of Pipelined ADC . . . . . . . . . . . . . . . . . . ..

(20) 6. 76. 4.12 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 77. A 12-Bit 80 MS/s Pipelined ADC. 79. 5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 79. 5.2. Pipelined ADC Architecture . . . . . . . . . . . . . . . . . . . . . . . .. 79. 5.3. Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . .. 83. 5.3.1. Bootstrapped Switch . . . . . . . . . . . . . . . . . . . . . . . .. 83. 5.3.2. Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . .. 83. 5.3.3. Switched-Capacitor Comparator . . . . . . . . . . . . . . . . . .. 87. 5.4. Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 87. 5.5. Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 96. Split-Channel ADC. ES. A. 5. 4.11 Cs Partition Consideration . . . . . . . . . . . . . . . . . . . . . . . . .. 99. 6.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6.2. Prior Arts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100. 6.3. 99. 1896. 6.2.1. Two-Channel ADCs . . . . . . . . . . . . . . . . . . . . . . . . 100. 6.2.2. Split-ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101. 6.2.3. Prediction Using a FIR Filter . . . . . . . . . . . . . . . . . . . . 102. Split-Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . 103 6.3.1. Split-Channel ADC Architecture . . . . . . . . . . . . . . . . . . 104. 6.3.2. ADC Output Encoding . . . . . . . . . . . . . . . . . . . . . . . 105. 6.3.3. Calibration Principle . . . . . . . . . . . . . . . . . . . . . . . . 107. 6.3.4. Calibration Noise Reduction . . . . . . . . . . . . . . . . . . . . 108. 6.4. Offset Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109. 6.5. Gain Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110. 6.6. Correlation Data Extraction . . . . . . . . . . . . . . . . . . . . . . . . . 111. 6.7. ADC Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112. 6.8. A 15-Bit ADC Design Example . . . . . . . . . . . . . . . . . . . . . . 113. 6.9. Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 ix.

(21) 7. Conclusions and Future Works. 119. 7.1. Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119. 7.2. Recommendations for Future Investigation . . . . . . . . . . . . . . . . . 120 121. Vita. 127. Publication List. 128. ES. A. Bibliography. 1896. x.

(22) List of Tables Opamp Performance Summary . . . . . . . . . . . . . . . . . . . . . . .. 85. 5.2. Performance Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .. 90. 5.3. 12-bit Nyquist-rate ADC . . . . . . . . . . . . . . . . . . . . . . . . . .. 97. 6.1. Gains and offsets of the pipline stages in simulations. . . . . . . . . . . . 114 ES. A. 5.1. 1896. xi.

(23) A. ES. 1896. xii.

(24) List of Figures Block disgram of DSP-based system. . . . . . . . . . . . . . . . . . . . .. 1. 1.2. Impact of deep-submicron technology. . . . . . . . . . . . . . . . . . . .. 2. 2.1. Analog signal approximation concept. . . . . . . . . . . . . . . . . . . .. 8. 2.2. Pipelined ADC block diagram. . . . . . . . . . . . . . . . . . . . . . . .. 10. 2.3. Transfer characteristic of a pipelined ADC. . . . . . . . . . . . . . . . .. 10. 2.4. Signal flow of an analog processor. . . . . . . . . . . . . . . . . . . . . .. 11. 2.5. Input-referred signal reconstruction in digital domain. . . . . . . . . . . .. 12. 2.6. Encoding of the pipelind ADC. . . 1896 . . . . . . . . . . . . . . . . . . . . .. 13. 2.7. Quantization error and its probability-density function. . . . . . . . . . .. 14. 2.8. Schematic of a tranditional 2.5-bit switched-capacitor pipeline stage. . . .. 15. 2.9. Transfer function of Figure 2.8. . . . . . . . . . . . . . . . . . . . . . . .. 15. ES. A. 1.1. 2.10 The configurtion of the SC circuit in sampling phase and amplifying phase. 16 2.11 MDAC with M bit/stage in amplifying phase. . . . . . . . . . . . . . . .. 18. 2.12 An Opamp in closed loop configuration. . . . . . . . . . . . . . . . . . .. 19. 2.13 RC sampling network and its low-pass characterestics. . . . . . . . . . .. 20. 2.14 Sampling thermal noise of a M bit SC pipeline stage. . . . . . . . . . . .. 22. 2.15 Opamp input-referred noise and the model used to calculate the opamp thermal noise of the pipeline stage in amplifying phase. . . . . . . . . . .. 23. 2.16 Simple model used to represent the noise of the turn-on resistance Rs . . .. 24. 2.17 Simple model used to represent the noise of the turn-on resistance Rf . . .. 25. 2.18 A 12-bit ADC SNR versus total capacitance Ct for different stage resolution. 26 3.1. Vj -to-Do,j transfer characteristic of a pipelined ADC. . . . . . . . . . . . xiii. 30.

(25) 31. 3.3. Vj -to-Do,j transfer charasteristics of pipeline stage with Vjda mismatch. . . Vj -to-Do,j transfer charasteristics pipeline stage only with Gˆ j mismatch. .. 3.4. Output transfer curve of a pipeline stage. . . . . . . . . . . . . . . . . . .. 33. 3.5. Digital calibration concept. . . . . . . . . . . . . . . . . . . . . . . . . .. 34. 3.6. Calibration scheme of foreground calibration. . . . . . . . . . . . . . . .. 35. 3.7. Spread-spectrum modulation in correlation data extraction. . . . . . . . .. 37. 3.8. PN signal injects into the pipeline stage before the sub-ADC. . . . . . . .. 39. 3.9. PN signal injects into the pipeline stage before the sub-DAC. . . . . . . .. 40. 3.10 A 1.5-bit pipeline stage with capacitor swapping using PN signal. . . . .. 41. 3.11 The calibration scheme published in [1]. . . . . . . . . . . . . . . . . . .. 42. 3.12 The split-capacitor radix-2 1.5-bit pipeline stage in [2]. . . . . . . . . . .. 44. 3.13 Figure 3.12’s conversion characteristic with ”q” injection. . . . . . . . . .. 44. 3.14 A split-capacitor SC pipeline stage with N = 2. . . . . . . . . . . . . . .. 47. E S pipeline stage. . . . . . . . . . . . 3.15 Transfer characteristic of Figure 3.14’s. 47. 3.16 A split-capacitor SC pipeline stage with redundant comparators. . . . . .. 48. 3.17 Transfer characteristic of Figure 3.16’s pipeline stage. . . . . . . . . . . .. 48. 3.18 Configuration for gain/sub-DAC calibration. . . . . . . . . . . . . . . . .. 50. A. 3.2. 1896. 32. 3.19 Transfer characteristic of Figure 3.16’s pipeline stage when PN sequence is injected in it. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 52. 3.20 A correlation-based Wj,k extractor. . . . . . . . . . . . . . . . . . . . . .. 54. 3.21 An alternative form of Wj,k extractor. . . . . . . . . . . . . . . . . . . . .. 54. 4.1. Multi-bit pipelined ADC transfer charateristics with stage nonlinearity. . .. 58. 4.2. Basic nonlinearity correction scheme. . . . . . . . . . . . . . . . . . . .. 59. 4.3. Input-output transfer curve for linear and nonlinear opamp. . . . . . . . .. 61. 4.4. Correlation-based nonlieanr detection technique. . . . . . . . . . . . . .. 62. 4.5. Linear system definition. . . . . . . . . . . . . . . . . . . . . . . . . . .. 63. 4.6. Pipeline stage transfer curve with random sequence injection for linear and nonlinear amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 65. 4.7. A pipeline stage for b3 nonlinearity calibration. . . . . . . . . . . . . . .. 66. 4.8. Analog transfer fynction of a nonlinear pipeline stage. . . . . . . . . . . .. 66. xiv.

(26) 4.9. Configuration for nonlinearity calibration. . . . . . . . . . . . . . . . . .. 67. 4.10 Calibration processor for b3 calibration. . . . . . . . . . . . . . . . . . .. 69. 4.11 A correlation-based dual-q. I Wj,k. extractor. . . . . . . . . . . . . . . . . .. 69. 4.12 Calibration processor for b3 and b5 calibration. . . . . . . . . . . . . . . .. 73. 4.13 Calibration processor for b2 and b3 calibration. . . . . . . . . . . . . . . .. 75. 4.14 HIII /HII versus Y 0 at various Cs,i . . . . . . . . . . . . . . . . . . . . . . .. 78. 5.1. Pipelined ADC architecture. . . . . . . . . . . . . . . . . . . . . . . . .. 80. 5.2. Schematic of the pipeline stage for gain/DAC calibration. . . . . . . . . .. 81. 5.3. Transfer function of Figure 5.2 when random sequence is injected in it. . .. 81. 5.4. Schematic of the pipeline stage for nonlinearity calibration. . . . . . . . .. 82. 5.5. Analog transfer function of a nonlinear pipeline stage when qa and qb are 82. 5.6. Bootstrapped analog switch proposed in [3]. . . . . . . . . . . . . . . . .. 84. 5.7. Traditional folded-cascode two stage opamp. . . . . . . . . . . . . . . .. 85. 5.8. Proposed two stage opamp circuit. . . . . . . . . . . . . . . . . . . . . .. 85. 5.9. Switched-capacitor comparator circuit schematic. . . . . . . . . . . . . . 1896. 86. 5.10 Testing enviroment setup. . . . . . . . . . . . . . . . . . . . . . . . . . .. 88. 5.11 Micrograph of the ADC prototype. . . . . . . . . . . . . . . . . . . . . .. 89. 5.12 Measured DNL performance at 12-bit resolution. . . . . . . . . . . . . .. 91. 5.13 Measured INL performance at 12-bit resolution. . . . . . . . . . . . . . .. 92. 5.14 Measured FFT spectrum. . . . . . . . . . . . . . . . . . . . . . . . . . .. 93. 5.15 Measured SNR and SFDR versus input frequencies with 80MS/s. . . . . .. 94. 5.16 Measured THD versus input frequencies with 80MS/s. . . . . . . . . . .. 95. ES. A. injected in it. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6.1. Two-channel ADC architecture proposed in [4]. . . . . . . . . . . . . . . 100. 6.2. Basic concept of split-channel ADC architecture. . . . . . . . . . . . . . 101. 6.3. Split-channel ADC architecture for background calibration. . . . . . . . . 102. 6.4. Predict the input signal using a FIR filter. . . . . . . . . . . . . . . . . . 103. 6.5. Split-channel ADC architecture for background calibration. . . . . . . . . 104. 6.6. Calibration processor for the split-channel ADC. . . . . . . . . . . . . . 107. 6.7. OC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 xv.

(27) 6.8. GC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110. 6.9. Simulated gc and oc versus calibration cycle. . . . . . . . . . . . . . . . . 115. 6.10 Simulated ADC’s SNDR versus calibration cycle. . . . . . . . . . . . . . 116. ES. A. 6.11 Simulated SNDR performance with different values of M. . . . . . . . . 117. 1896. xvi.

(28) Chapter 1 Introduction 1.1. Motivation A. The role of analog-to-digital converter (ADC) is the interface between the analog signal ES and the digital signal processing system as shown in Figure 1.1. Various ADCs have been designed for the same purpose. Pipelined ADC is a popular structure in nowadays because 1896 resolution. Other structures are hard to of the compromise between high speed and high. achieve high speed and high resolution requirements at the same time. Although several design configurations are used for pipelined ADC, switched-capacitor (SC) structure is particularly popular due to its capability of high-precision sampling and charge transfer. The resolution of the SC pipeline ADC is mainly limited by the matching of the capacitors and the finite gain of the operational amplifier. The nature matching of the capacitors in. Vi. Analog. ADC. Signal Processing. DSP. PGA Analog Domain. Digital Domain. Figure 1.1: Block disgram of DSP-based system. 1.

(29) 2. CHAPTER 1. INTRODUCTION VDD Cf. Vi. Cs. M2. Vo. Cp. A0. M1. Vdsat2 . r o2. r o1. Vdsat1 . GND. Figure 1.2: Impact of deep-submicron technology. modern technology limited the resolution of pipelined ADC to 10-12bit. Moreover, it is more difficult to design a high gain operational amplifier for high resolution ADC because of the shrinks of the channel length and supply voltage. In deep-submicron technology, the parasitic of MOS transistor is smaller than its A. ES long channel counterpart and reduced parasitic makes the device be able to be oper-. ated in higher frequency. This feature also means the circuit can be implemented with lower power dissipation and smaller area. However, short channel device has low output 1896. impedance and this limits the achievable gain of an amplifier. A closed-loop amplifier is shown in Figure 1.2 and its output is Vo Cs = × Vi Cf. 1 1 Cs + Cf + Cp 1+ · A0 Cf. (1.1). The accuracy of the amplifier output is affected by the gain of the opamp. Furthermore, low gain opamp means the signal swing at the opamp’s input node is increased. This also increases nonlinear distortion of the amplifier [5]. Besides, the thickness of the gate oxide is also reduced and that means the supply voltage must be reduced for reliability issue. Reducing the supply voltage also reduces the dynamic range of the analog circuits, as shown in Figure 1.2. These properties make analog circuit design have more challenges especially for the circuits that need high gain amplifier and large dynamic range. In order to design a high performance analog circuit in such a suffering condition, these drawbacks must be overcome by other techniques. In this thesis, the analog circuit imperfection is remedied by digital calibration..

(30) 1.1. MOTIVATION. 3. In a SC pipelined ADC, capacitor mismatch and finite opamp dc gain make the residue gain and sub-DAC output deviate from its nominal value. In order to overcome these natural limitations, various calibration techniques are proposed to enhance the ADC resolution. By using these techniques, the matching and gain requirements can be greatly loosened and the analog circuit can be implemented with less complexity. This means that the ADC can be fabricated with less power dissipation and smaller area. ADC calibration can be classified into analog calibration and digital calibration. Analog calibration means that the ADC imperfection is corrected in analog domain. However, this technique usually makes the analog circuitry more complex and usually needs larger area. This is undesirable because it may deteriorate the circuit performance. In contrast, digital calibration usually corrects the ADC imperfection in digital domain. This technique may need more complex digital signal process. However, this overhead is inapparent in advanced used at present.. ES. A. technology. For these reasons, digital calibration technique is more popular and is widely In pipelined analog-to-digital converter (ADC) designs, digital calibration enables a trade-off between analog circuitry and digital circuitry. Various correlation-based digital 1896 background calibration schemes have been proposed [2, 5, 6, 7, 8, 9, 10]. They share. the same basic principle which involves randomly varying the configuration of a pipeline stage, digitizing its analog output by using its back-end stages, and then extracting the slow-varying stage parameters in the digital domain by employing correlation. They differ in (1) how a pipeline stage is reconfigured; (2) what and how stage parameters are extracted; (3) how the overall A/D conversion is corrected. Criteria to evaluate a calibration scheme include: 1. Hardware overhead. What analog and digital circuits are added? Are circuit performances, such as speed and power, deteriorated by the circuit modification? 2. Signal range overhead. How much extra signal range does the calibration require? This is crucial for circuits already under low-voltage supplies. 3. Component matching requirement. Does the calibration scheme hint any matching requirement for circuit components? Is the calibration sensitive to offset or other effects due to mismatches?.

(31) 4. CHAPTER 1. INTRODUCTION. 4. Robustness. Can the background calibration be effective under any input condition? Is the calibration still functional if the input is a dc signal? 5. Calibration time. How long does it take for the calibration process to converge? Can the calibration track the variations of the stage parameters? A generic pipeline stage comprises a sub-ADC, a sub-DAC, and a subtracting amplifier. Calibrating a pipeline stage is extracting the parameters related to the characteristics of its sub-DAC and amplifier. The extracted data are then used to correct the digital output so that the overall analog-to-digital (A/D) conversion becomes linear. To enable background calibration, a pipeline stage is randomly reconfigured by either switching the sub-ADC’s thresholds [5, 6] or adding a digital test signal to the sub-DAC’s input [2, 7, 8]. However, the above stage reconfiguration techniques increase the stage’s output signal range. The original signal range can be restored by adding redundant sub-ADC A. thresholds and extra sub-DAC output levelsE[5, S 10]. Some calibration schemes assume certain matching requirements. The [6] scheme requires a precise sub-ADC threshold shift. The [5, 7] schemes assume the sub-DAC has an 1896 uniform output step size. On the other hand, the [8, 9] schemes employ a separate calibra-. tion procedure to correct the sub-DAC error, thus eliminating the matching requirement. The [2] scheme calibrates both gain and sub-DAC at the same time; thus, no need to have any component matching. Correlation-based calibration schemes usually require a large number of samples to extract accurate data, thus resulting in long calibration time. There are techniques to reduce the calibration time [6, 10, 11, 12]. To further improve A/D conversion linearity, there are schemes which also calibrate amplifier’s nonlinearity [5, 7, 9]. However, the schemes of [5, 7] cannot function under certain input conditions, such as a dc input. The [9] scheme requires extra signal range, which in turn degrades stage linearity. Unlike simple gain/sub-DAC calibration, amplifier’s offset can affect nonlinearity calibration. Nevertheless, it was neglected or was not corrected in the aforementioned schemes. In this thesis, a 12-bit pipelined ADC was designed to demonstrate a new digital background calibration scheme that can calibrate stage gain, sub-DAC, and stage nonlinear-.

(32) 1.2. ORGANIZATION. 5. ity simultaneously. To enable background calibration, multiple uncorrelated random sequences are injected into a split-capacitor pipeline stage. By employing input-dependent generation of the random sequences, no extra signal range is required. Calibration data are extracted by correlation-based integration-and-dump. Nonlinearity is detected by solving simple linear equations. The proposed calibration scheme needs no matching requirement and is flexible to include multiple harmonics calibration. The offset effect can be simply treated as even-order harmonics and be removed by calibration.. 1.2. Organization. The organization of the thesis is described as follow: Chapter 2 is the overview of pipelined ADC. Mathematics description and analysis are presented in this chapter. The design considerations of a pipelined ADC, including A. E S noise requirement etc., are introduced by opamp dc gain, capacitor matching and thermal. mathematics analyses. Chapter 3 describes the error sources of a pipelined ADC. The opamp’s finite dc gain 1896. and capacitor mismatch make the residue gain and sub-DAC output deviate from their nominal values and also result in nonlinear conversion of a pipelined ADC. To correct these errors, a new split-capacitor digital background calibration configuration is proposed. With calibration, the analog circuit imperfection is corrected. An input-dependent random sequence generator is also proposed to remedy the defects of prior arts. Chapter 4 analyzes the effect of the stage nonlinearity. In deep-submicron technology, high gain and high swing opamp is hard to obtain and the pipelined ADC may still have significant distortion even with gain and DAC calibration. To further enhance the resolution of the ADC, the pipeline stage nonlinearity must be corrected. Split-capacitor calibration technique is extended and used to correct the stage nonlinearity. To verify the digital background calibration configuration described in Chapter 3 and Chapter 4, a 65nm 12-bit 80MS/s pipelined ADC was demonstrated in Chapter 5. A low gain and low power dissipation opamp is also proposed in this chapter. Chapter 6 describes the convergence issue of a correlation-based calibration technique. The main source that limits the calibration data extraction time is mentioned in the chapter..

(33) 6. CHAPTER 1. INTRODUCTION. A new split-channel ADC configuration is proposed to remedy this drawback. With this technique, the calibration convergent speed is improved by more than 1000 times.. ES. A. Finally, conclusions and recommendations for future works will be given in Chapter 7.. 1896.

(34) Chapter 2 Overview of Pipelined ADC 2.1. Introduction A. Analog-to-digital converters (ADCs) are used E S to convert an analog signal into a corresponding digital output. Various different ADCs are designed to achieve the same purpose. Pipelined ADC is the most popular structure in nowadays because of the compro1896 mise between high speed and high resolution. Other structures are hard to achieve high. speed and high resolution requirements at the same time. Although several design styles are used for pipelined ADC, switched-capacitor (SC) structure is particularly popular due to its capability of high- precision sampling and charge transfer. The resolution of the SC pipelined ADC is mainly limited by the matching of the capacitors and the finite gain of the operational amplifier (opamp). In this chapter, we will introduce the concept and the error sources of pipelined ADCs by mathematic analysis. The operation of a 2.5-bit pipeline stage is also described in this chapter. Moreover, the design considerations of a pipelined ADC are also analyzed.. 2.2. Quantization Feedforward Architecture. Analog-to-digital converters (ADCs) are used to quantize an analog signal Vi to a digital signal Do which is a linear representation of Vi . To achieve this goal, a signal approximation concept can be used to estimate the analog signal. As shown in Figure 2.1, the input 7.

(35) 8. CHAPTER 2. OVERVIEW OF PIPELINED ADC. Dj +4 V2. +3 +2. V1. +1 0 −1. A. ES. V3. 1896. −2. V4. −3 −4. D 1=+2. D 2=+3. D 3=+1. Figure 2.1: Analog signal approximation concept.. D 4=−2.

(36) 2.2. QUANTIZATION FEEDFORWARD ARCHITECTURE. 9. V1 is first compared with a scaler and is coarsely quantized, the output D1 is 2. D1 is the rough estimation of the signal V1 . The coarsely quantized output D1 is then subtracted from V1 . The resulting residue value is multiplied with G1 = 9 and amplified to the full scale. In the next step, V2 is quantized again with the same scaler and D2 = 3. Then D2 is subtracted from V2 and the residue is amplified again to the full scale. These processes repeat in each comparison. With the residue gain, the input signal can be quantized more accurately with the same scaler, as shown in Figure 2.1. If Gj = 1 for each comparison, we will need a more accurate scaler for the later conversion. By combining the output Dj for each conversion, we can estimate and linear represent the input Vi . As illustrated in this figure, the input V1 can be expressed as: V1 = 2 +. 1 −2 VP +1 3 + 2 + 3 + ··· + P 9 9 9 9. (2.1). ES. A. where P is the total conversion number. The denominator in Equation (2.1) is because the residue of each conversion is amplified by the gain factor and is referred back to the input. A pipelined ADC is used to realize this signal approximation processing. The general 1896 form of a pipelined ADC is shown in Figure 2.2, which consists of P identical pipeline stage. Each pipeline stage includes both an analog processor (AP) and an encoder. A AP comprises sample and hold amplifier (SH), sub-ADC, sub-DAC and residue amplifier. For the j-th AP, its analog input Vj is quantized by an internal sub-ADC and generates a digital output Dj . Its digital output Dj drives an internal sub-DAC to generate a corresponding analog signal Vjda . The digital signal Dj is a rough estimate of Vj in digital domain. Vjda is the analog expression of Dj and is an rough estimate of Vj in analog domain. The j-th stage’s analog output Vj+1 can be expressed as: Vj+1 = Gj × Vj − Vjda. . (2.2). The output Vj+1 is the residue voltage that is obtained by amplifying the quantization error by the gain factor Gj , the Vj -Vj+1 transfer function is shown in Figure 2.3. The detail operation and the analog signal flow of the pipeline stage is shown in Figure 2.4. To obtain a linear representation of the input signal, Equation (2.2) can be re-written.

(37) 10. CHAPTER 2. OVERVIEW OF PIPELINED ADC. Vj. SH. +. ADC. V2. AP 1. V3. AP. da. j. VP. 2 D1. Do,1. V. Encoder. D2 Do,2. 1. AP. VP+1. P. Encoder. ES. DP A. V1. Dj. −. DAC. V j+1. Gj. Do,3. Do,P. 2. Encoder P. 1896. Figure 2.2: Pipelined ADC block diagram.. V j+1. Vj. Dj. −3. −2. −1. 0. +1. +2. +3. Figure 2.3: Transfer characteristic of a pipelined ADC..

(38) 2.2. QUANTIZATION FEEDFORWARD ARCHITECTURE. 11. Vsg. Vj. +. ad Vj. Vj. Dj 2. ad. V. ad. 0 ad. ad. V. Vj+1. (+2). da. V 1896. (+1). (2). 0 V. da. Vsg. da j. da Vj E SV. V j+1. (3) 1. V. V. DAC. A. ADC. Dj. −. Gj. da. V. (0). 0. (1) da. 1. V. 2. V. (−1). (0) da. (−2). Figure 2.4: Signal flow of an analog processor.. 0.

(39) 12. CHAPTER 2. OVERVIEW OF PIPELINED ADC. Vj. SH. +. ADC Analog Domain Digital Domain D o,j. V j+1. Ideal ADC. − V. DAC. Dj +. Gj. da. j D o,j+1. +. 1/G d. Figure 2.5: Input-referred signal reconstruction in digital domain. as: Vj =. 1 × Vj+1 + Vjda Gj. (2.3). A. ES The signal processing of Equation (2.3) is usually implemented in digital domain and can. also be depicted in Figure 2.5. Vjda in Equation (2.3) is replaced with Dj in this figure and Gj is replaced with Gd , because they represent the same signal in different signal domain. 1896. The ideal ADC in Figure 2.5 linearly transfers its input signal to a corresponding digital output, that means Do,j+1 = Vj+1 . According to Equation (2.3), the input analog signal V1 in Figure 2.2 can be approximated as a digital output Do,1 and can be expressed as: Do,1. V3da V4da V2da VPda VP +1 + + + ··· + + = + G1 G1 G2 G1 G2 G3 G1 G2 · · · GP −1 G1 G2 · · · GP D2 D3 D4 DP = D1 + + + + ··· + + Qn G1 G1 G2 G1 G2 G3 G1 G2 G3 · · · GP −1 V1da. = W 1 + W 2 + W 3 + W 4 + · · · + W P + Qn. (2.4) (2.5) (2.6). where Qn is the quantization error and its value is Qn =. VP +1 G1 G2 · · · GP. (2.7). Wj =. Dj G1 G2 · · · Gj−1. (2.8). and.

(40) 2.2. QUANTIZATION FEEDFORWARD ARCHITECTURE. V2. AP. V1. 1. VP−1. 2 D2. Look−up Table. Look−up Table Do,2. VP. AP P−1. D1. W1 Do,1. V3. AP. 13. W2. DP−1 Look−up Table Do,3. Do,P−1. WP−1. AP P DP Look−up Table WP. Figure 2.6: Encoding of the pipelind ADC.. The result is consistent with the result mentioned in Equation (2.1). The input signal can A. be correctly estimated by combing the Wj of each stage. Consequently, as long as the Dj ES and Gj are known for each conversion, the input signal can be approximated. Based on Equation (2.6), the complete block diagram of the pipelined ADC is shown 1896. in Figure 2.6, where Do,1 is simplified as Do and Qn is ignored. An ideal ADC is used to convert the input signal to a corresponding output and the output should be a linear representation of the input. Pipelined ADC can achieve this goal by simply repeating the same signal processing in analog domain and combining the output in digital domain. Now we consider the effect of quantization error. The quantization error Qn of a ADC and its probability-density function (PDF) is shown in Figure 2.7 [13], ∆ is the leastsignificant bit (LSB) of the ADC and its value is. ∆=. VF S 2N. (2.9). where VF S is the full-scale input range of the ADC and N is the resolution of the ADC. Assuming that the quantization error uniform distributes between +∆/2 and −∆/2 and.

(41) 14. CHAPTER 2. OVERVIEW OF PIPELINED ADC. Qn. PDF. +∆ +∆/2 V. 1/∆ . −∆ j. −∆/2. +∆. Qn. +∆/2. −∆/2 −∆. Figure 2.7: Quantization error and its probability-density function. its PDF is 1/∆. The quantization noise power, PQn , is. = =. −∆/2 Z +∆/2 −∆/2 2. ∆ 12. (Qn )2 × pdf (Qn ) d(Qn ) (Qn )2 × ES. 1 d(Qn ) ∆ A. PQn =. Z +∆/2. (2.10) (2.11) (2.12). For an ideal ADC which contains only the quantization noise, the SNR is 1896. SNR =. V 2 /8 22N · 3 Pin = F2S = PQn ∆ /12 2. = 6.02 · N + 1.76 (dB). (2.13) (2.14). where Pin is the input signal power. We assume the input signal is sine-wave and its amplitude is VF S /2. This value is the natural limitation for a ADC design.. 2.3. A 2.5-bit Pipeline Stage. Multi-bit switched-capacitor (SC) pipelined ADC is widely used in recent years because it can achieve the same resolution with fewer opamps. Multi-bit pipeline stage usually suffers from the low feedback factor and that usually means low operating frequency. However, this drawback can be mitigated by using deep-submicron technology which has higher unit-gain frequency. This architecture also loosens the opamp’s dc gain requirement. Consequently, multi-bit pipeline stage becomes a popular choice in nowadays..

(42) 2.3. A 2.5-BIT PIPELINE STAGE. 15. 2 1. Vj. 1 sub−ADC. Vr B1. 1. 1. Do,j B 1 B 2 B 3. 1. Vj+1. Cs3. 2. Vr B3. A0. Cs2. 2. Vr B2. Encoder. Cs1. 2. Dj Do,j+1. Cf. ES. 5/8Vr. A. Figure 2.8: Schematic of a tranditional 2.5-bit switched-capacitor pipeline stage.. V j+1 1896. 3/8Vr. 1/8Vr. 1/8Vr. 3/8Vr. 5/8Vr. Vr 0.5Vr 0. Vj. 0.5Vr Vr 6/8Vr. 4/8Vr. 2/8Vr. 2/8Vr. 4/8Vr. 6/8Vr. B1. −1. −1. −1. 0. +1. +1. +1. B2. −1. −1. 0. 0. 0. +1. +1. B3. −1. 0. 0. 0. 0. 0. +1. Dj. −3. −2. −1. 0. +1. +2. +3. Figure 2.9: Transfer function of Figure 2.8..

(43) 16. CHAPTER 2. OVERVIEW OF PIPELINED ADC. Cf. V rx B 1. Vj. A0 C s,3. V j+1. V rx B 2 V rx B 3. C s,1. Cf. C s,2 C s,3. φ 1=1. Cp. A0. V j+1. φ 2=1. Sampling Phase. Amplifying Phase. Figure 2.10: The configurtion of the SC circuit in sampling phase and amplifying phase.. In this thesis, instead a 1.5-bit pipeline stage, a 2.5-bit pipeline stage is introduced and implemented. Figure 2.8 is a 2.5-bit SC pipeline stage and the corresponding conversion A. characteristic of the pipeline stage is shown E Sin Figure 2.9. The SC pipeline stage can provide the gain of four and also have the sample-and-hold function. The switches in Figure 2.8 are controlled by two non-overlapping clocks, φ1 and φ2 . During φ1 = 1, also called sampling phase, the voltage Vj is1896 sampled on capacitors Cf , Cs,1 , Cs,2 , and Cs,3 . During φ2 = 1, also called amplifying phase, Cf becomes a feedback capacitor, and each Cs,i , where i = 1, 2, 3, is connected to a Vr × Bi reference. The value of Bi is among {−1, 0, +1}. The Cs,i capacitors form the sub-DAC, whose output is controlled by the signals Bi . The pipeline stage in sampling phase and amplifying phase are shown in Figure 2.10. The sub-ADC comprises 6 comparators with thresholds at ±Vr /8, ±3Vr /8 and ±5Vr /8 respectively. Its digital output Dj is an estimate of the input Vj . The relationship between Dj and Vj is shown in Figure 2.9. The value of Dj is among {0, ±1, ±2, ±3}. Assume the opamp in Figure 2.8 is linear and has a finite dc gain of A0 . Then, its output during φ2 = 1 can be written as:. Vj+1 = Gˆ j × Vj − Vˆ jda − Vjos. (2.15).

(44) 2.4. OPAMP GAIN AND CAPACITOR MATCHING. where Gˆ j =. Cs + Cf × Cf. 1 1 Cs + Cf + Cp 1+ · A0 Cf. Vˆ jda = Vr. 3 X Cs,i × Bi i=1. Cs + Cf. Cs = Cs,1 + Cs,2 + Cs,3. 17. (2.16). (2.17) (2.18). Comparing Equation (2.15) with Equation (2.2), Gˆ j and Vˆ jda represent the actual value which contain the capacitor mismatch and opamp’s finite dc gain. In Equation (2.16), A0 is the opamp’s dc voltage gain and Cp is the capacitance associated with the opamp’s negative input node. The Vjos term represents the offset of the j-th stage, which summarizes the offset effect due to the input-referred offset voltage of the opamp, the charge injection. ES. A. from the analog switches, and the offset of the sub-DAC. If Cf = Cs,1 = Cs,2 = Cs,3 and opamp’s dc gain is infinite, the nominal value of Gˆ j = 4 and Vˆ jda = 0, ±2Vr /8, ±4Vr /8 and ±6Vr /8 respectively. The SC circuit in Figure 2.8 can perform the sample-and-hold (SH), sub-DAC and multiplication function, and is also called multiply-DAC (MDAC). 1896. 2.4. Opamp Gain and Capacitor Matching. Equation (2.16) and Equation (2.17) show that Gˆ j and Vˆ jda are affected by opamp’s dc gain and capacitor mismatching. To achieve desired ADC resolution, large enough dc gain is required to reduce the error in Gj . In addition to opamp’s dc gain, capacitor matching in the SC circuit must be good enough to reduce the error in Gˆ j and Vˆ jda . In this section, we will determine gain and matching requirements of pipelined ADCs. According to Equation (2.16), gain error of a M bit pipeline stage in Figure 2.11 can be written as: Gain error =. ∆Vj+1 Cs + Cf + Cp 1 = × Vj+1 A0 Cf. (2.19). where Cf = C and CS = (2M−1 − 1) · C. The output Vj+1 of the pipeline stage is sampled by the backend ADC. Usually we want Cs + Cf + Cp 1 1 × ≤ Z+1 A0 Cf 2. (2.20).

(45) 18. CHAPTER 2. OVERVIEW OF PIPELINED ADC. C C C C (2. M−1 −1) C. A0. Vo. C. Figure 2.11: MDAC with M bit/stage in amplifying phase. where Z is the resolution of the backend ADC. If the resolution of the entire pipelined ADC is N and N = M + Z − 1. Then Equation (2.20) can be re-written as: Cp C C p = 2N+1 × 1 + M−1 ·C ES 2. (2.21) (2.22). A. A0 ≥ 2Z+1 × 2M−1 +. Equation (2.22) shows that for high resolution application, large dc gain is required to make the error neglected. In deep-submicron technology, large dc gain is obtained by cascading several gain stages. However, this1896 topology usually needs frequency compensation that will decrease the unit-gain frequency of the opamp. Equation (2.22) also reveals that increasing bit/stage loosens the gain requirement, because the second term in Equation (2.22) is insignificant for large M. As mentioned in previous section, for a M bit pipeline stage, 2M−1 capacitors are used to sample and amplify the signal. Assuming that each capacitor has ∆C/C mismatch, generally the capacitor matching requirement can be expressed as: 1 1 ∆C ≤ Z+1 × √ C 2 2M−1. (2.23). Increasing bit/stage will relax the matching requirement of the capacitor. For current CMOS technology, 0.1% capacitor matching can be obtained easily and achieve more than 10-bit resolution. For high resolution application, we can use large capacitor to improve the matching requirement. However, this approach increases the power dissipation of the amplifier. Generally calibration can be applied to relax the requirement and enhance the resolution..

(46) 2.5. OPAMP SPEED REQUIREMENT. 19 Cf. Vi. Cs. I. Vo. Gm. Cp. CL. Figure 2.12: An Opamp in closed loop configuration.. 2.5. Opamp Speed Requirement. For the SC circuit mentioned above, the opamp is configured as a closed loop amplifier in amplifying phase. Figure 2.12 is an opamp in closed loop configuration. The input-output transfer function of the closed loop amplifier can be calculated as: Cf. Vo = × Vi Cf. A. 1−s· −Cs E S Gm 1 + sτ. (2.24). Gm is the transconductance of the opamp. The 3-dB bandwidth is 1896. ω3dB =. 1 Gm =f× = f × ωu τ Cload. (2.25). where f=. Cf Cs + Cf + Cp. Cload = CL +. Cf · (Cs + Cp ) Cs + Cf + Cp. (2.26) (2.27). The 3-dB bandwidth of the closed loop amplifier is determined by the opamp’s unit-gain bandwidth ωu and the feedback factor f. Assuming the amplifier is a single pole system. The step response of a single-pole system is −t τ Vo (t) = Vstep · 1 − e. (2.28). To achieve N-bit ADC, we usually want −tsettle ∆Vo 1 = e τ ≤ Z+1 Vo 2. (2.29).

(47) 20. CHAPTER 2. OVERVIEW OF PIPELINED ADC. R on. |H(f)|. 2 Vn. Vi. Brickwall Approximation. =. Vo C. f 0 (π/2) f 0. f. Figure 2.13: RC sampling network and its low-pass characterestics. where tsettle is the required settling time. Assuming that the clock period of the SC circuit is T and tsettle is half of the clock period. Equation (2.29) can be simplified as: T ≥ ln2 · (Z + 1) · τ 2. (2.30). A. ES Equation (2.30) can be used to roughly estimate the required time constant. In general,. tsettle is usually smaller than T/2 due to the output slewing and the nonoverlapping period for different clock phases. In general, increasing bit/stage in a pipelined ADC design will 1896. reduce the f and higher ωu is required for the same operating speed.. 2.6. Thermal Noise. Noise is an important concern in high resolution ADC design. To achieve desired signalto-noise ration (SNR), the noise should be as low as possible. The main noise source of the SC pipeline stage is thermal noise. Thermal noise comes from the turn-on resistance of the switches and the opamp. In this section, we will analyze and calculate the output noise of a pipeline stage.. 2.6.1. Sampling Thermal Noise. At first, we consider the noise generated during the sample duration. For a SC pipeline stage, the input is sampled by switches and capacitors. The thermal noise comes from the turn-on resistance of the switch and occurs at the sampling period, this can be realized in.

(48) 2.6. THERMAL NOISE. 21. Figure 2.13. The thermal noise of the turn-on resistance Ron is V¯ n2 = 4KT Ron. (2.31). The Vi -to-Vo transfer function H (s) of the Ron and C sampling network is a low-pass function and can be expressed as: H (s) =. 1 Vo = Vi 1 + sRon C. (2.32). its frequency response is shown in Figure 2.13 and is calculated as: 1. |H (f )|2 =. 1+(. f 2 ) f0. (2.33). where 1 f0 = E S 2πRon C A. (2.34). The noise bandwidth of the single-pole low-pass system can be approximated to f0 π/2. Hence, the noise sampled by the capacitor is. 1896. ¯2 = 4KT R × Vthn on. kT π f0 = 2 C. (2.35). The sampled thermal noise is inverse proportion to the sampling capacitor and independent of the turn-on resistance of the switch. Larger C may reduce the sampling noise but also reduce the operating bandwidth. A compromise should be made between the noise and the bandwidth requirement. Consider the sampling thermal noise of a M bit pipeline stage and there are 2M−1 identical capacitors used to sample and amplify the input signal, as shown in Figure 2.14. In sampling phase, Vi is sampled by the 2M−1 capacitors and according to Equation (2.35), the noise in each capacitor is kT/C. In amplifying phase, the noise in each capacitor transfers to the feedback capacitor. The total noise V¯ 2 at the output can be expressed as: o1. kT × 2M−1 V¯ o12 = C The total noise at the output depends on capacitor value and bit/stage.. (2.36).

(49) 22. CHAPTER 2. OVERVIEW OF PIPELINED ADC. C. C. C. Vi. Gm. Vo. C. M−1 −1) C. C. C. (2. C. C. C. Gm. Sampling Phase. Vo1 CL. Amplifying Phase. Figure 2.14: Sampling thermal noise of a M bit SC pipeline stage.. 2.6.2. Thermal Noise of Opamp. For a MOS transistor operating in saturation and strong inversion region, the channel ES. A. thermal noise can be modeled by a current source connected between the drain and source terminals. The noise current power spectral density (PSD) can be expressed as: I¯n2 = 4kT γgm. (2.37). 1896. where gm is the transcondutance of the transistor and γ is the noise factor which is about 2/3 for a long channel transistor. To represent the thermal noise of an opamp, a simple CMOS fully differential opamp is shown in Figure 2.15. The input-referred noise of the opamp is γ 2 2 V¯ n,op = V¯ n,on = 4kT × nf gm1. (2.38). where nf = 1 + gm3 /gm1 is the input-referred factor of the input differential pair and the active load. The simple model used to calculate the output-referred noise of the pipeline stage is shown in Figure 2.15. The noise transfer function can be expressed as Vo2 Cs 1 = 1+ × Vn,op Cf 1 + sτ. (2.39). where τ is the same as Equation (2.25) and Cf = C, CS = (2M−1 − 1)C. Assuming the opamp is a single pole system and the total output noise V¯ 2 which is due to the opamp o2.

(50) 2.6. THERMAL NOISE. 23. VDD. C C. M1 2 V n,op. M2 2 V n,on. M−1 −1) C. M4. C Gm. (2. M3. C Vo2 CL. C V n,op. Figure 2.15: Opamp input-referred noise and the model used to calculate the opamp thermal noise of the pipeline stage in amplifying phase. thermal noise is (2.40). A. 2 1 Cs 2 2 ¯ ¯ Vo2 = Vn,op × × 1+ ES 4τ Cf kT = × nf × γ × 2M−1 Cload. (2.41). 1896. Where the transcondutance Gm of the opamp is equal to gm1 . Cload is the same as Equation (2.27). Similar to the sampling thermal noise as it is, the noise at the output of the pipeline stage is independent of the transconductance of the opamp. The opamp induced noise at the output of the pipeline stage is inverse proportional to the total capacitance loading at the output node.. 2.6.3. Thermal Noise of Rs. In the next step, we consider the thermal noise comes from the turn-on resistance Rs . The switches are used to connect to the reference voltage in amplifying phase. First, we calculate the noise effect of one of the switches. The simple model is shown in Figure 2.16. The noise transfer function of this circuit can be approximated to. Vo3 ≈ Vn,s. Cf Gm 1 + sτ. 1−s·. (2.42).

(51) 24. CHAPTER 2. OVERVIEW OF PIPELINED ADC. V n,s. Rs. C C. M−1 −1) C. C C. (2. Gm. Vo3. C. Figure 2.16: Simple model used to represent the noise of the turn-on resistance Rs . In amplifying phase, there are (2M−1 − 1) different noise sources and all of them are uncorrelated to each other. According to superposition theory, the total output noise V¯ 2 is o3. A. 1 2 V¯ o32 = V¯ n,s × × 2M−1 − 1 4τ kT = × 2EM−1 − 1 × gm1 Rs S Cload. (2.43) (2.44). 2 where the turn-on thermal noise V¯ n,s is 4kT Rs . Similar to the opamp induced noise as it. is, the noise contributed by Rs is also inverse proportional to the total capacitance loading 1896. at the output node. Besides, the noise is also proportional to gm1 Rs .. 2.6.4. Thermal Noise of Rf. Finally we consider the thermal noise coming from the turn-on resistance Rf . In amplifying phase, the feedback capacitor connects between the input and output of the opamp. The turn-on resistance Rf also contributes noise to the output. The simplified model is shown in Figure 2.17 and the transfer function of Vn,f can be approximated to Vo4 ≈ Vn,f. Cs Gm 1 + sτ. 1+s·. (2.45). The output noise V¯ o42 introduced by Rf is 1 2 × V¯ o42 = V¯ n,s 4τ kT = × gm1 Rf Cload. (2.46) (2.47).

(52) 2.6. THERMAL NOISE. 25. C. C Rf. V n,f. (2. M−1 −1) C. C C Vo4. Gm. CL. C. Figure 2.17: Simple model used to represent the noise of the turn-on resistance Rf . 2 where the turn-on thermal noise V¯ n,f is 4kT Rf . Similar to Equation (2.44), the noise is. inverse proportional to the total loading capacitors at the output node and is proportional. 2.6.5. Total Noise of Pipelined ADC ES. A. to gm1 Rf .. The output noise coming from individual noise source has been calculated. By combining Equation (2.36), Equation (2.41), Equation (2.44) and Equation (2.47), we can estimate 1896 2 the total output noise V¯ n,out of the M-bit pipeline stage is 2 V¯ n,out = V¯ o12 + V¯ o22 + V¯ o32 + V¯ o42 kT kT × 2M−1 + × 2M−1 × γnf + gm Rs = C Cload. (2.48) (2.49). where we assume Rs = Rf for simplification. To further simplify Equation (2.48) and to calculate the input-referred noise of the pipeline stage, we assume Cload = 2C, γ = 2/3, nf = 2 and neglect the parasitic capacitor Cp . Next, assuming that the time constant τRC of the Rs and C is τ/8. That means Rs C =. Cload 1 × ⇒ gm1 Rs = 2M−3 8 f × gm1. (2.50). According to Equation (2.49) and Equation (2.50), the input referred-noise of the pipeline stage is 2 V¯ n,in. kT = × Ct. . 5 + 2M−4 3. (2.51).

(53) CHAPTER 2. OVERVIEW OF PIPELINED ADC. ES. A. 26. Figure 2.18: A 12-bit ADC SNR versus total 1896 capacitance Ct for different stage resolution. where Ct = 2M−1 C is the total capacitance of the pipeline stage. The first term in Equation (2.51) is introduced by opamp and sampling switch. The second term is introduced by switches in amplifying phase. If Ct is keep constant for different M, increasing bit/stage will increase the value of second term. This is because when bit/stage increases, the feedback factor reduces and larger gm1 is required for the same operating speed. Furthermore, increasing bit/stage means the unit capacitance C decreases and the turn-on resistance increases for the same time constant τRC . In reality, both quantization noise and thermal noise present in the pipelined ADC. Equation (2.12) and Equation (2.51) are used to represent the total noise in a pipelined ADC, the SNR of the ADC is VF S ( √ )2 2 2 SNR = kT 5 ∆2 M−4 α× × +2 + Ct 3 12. (2.52).

(54) 2.7. SUMMARY. 27. α is a scaling factor which is used to estimate the capacitor scale down effect and is usually larger than 1. Figure 2.18 is the SNR of a 12-bit ADC versus capacitor size for different stage resolution. Where VF S is 2 and α is 1 in this figure. For small capacitor size, the SNR is dominated by the thermal noise and increasing capacitor size will improve the SNR performance. For large capacitor size, the SNR is dominated by the quantization noise and further increasing the capacitor size has negligible effect. Another important issue is about the front-end sample and hold amplifier (SHA). In a conventional pipelined ADC design, a front-end SHA is usually adopted to ease the design requirement of the first pipeline stage. However, SHA do not provide signal amplification but induce additional noise source. Besides, to meet the resolution and speed requirements, SHA usually needs large capacitor and consumes large power. For these reasons, SHA is usually omitted to save area and power dissipation of the ADC in nowadays. The. ES. 2.7. A. omission of SHA needs careful design of the first pipeline stage and its sub-ADC.. Summary. In this chapter, the operation principle and 1896 the mathematical analysis of the pipelined ADC are introduced. Pipelined ADC is usually implemented in voltage mode SC circuit. The design considerations of a SC pipeline ADC are noise, amplifier gain and amplifier operation speed. With the mathematic analysis, we can get a general idea of designing a pipelined ADC. However, in real implementation, the circuits may suffer from some process variation such as capacitor mismatch or dc gain drift, etc.. These imperfections result in the nonlinear conversion of the pipelined ADC. In the following chapters, we will explain the nonlinearity induced by imperfection and see how to remedy these errors..

(55) CHAPTER 2. OVERVIEW OF PIPELINED ADC. ES. A. 28. 1896.

(56) Chapter 3 Gain/DAC Calibration 3.1. Introduction A. Pipelined analog-to-digital converters (ADCs) E S consist of comparators and switched capacitor (SC) multiplying digital-to-analog converter (MDAC). Individual MDAC is linearized by employing high-gain capacitive feedback. However, it is mainly the accuracy 1896 of conversion gain of each MDAC along the pipeline stage that determines the overall res-. olution of an ADC. For a SC MDAC, the uncertainty of its conversion gain is caused by capacitor mismatch and finite gain of the opamp. For high-resolution applications, several background calibration techniques have been developed to constantly monitor MDACs’s conversion gains against variations in temperature and supply voltage without interrupting normal analog-to-digital (A/D) conversion operation [5, 14, 15, 16, 17, 18]. In this chapter, the nonlinearity induced by capacitor mismatch and finite opamp dc gain will be analyzed. we will detail background calibration principle and propose a new configuration for background calibration.. 3.2. Gain and DAC Errors. As shown in Equation (2.15)-Equation (2.17), the transfer characteristic of a 2.5-bit pipeline stage is affected by capacitor mismatch and opamp’s finite gain. Due to component mismatches and variations in fabrication process, supply voltage, and tempera29.

(57) 30. CHAPTER 3. GAIN/DAC CALIBRATION. V r xB V r xB V r xB. C s,1. 1. Cf. C s,2. 2. V j+1 A0. C s,3. n. Backend ADC. Dz. D o,j. ES. A. D o,j. Dz. Encoder. +Wj,+1+W j,+2. +Wj,+1. V 1896. −Wj,−1 −W j,−2. B B B D. 1 2 3 j. j. −Wj,−1. −1. −1. 0. +1. +1. −1. 0. 0. 0. +1. 0. 0. 0. 0. 0. −2. −1. 0. +1. +2. Figure 3.1: Vj -to-Do,j transfer characteristic of a pipelined ADC..

(58) 3.2. GAIN AND DAC ERRORS. V. 31. j+1. D o,j. +1. V. V. j. j. −1. Figure 3.2: Vj -to-Do,j transfer charasteristics of pipeline stage with Vjda mismatch. ture, both Gˆ j and Vˆ jda (Dj ) may also deviate from their nominal values respectively. These A. E Sthe overall A/D conversion [19, 20, 21, 22]. undesired deviations lead into nonlinearity for. A multi-bit pipeline stage in amplifying phase is shown in Figure 3.1. The output Vj+1 is quantized by the backend ADC which comprises of (j+1)-th to P-th pipeline stages and 1896. the result is Do,j+1 . In the following section, we use Dz to denote the backend ADC output for simplification. Assuming that the backend ADC is an ideal ADC and linear converts its input Vj+1 to a corresponding output Dz , that means Dz = Vj+1. (3.1). To encode a pipelined ADC output is to generate a digital output which is the linear representation of its input signal, that means Vj -to-Do,j is a linear transformation. As shown in Figure 3.1, Do,j can be expressed as: Do,j = Dz +. n X. Bi × Wj,i. (3.2). i=1. The Dz is shifted up or down by Wj,i according to the value of Bi . The digital value Wj,i represents the transition height when Di is changed by one. If the transfer characteristic of the pipeline stage is ideal , which means the transition height is equal to the nominal value, then after encoding, the ADC output Do,j is a linear representation of its analog input Vj , as shown in Figure 3.1..

(59) 32. CHAPTER 3. GAIN/DAC CALIBRATION. V. V. j+1. +1. j+1. +1. V. V. j. −1. ES. D o,j o. 1896. V. ^ G < nominal value j. A. −1. j. Do o,j. V. j. ^ G > nominal value j. Figure 3.3: Vj -to-Do,j transfer charasteristics pipeline stage only with Gˆ j mismatch.. j.

(60) 3.3. DIGITAL FOREGROUND CALIBRATION −3/8Vr. 33. −1/8Vr +1/8V r V j+1. a. R. +3/8V r. j,+1. c. R. j,+2 V. R D. j. j,−2 −2 da V j,−2. R. b. j,−1. −1 da V j,−1. 0 da V j,0. j. d +1 da V j,+1. +2 da V j,+2. Figure 3.4: Output transfer curve of a pipeline stage.. ES. A. However, in actual condition, the transfer characteristic deviates from the ideal case and the transition height is different from the ideal value, as shown in Figure 3.2 and Figure 3.3. Where the dash line is the ideal case and the solid line is the case with mismatch. Figure 3.2 is the pipeline stage that contains only Vˆ jda mismatch and Figure 3.3 contains 1896. only Gˆ j mismatch. Vˆ jda and Gˆ j make the transition height larger or smaller than the nominal value. According to Equation (3.2), the deviation of the transition height makes Vj -to-Do,j conversion not a linear relationship and have a discontinuous jump. These discontinuity means nonlinear distortion occurs in A/D conversion. This results can also be realized in Figure 3.2 and Figure 3.3. Imperfections introduce missing code and missing decision level in A/D conversion. In order to linearize the output of the ADC, the pipeline stage must be calibrated to eliminate these errors. We will introduce calibration techniques in the following section.. 3.3. Digital Foreground Calibration. As mentioned above, to linearize the Vj -to-Do,j transfer characteristic of the ADC, the transition height of the pipeline stage must be calculated and corrected, and then used to encode the ADC’s output. The calibration of the j-th pipeline stage involves measuring the.

(61) 34. CHAPTER 3. GAIN/DAC CALIBRATION. Vj+1. Stage. Vj. Backend. j. ADC Dj Dz. Look−up Table. CP. W j,i Doj Figure 3.5: Digital calibration concept. magnitude of the transition height and updating the value of Wj,i . According to Figure 3.4 ES. A. and Equation (2.15), the transition height can be calculated as: da da Rj,+1 = Vj+1,a − Vj+1,b = +Gj · Vj,+1 − Gj · Vj,0. (3.3). da da Rj,+2 = Vj+1,c − Vj+1,d = +Gj · Vj,+2 − Gj · Vj,+1 ..1896 .. (3.4). The transition height of the Vj -to-Vj+1 transfer function in Figure 3.4 is the value of Rj,i when the Dj digital code is changed by one. During calibration, Rj,i is measured and digitized by a backend pipelined ADC, and the result is Wj,i . Wj,i is the digital expression of Rj,i . The backend ADC quantizes the output Vj+1 of the j-th stage and generates a corresponding digital code Dz . If the backend ADC has a linear A/D characteristic, then its input Vj+1 can be denoted as: Vj+1 =. 1 × Dz + Oz + Qz Gˆ z. (3.5). This Vj+1 -to-Dz conversion contains a conversion gain of 1/Gˆ z , an offset of Oz , and a quantization error of Qz . According to Equation (3.3)-Equation (3.5), the calibration processor (CP) can yield calibration data Wj,i that is related to Rj,i as: Wj,i = Gˆ z × Rj,i. (3.6).

(62) 3.3. DIGITAL FOREGROUND CALIBRATION. Vj. MUX. Vc. V j+1 SH. + MUX. Dc CAL. 35. ADC. DAC. Gj − V. da j,i. Backend ADC Dz CP. CAL W j,i. Dj. Figure 3.6: Calibration scheme of foreground calibration.. Wj,i is the linear representation of Rj,i and contains the actual gain of the backend ADC. During normal A/D conversion operation, the Wj,i data become a look-up table, as shown in Figure 3.5. A. In order to linearize the ADC, digital foreground calibration technique is used to calES ibrate the ADC [22, 23, 24, 25]. Foreground calibration, also called off-line calibration, is to calibrate the ADC with a deterministic testing analog input signal. During calibra1896 tion period, the actual analog input is disabled and the calibration signal is applied to the. ADC. Based on this reason, foreground calibration is usually performed in the power-on condition or the idle duration. By using a deterministic input signal, the calibration can be accomplished with less clock cycles compared with a background calibration technique. Figure 3.6 is one of the scheme used to perform the foreground calibration. The concept of the foreground calibration is based on Equation (3.3) and Equation (3.4). To measure the transition height in foreground, the analog testing input Vc is applied to the pipeline stage and the analog input Vj is disabled in samplng phase, as shown in Figure 3.6. In amplifying phase, the sub-DAC input connects to Dc . To calculate Rj,1 , Vc = +Vr /8 and Dc changes from 0 to +1, that will alternate the output of the pipeline stage from a to b in Figure 3.4. Wj,1 can be estimated by calculating the difference of Dz when Dc changes from 0 to +1. The Wj,i data in look-up table is then updated by the estimated Wj,1 . To calculate Rj,2 , Vc = +3Vr /8 and Dc changes from +1 to +2, that will alternate the output of the pipeline stage from c to d in Figure 3.4. Wj,2 can then be obtained in the same way. The calibration procedure is repeated and is completed when all the transition.

(63) 36. CHAPTER 3. GAIN/DAC CALIBRATION. heights Wj,i are obtained. By calculating the difference of Dz , the transition height can be obtained easily. However, foreground calibration can not trace the change of temperature, supply voltage and other environment variation. Moreover, when the calibration is performed, the interruption of the input signal may not be suitable of some actual applications. These reasons make background calibration more attractive.. 3.4. Correlation-Based Technique. Correlation-based technique is the most popular technique in digital background calibration. This technique is developed based on spread-spectrum modulation theory and used in background calibration. Spread-spectrum modulation technique is widely used in communication system [26]. With spread-spectrum modulation, the modulated signal can be A. transmitted to the receiver with high suppression E S of the interference. In this technique the desired input signal is spread by a pseudo-random number (PN) sequence and transmitted to the receiver. The desired signal passes through the channel with wideband interference 1896 that comes from the other channels. In the receiver, the received signal is despread by the. same PN sequence and the interference is spread. Finally, a filter is used to extract the desired input signal. Now, this theory is used to calibrate the pipelined ADC. The desired signal, which is mentioned in spread-spectrum theory, is the calibration data which is the value contains the capacitor mismatch and finite opamp’s dc gain ,and is usually a dc signal. The ADC is like the channel in communication. The wideband interference is the ADC input analog signal and the ADC’s quantization noise. In this technique, the calibration data is modulated by a PN sequence and mixed with the input signal, as shown in Figure 3.7. It’s not necessary to interrupt the ADC’s input signal and makes background calibration possible. In calibration duration, the calibration data can be extracted from ADC output in background without interrupting the normal operation of the ADC. The ADC’s output Do can be written as: Do = Vi + Rj,i × q. (3.7). where Rj,i is the randomized calibration data that we want to extract from the output and.

(64) V. A. f. |H(f)|. LPF. |D ds | R j,i 11111111111 00000000000 00000000000 11111111111 00000000000 11111111111. V i Xq. Figure 3.7: Spread-spectrum modulation in correlation data extraction.. 11111111111 00000000000 00000000000 11111111111 00000000000 11111111111. |D o (f)|. Despreading. 1896. i WideBand Interference. Spreading. ADC. D ds. ES. R j,i. Do. q. Channel. q. f. t. PN Signal. 11111111111 00000000000 00000000000 11111111111 00000000000 11111111111. |q(f)|. −1. PN Signal. q(t). +1. f. 3.4. CORRELATION-BASED TECHNIQUE 37.

(65) 38. CHAPTER 3. GAIN/DAC CALIBRATION. Vi is the ADC’s input signal. The PN signal q is white noise and uncorrelated Vi , as shown in Figure 3.7. The PN sequence q alternates between −1 and +1 and its mean is zero. To despread Do , we multiply the output Do with q and the result is Dds = Do × q = Vi × q + Rj,i × q 2. (3.8). Vi is uncorrelated with q and will be spread in frequency domain. The expected value E[Vi × q] = E[Vi ] × E[q] = 0 and E[Rj,i × q 2 ] = E[Rj,i ] × E[q 2 ] = Rj,k . Because Rj,i is almost a dc signal, we can process Dds with a low-pass filter and the result is E[Dds ] = E[Vi × q] + Rj,i × E[q 2 ] = Rj,i. (3.9). The despread signal Vi × q is white in frequency domain and Rj,i is a dc value. To A. achieve desired SNR, the low-pass filter must E S have sufficient low bandwidth to filter out the out-of-band noise that results from Vi . The bandwidth requirement is an important issue in background calibration, we will discuss this later. To perform a background 1896 calibration in pipelined ADC, we must try to modulate the calibration data and mix it. with the input signal. This goal can be achieved in various ways, we will introduce these techniques in next section.. 3.5. Prior Arts. Various calibration techniques have been demonstrated in pipelined ADCs to enhance their linearity [5, 6, 7, 8, 9, 2, 10, 27, 28]. These calibration techniques can be perform in analog domain or digital domain. But in our discussion, we focus on correlation-based digital background calibration technique. Background calibration techniques usually need to modify the analog circuit or change the operation configuration, that usually make the analog circuit more complex. How to modify the analog circuits without degrading the operating speed is an important issue in background calibration. In this section, we will learn about these techniques..