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極高位元率數位用戶迴路之時脈同步設計

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國 立 交 通 大 學

電子工程學系 電子研究所碩士班

碩 士 論 文

極高位元率數位用戶迴路之時脈同步設計

Clock Synchronization of VDSL system

研 究 生:賴明秀

指導教授:陳紹基 博士

(2)

極高位元率數位用戶迴路之時脈同步設計

Clock Synchronization of VDSL System

研 究 生:賴明秀 Student:Ming-Hsiu Lai

指導教授:陳紹基 博士 Advisor:Sau-Gee Chen

國 立 交 通 大 學

電子工程學系 電子研究所所碩士班

碩 士 論 文

A Thesis

Submitted to Institute of Electronics

College of Electrical Engineering and Computer Science National Chiao Tung University

in Partial Fulfillment of the Requirements for the Degree of

Master of Science in

Electronics Engineering

May 2004

Hsinchu, Taiwan, Republic of China

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