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Comparative Study of Multigate and Multifin Metal–Oxide–Semiconductor Field-Effect
Transistor
View the table of contents for this issue, or go to the journal homepage for more 2010 Jpn. J. Appl. Phys. 49 04DC09
(http://iopscience.iop.org/1347-4065/49/4S/04DC09)
Comparative Study of Multigate and Multifin Metal–Oxide–Semiconductor
Field-Effect Transistor
Hui-Wen Cheng1and Yiming Li1;2;3
1Institute of Communication Engineering, National Chiao Tung University, Hsinchu 300, Taiwan 2Department of Electrical Engineering, National Chiao Tung University, Hsinchu 300, Taiwan 3National Nano Device Laboratories, Hsinchu 300, Taiwan
Received October 6, 2009; accepted December 25, 2009; published online April 20, 2010
In this work, we explore the effects of the number of fins and fin structure on the device DC, dynamic behaviors, and random-dopant-induced characteristic fluctuations of multifin field-effect transistor (FET) circuits. Multifin FETs with different fin aspect ratios [AR fin height (Hfin)/fin
width (Wfin)] and a fixed channel volume are simulated in a three-dimensional device simulation and the simulation results are experimentally
validated. The multi-fin FinFET (AR ¼ 2) has better channel controllability than the multifin trigate (AR ¼ 1) and multi-fin quasi-planar (AR ¼ 0:5) FETs. A six-transistor (6T) static random access memory (SRAM) using multi-fin FinFETs also provides the largest static noise margin because it supports the highest transconductance in FinFETs. Although FinFETs have a large effective device width and driving current, their large gate capacitance limits gate delay. The transient characteristics of an inverter with multi-fin transistors are further examined, and compared with those of an inverter with single-fin transistors. The multi-fin inverter has a shorter delay because it is dominated by the driving current of the transistor. With respect to random-dopant-induced fluctuations, the multifin FinFET suppresses not only the surface potential but also its variation because it has a more uniform surface potential than the multifin trigate and quasi-planar FET, and so the effects of random dopants on the circuits are attenuated. The results of this study provide insight into the DC, and circuit characteristics of multifin transistors and associated random dopant fluctuations. #2010 The Japan Society of Applied Physics
DOI: 10.1143/JJAP.49.04DC09
1. Introduction
When the gate length of a bulk metal–oxide–semiconductor field-effect transistor (MOSFET) decreases below 32 nm, the performance of the device is degraded by serious short-channel effects (SCEs). This problem has complicated technological ramifications in the semiconductor industry.1) Therefore, diverse approaches to enhancing device perform-ance have been proposed, such as the use of strain silicon,2) high-/metal gate materials,3)and MOSFETs with vertical channels.4–8) Among these promising approaches, vertical channels have attracted much attention because of their many interesting characteristics.9–12) Various studies of devices with multigate structures have been published.13) We presume that multigate devices with multifins will further enhance driving capability. However, no DC char-acteristic simulation14) of multi-gate and multi-fin devices has yet been comprehensively performed; moreover, studies of the behavior and random-dopant-induced fluctuation of their circuits are still lacking.
In this work, a coupled device-circuit simulation15–18) is performed to study the device and circuit characteristics of single- and multi-fin devices with fins of different shapes (FinFET, trigate, and quasi-planar MOSFETs). The esti-mated electrical characteristics include threshold voltage (Vth), gate capacitance (Cg), the delay time of the inverter, and the static noise margin (SNM) of a six-transistor (6T) static random access memory (SRAM). Random-dopant-induced fluctuations in the aforementioned characteristics are further discussed with respect to the different ARs. The results of this study indicate that structures with multifins and a large AR may exhibit excellent characteristics and fluctuation suppression. The accuracy of the three-dimen-sional (3D) quantum drift-diffusion device simulation performed was experimentally verified.18)
This article is organized as follows. In §2, we describe the devices and circuits of interest, and the simulation settings.
In §3, we present their DC and dynamic characteristics, including their variations. Finally, In §4, we present the conclusions drawn in this study and suggest future works. 2. Multigate and Multifin Devices and Circuits As shown in Fig. 1(a), 16-nm-gate triple-fin silicon-on-insulator (SOI) FETs are examined. Figure 1(b) shows a cross-sectional view of the devices with different ARs, and Fig. 1(c) shows the tested 6T SRAM and inverter circuit with the adopted triple-fin devices. Table I shows a summary of the specifications of the devices. The physical channel length is assumed to equal the effective channel length, and the thickness of the sidewall spacer thickness is neglected. For fair comparison, the cross-sectional area of the silicon fins in the devices of interest is fixed at 128 nm2. Additionally, the threshold voltages of the 32-nm-gate devices are initially calibrated to 200 mV for the Vth roll-off characteristics. The similarity among cross-sectional areas and Vth values ensure that the control volumes of the device channels are the same under the same operating conditions. To study random-dopant-induced fluctuations, dopants are generated randomly with AR ¼ 2, as shown in Fig. 2. A total of 379 dopants are randomly generated in an 80 40 80 nm3 cube, yielding an equivalent doping concentration of 1:48 1018cm3. The 80 40 80 nm3 cube is then partitioned into 125 subcubes of 16 8 16 nm3. The number of dopants in the cubes varies from zero to nine with an average of three. The 125 subcubes are equivalently mapped into the channel region to simulate the sensitivity of the device to the position and number of dopants. Similarly, the 125 subcubes of 11:3 11:3 16 and 8 16 16 nm3are mapped into the channel region for the trigate (AR ¼ 1) and the quasi-planar (AR ¼ 0:5) structures. In estimating circuit characteristics, since no well-estab-lished compact model of nanoscale devices is available, a coupled device-circuit simulation is adopted to capture the random-dopant-position-induced fluctuation.9,15–17) The nodal equations of the tested SRAM and inverter are formulated (by applying the current and voltage conserva-
E-mail address: [email protected]
tion laws, Kirchhoff’s current law and Kirchhoff’s voltage law) and then directly coupled to the device transport equations (in the form of a large matrix that contains both circuit and device equations), which are solved simultane-ously to obtain the circuit characteristics. The device characteristics, such as potential and current density, obtained by the 3D device simulation are utilized in the circuit simulation using circuit nodal equations. The effects of discrete dopants in the transistor on circuit characteristics are thus appropriately estimated. The physical models adopted in the 3D device transport equations were calibrated for the fabricated and measured samples to maximize accuracy.18)
3. Results and Discussion
Figures 3(a) and 3(b) show plots of the Vth roll-off characteristics for single- and triple-fin MOSFETs at differ-ent ARs, with the gate length scaled from 32 to 16 nm. The results of this study reveal that the triple-fin FinFET with AR ¼ 2 is less sensitive to the scaling of the gate length because it has a larger effective device width [Weff¼n ð2 HfinþWfinÞ], where n is the number of fins. Effective device width increases with the number or height of fins. Hence, a moderate Vth roll-off of FinFETs exhibits excellent channel controllability and high resistance to intrinsic parameter variations. Figure 4(a) shows plots of the gate capacitances of the 16-nm-gate single- and triple-fin devices. Notably, the threshold voltages of these 16-nm-gate devices (FinFET, trigate FET, and quasi-planar FET) are calibrated to 150 mV to compare their performances. The Cg of the
Tri-gate Quasi-planar 8 fin Wfin(nm) Wfin FinFET 16 VDD VOUT VIN Inverter SRAM NMOS PMOS BL VDD WL BL’ Vout1 Vout2 2 1 0.5 AR 16 11.3 H (nm) 8 11.3 Hfin Lg Hfin Wfin Drain Tox Z X y Source (c) (b) (a) AR = 1 AR = 0.5 AR = 2
Fig. 1. (Color online) (a) Schematic plot of the triple-fin MOSFET. (b) The cross-sectional plots of the three studied fin shapes are FinFET (AR ¼ 2), trigate (AR ¼ 1), and quasi-planar (AR ¼ 0:5). The parameter settings for Hfinand Wfinare listed in the inset table. (c) Inverter and SRAM are tested as
the test circuits. BL and BL0denote bit lines; WL denotes word line.
Table I. Parameters of triple-fin FinFET (AR ¼ 2), trigate (AR ¼ 1), and quasi-planar (AR ¼ 0:5) MOSFETs.
Quasi-planar Trigate FinFET
Vth,lin(V) 0.15 0.15 0.15 Vth,sat(V) 0.208 0.198 0.193 Ion(A) 2:055 105 3:126 105 4:694 105 Ioff(A) 1:672 109 1:213 109 1:101 109 DIBL 0.058 0.048 0.043 Oxide thickness (nm) 1.2 1.2 1.2 Width (nm) 16 11.3 8
Work function (eV) 4.4 4.4 4.4
Channel doping concentration (cm3) 1:48 1018 1:48 1018 1:48 1018 Body doping concentration (cm3) 1 1015 1 1015 1 1015 Source/drain doping concentration (cm3) 1:7 1019 2:5 1020 3 1020 Effective fin width (nm) 32 33.9 40 VDD(V) 1 1 1 40 nm 80 nm 80 nm FinFET 16 nm 16 nm 8 nm 9 dopants 0 dopants Concentration : 1.48 x 1018cm-3 with 375 dopants inside the cube.
Fig. 2. (Color online) Generated discrete models of FinFET, which follow a Gaussian distribution and range from 0 to 9, with an average of value is 3. Similarly, we also have models of the trigate and quasi-planar FETs.
triple-fin FinFET is 3.7 times that of the triple-fin quasi-planar device. The large Cg of the triple-fin transistor with a high AR enhances charge control; nevertheless, the increas-ed Cg affects the operational speed of the transistors. In the trade-off between Ion and Cg, the intrinsic gate delay of the transistor ( ¼ CgVDD=Ion) is calculated, as shown in Fig. 4(b). The results show that a single-fin FinFET has a 1.1 and 2.5 times smaller than those of the trigate FET and quasi-planar FET, respectively, because of its smaller Cg.
Figures 5(a) and 5(b) respectively show plots of the high-to-low transition characteristics of both single- and triple-fin inverters at various ARs, with a power supply voltage of 1 V.
The three solid lines represent the output signals of the devices with different fin structures and the dotted line represents the input signal. The high-to-low delay time (tHL) is defined as the time difference between 50% points of the input and output signals during the falling of the output signals. The insets in Figs. 5(a) and 5(b) respectively show plots of the high-to-low delay times (tHL) of the studied single- and triple-fin transistors, which are affected by the shape of the fins. As expected, both single- and triple-fin FinFET inverters have the smallest tHL for various ARs, indicating the advantages afforded by FinFET in terms of both DC and dynamic characteristics. Although the gate
Gate Length (nm) 16 20 24 28 32 Vth (V) 0.08 0.10 0.12 0.14 0.16 0.18 0.20 AR = 2 AR = 1 AR = 0.5 Single Fin (a) Gate Length (nm) 16 20 24 28 32 Vth (V) 0.08 0.10 0.12 0.14 0.16 0.18 0.20 AR = 2 AR = 1 AR = 0.5 Triple Fin (b)
Fig. 3. Plots of Vth,satroll-off characteristics for (a) single-fin and (b) triple-fin MOSFETs for different ARs.
AR 0.5 1.0 2.0 Cg (fF/ μ m) 0 2 4 6 Single-FinTriple-Fin (a) AR 0.5 1.0 2.0
Intrinsic Gate Delay
T ime (τ) (ps) 0.0 0.1 0.2 0.3 0.4 Single-Fin Triple-Fin (b)
Fig. 4. (a) Device gate capacitances and (b) intrinsic gate delay time for the studied single- and triple-fin transistors with different ARs.
Time (s) 30x10-12 33x10-12 Vout (V) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 AR =0.5 AR = 1 AR = 2 VIN Single-Fin Inverter 1.9 2 2.2 1 4.8 0.5 THL(ps) AR (a) Time (s) 30x10-12 33x10-12 Vout (V) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 Triple-Fin Inverter Delay time (tHL) T (ps) AR 1.4 2 1.7 1 2.6 0.5 HL (b)
Fig. 5. (Color online) Transient characteristics of (a) single- and (b) triple-fin inverters, where the extracted rise time, fall time, and hold time of the input signal are 2, 2, and 30 ps, respectively.
capacitance of the triple-fin transistor is larger than that of the single-fin transistor, it provides a smaller transition delay because the increase in drive current is larger. Figure 6 shows a comparison of the single-fin and triple-fin FinFETs for AR ¼ 0:5, 1, and 2 in terms of the fan-out of 4 (FO4) inverter delay. For the single-fin transistor, as shown in Fig. 6(a), delay time decreases substantially as AR is increased. Increasing the number of fins and AR enhances driving ability; allowing delay time to be further reduced, as shown in Fig. 6(b). The delay time of the triple-fin FinFET inverter is about 1.4 times smaller than that of the single-fin FinFET inverter, for example.
Figure 7 shows the random-dopant-induced threshold voltage fluctuation (Vth), and the gate capacitance fluctua-tion (Cg) of the studied triple-fin devices. Vthis derived as
Vth¼ q Cox ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi NaWdm 3LW r ; ð1Þ
where Wdm denotes the maximum depletion width, Na denotes the background doping concentration, L and W are the gate length and width, respectively, and Coxis the oxide capacitance.19) Because V
th is proportional to depletion width, the Vthof p-FET is lower than that of n-FET because the depletion depth is small. The Vth values of n- and p-type FinFETs are 1.5 and 1.9 times, respectively, smaller than that of quasi-planar structures, as shown in Fig. 7(a), suggesting that, for the same channel volume, FinFET has a more uniform surface potential. The Cg of triple-fin
FinFETs is slightly higher than triple-fin trigate and quasi-planar MOSFETs because their gate area is larger, as shown in Fig. 7(b); the inset in Fig. 7(b) shows a plot of the normalized on-state current fluctuation (Ion=Ion100%). Although the Cgof the triple-fin FinFETs is slightly higher than triple-fin trigate and quasi-planar MOSFETs, the large on-state current reduces the of triple-fin FinFETs, as shown in Fig. 8(a). Figure 8(b) shows the tHLand tLHof triple-fin device inverters. tHL and tLH are dominated by n-FET and p-FET, respectively. Thus, tHL exceeds tLH because n-FETs have a large Vth.
Figure 9(a) shows a plot of the SNM of the triple-fin device SRAM cells, where cell ratio and pull-up ratio are assumed to be unity in this determination. The relation between the device transconductance and SNM of SRAM could be expressed as SNM / ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1 Inx gm,pmos s Iax gm,nmos ; ð2Þ
where Inx is the saturation drain current of the driver transistor of SRAM and Iaxis the saturation drain current of the access transistor.20)The calculated transconductances for AR ¼ 0:5, 1, and 2 are 0.0284, 0.0536, and 0.0752 mA/V, respectively. Consequently, among the explored three structures, FinFET has the largest SNM owing to its having the largest transconductance, as shown in Fig. 9(a).
Figure 9(b) shows the random-dopant-induced SNM fluctuation (SNM) of the triple-fin device SRAM cells.
AR
0.5 1.0 2.0
FO4 Inverter Delay (t
HL ) (ps) 0 1 2 3 4 5 6 Single-Fin (a) AR 0.5 1.0 2.0
FO4 Inverter Delay (t
HL ) (ps) 0 1 2 3 4 Triple-Fin (b)
Fig. 6. Gate delay plots of the inverter with fan-out of 4 (FO4) using (a) single- and (b) triple-fin structures.
AR 0.5 1.0 2.0 σ Vth (V) 0.000 0.005 0.010 0.015 0.020 0.025 0.030 NMOS PMOS 0.0094 0.0123 2 0.0152 0.0154 1 0.018 0.0184 0.5 σVth(PMOS) σVth(NMOS) AR (a) AR 0.5 1.0 2.0 σ Cg (x 10 -3 fF) 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 3.1% 2 3.5% 1 3.6% 0.5 σIon/Ion x 100% AR (b)
Fig. 7. (a)Vthand (b)Cginduced by random dopants vs AR for the triple-fin structure. The two insets show the summarizedVthand normalized
on-state current fluctuation (Ion=Ion100%).
Triple-fin FinFETs have the smallest SNM because they have the smallest Vth. The table inset in Fig. 9(b) shows the normalized SNM.
4. Conclusions
The DC characteristics and dynamic behavior of multigate and multifin devices and circuits with different ARs, including random-dopant-induced fluctuations were simu-lated. Increasing the number of fins and AR improves device performance by suppressing SCE and moderately enhancing the current drive. The multi-fin FinFET has better SCE, driving current, timing characteristic, SNM, and fluctuation resistivity than the trigate FET and quasi-planar FET. We are currently studying the optimal number of channel fins and optimal pinch distance for manufacturing multi-fin FinFETs. The parasitic capacitances of these devices are crucial for advanced multigate and multifin transistor design. We note that devices with intrinsic channels could suppress random-dopant-induced characteristic fluctuation, and that the selection of a metal gate material with an appropriate work function is promising for adjusting threshold voltage. However, completely intrinsic channels may encounter a pronounced short-channel effect, such as punch-through, and additional processes are required to integrate a selected metal gate material. With this consideration, the use of a device with doped channels is still one of the potential solutions to adjusting threshold voltage.21,22) Thus, the
adopted channel doping concentration in this work is empirically assumed to be 1:48 1018cm3 to evaluate the effect of random channel doping on the characteristics of the SOI-based FinFET and tri-gate and quasi-planar structures. Nevertheless, we presume that more studies on choosing metal gate materials and optimizing channel doping are necessary for the further scaling of devices. Acknowledgments
This work was supported in part by the National Science Council (NSC), Taiwan under contract NSC-97-2221-E-009-154-MY2.
1) K. Natori, T. Shimizu, and T. Ikenobe:Jpn. J. Appl. Phys. 42 (2003) 2063. 2) S. Saurabh and M. J. Kumar:Jpn. J. Appl. Phys. 48 (2009) 064503. 3) M. Sato, T. Aoyama, Y. Nara, and Y. Ohji:Jpn. J. Appl. Phys. 48 (2009)
04C002.
4) K. S. Mun, J.-H. Kim, T. W. Kim, and K. D. Kwack:Jpn. J. Appl. Phys. 46(2007) 7237.
5) N. Lindert, L. Chang, Y.-K. Choi, E. H. Anderson, W.-C. Lee, T.-J. King, J. Bokor, and C. Hu:IEEE Electron Device Lett. 22 (2001) 487. 6) J.-P. Colinge:Solid-State Electron. 48 (2004) 897.
7) K. Okuyama, A. Sugimura, and H. Sunami:Jpn. J. Appl. Phys. 47 (2008) 2407.
8) M. Yoshida, J.-R. Kahng, J.-S. Moon, K.-H. Jung, K. Kim, H. Sung, C. Lee, C.-K. Kim, W. Yang, and D. Park:Jpn. J. Appl. Phys. 47 (2008) 2672.
9) H.-W. Cheng, C.-H. Hwang, and Y. Li: Int. J. Electr. Eng. 16 (2009) 301. Vout1 (V) 0.0 0.2 0.4 0.6 0.8 1.0 Vout2 (V) 0.0 0.2 0.4 0.6 0.8 1.0 AR = 2 AR = 1 AR = 0.5 Triple-Fin SRAM 163 2 145 1 129 0.5 SNM (mV) AR (a) AR 0.5 1.0 2.0 SNM fluctuation (mV) 0 2 4 6 8 10 12 14 16 18 5.7% 2 10.3% 1 18.4% 0.5 σSNM/SNM (%) AR (b)
Fig. 9. (Color online) (a) Plots of static transfer characteristics for AR ¼ 2, 1, and 0.5; SNM is calculated from the length of the side of a square having the longest diagonal. (b) SNM fluctuations of the examined SRAM with AR ¼ 2, 1, and 0.5. The normalizedSNM(SNM=SNM 100%) is summarized in
the inset of (b). AR 0.5 1.0 2.0 στ (s) 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 (a) AR 0.5 1.0 2.0
Delay Time Fluctuation (ps) 0.00
0.01 0.02 0.03 0.04 0.05 0.06 σtHL σtLH (b)
Fig. 8. (a) of triple-fin transistors. (b) tHLandtLHvalues of the tested inverter with AR ¼ 2, 1, and 0.5.
10) T. Nagumo and T. Hiramoto:Jpn. J. Appl. Phys. 44 (2005) 50. 11) Y. Liu, E. Sugimata, K. Ishii, M. Masahara, K. Endo, T. Matsukawa, H.
Yamauchi, S. O’uchi, and E. Suzuki:Jpn. J. Appl. Phys. 45 (2006) 3084. 12) S. M. Kim, E. J. Yoon, H. J. Jo, M. Li, C. W. Oh, S. Y. Lee, K. H. Yeo, M. S. Kim, S. H. Kim, D. U. Choe, J. D. Choe, S. D. Suk, D.-W. Kim, D. Park, K. Kim, and B.-I. Ryu: IEDM Tech. Dig., 2004, p. 639. 13) J. P. Colinge: FinFETs and Other Multi-Gate Transistors, (Springer,
Berlin, 2007) Chap. 2, p. 50.
14) H. Shang, L. Chang, X. Wang, M. Rooks, Y. Zhang, B. To, K. Babich, G. Totir, Y. Sun, E. Kiewra, M. Ieong, and W. Haensch: VLSI Technology Dig. Tech. Pap., 2006, p. 54.
15) Y. Li, C.-H. Hwang, and H.-W. Cheng:Jpn. J. Appl. Phys. 48 (2009) 04C051.
16) Y. Li and C.-H. Hwang:Jpn. J. Appl. Phys. 47 (2008) 2580.
17) Y. Li and S.-M. Yu:Jpn. J. Appl. Phys. 45 (2006) 6860.
18) Y. Li, S.-M. Yu, J.-R. Hwang, and F.-L. Yang:IEEE Trans. Electron Devices 55 (2008) 1449.
19) Y. Taur and T. H. Ning: Fundamentals of Modern VLSI Devices (Cambridge University Press, Cambridge, U.K., 1998).
20) A. J. Bhavnagarwala, X. Tang, and J. D. Meindl:IEEE J. Solid-State Circuits 36 (2001) 658.
21) K. Endo, Y. Ishikawa, Y. Liu, M. Masahara, T. Matsukawa, S.-I. O’uchi, K. Ishii, H. Yamauchi, J. Tsukada, and E. Suzuki:IEEE Electron Device Lett. 28 (2007) 1123.
22) T. Matsukawa, K. Endo, Y. Ishikawa, H. Yamauchi, S. O’uchi, Y. Liu, J. Tsukada, K. Ishii, K. Sakamoto, E. Suzuki, and M. Masahara:IEEE Electron Device Lett. 30 (2009) 407.
