Statistical device simulation of physical and electrical characteristic fluctuations in 16-nm-gate high-kappa/metal gate MOSFETs in the presence of random discrete dopants and random interface traps

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Statistical device simulation of physical and electrical characteristic ﬂuctuations

in 16-nm-gate high-

j

/metal gate MOSFETs in the presence of random discrete

dopants and random interface traps

Yiming Li

⇑

, Hui-Wen Cheng

Parallel and Scientiﬁc Computing Laboratory, Department of Electrical and Computer Engineering, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu 300, Taiwan

a r t i c l e

i n f o

Article history:

Available online 26 June 2012 Keywords:

Random discrete dopant Random interface trap DC/AC ﬂuctuations Random effect High-j/metal gate 16-nm-gate MOSFETs

3D device simulation

a b s t r a c t

We estimate the effects of random discrete dopants (RDs) and random interface traps (ITs) on physical and electrical characteristic ﬂuctuations of 16-nm-gate high-j/metal gate (HKMG) metal–oxide-semi-conductor ﬁeld effect transistors (MOSFETs). Two-dimensional (2D) random ITs at the hafnium oxide (HfO2)/silicon interface and 3D RDs inside the silicon channel of the 16-nm-gate HKMG MOSFETs are

simultaneously incorporated into an experimentally validated 3D device simulation to quantify the RDs-and-ITs-fluctuated characteristics. The random effect of the combined RDs and ITs induces rather different fluctuation in the threshold voltage, the on-/off-state current, and the gate capacitance in the 16-nm-gate HKMG MOSFETs. The surface potential, DC and AC characteristic fluctuations are affected to different extents by the random combinatorial RDs and ITs. Nonlinearly correlated RDs and ITs violate the statistical assumption of independent identical distributions between the RDs- and ITs-induced ran-dom variables. Consequently, for the studied 16-nm-gate HKMG N-MOSFETs, the threshold voltage fluc-tuation induced by the combined RDs and ITs is 11% less than their statistical sum due to local interaction of surface potentials resulting from the RDs and ITs simultaneously. Similarly, it is about 8.9% for the P-MOSFET devices. Depending upon random position and number of the combined RDs and ITs, overesti-mation or underestioveresti-mation between the statistical sum of variances and the 3D device simulation is also observed for the drain current and the gate capacitance.

1. Introduction

Complementary metal oxide semiconductor (CMOS) device technology scaling and performance improvement follow the Moore’s law[1]in the last four decades. Nowadays, continuously pursuing Moore’s law requires not only overcoming a variety of fabrication challenges but also suppressing systematic variation and random effects [2,3]. Random dopant ﬂuctuation (RDF), as one of known major intrinsic parameter ﬂuctuations, complicates device scaling and design [4–11] in sub-65-nm CMOS devices era. High-

j

/metal-gate (HKMG) technology has been a key way to reduce intrinsic parameter ﬂuctuation and leakage current for sub-45-nm technology nodes. However, depending on different fabrication process, the HKMG approach may associate with ran-dom interface traps (ITs) at the high-

j

/silicon interface[12–17]. This additional random source may degrade device characteristic; thus, except recent studies on RDF, computational simulation of device variability induced by the random ITs was reported using a simple one-dimensional (1D) model of ITs for sub-65-nm CMOS

devices[16]and a 2D model of ITs for 16-nm-gate HKMG devices

[17]. Unfortunately, local interaction of the combined RDs and ITs

[18,19]and its impact on physical and electrical characteristic ﬂuc-tuation of 16-nm-gate HKMG planar CMOS devices have not been discussed yet.

In this work, we statistically simulate the interaction of com-bined random ITs and RDs of 16-nm-gate metal–oxide-semiconduc-tor ﬁeld effect transismetal–oxide-semiconduc-tors (MOSFETs) using an experimentally calibrated 3D device simulation[4]. In contrast to 1D interface trap’s model, a 2D ITs’ model at HfO2/silicon interface is established and

incorporated into 3D device simulation, which is solved with 3D RDs in the device channel at the same time. To examine the insights of the combined RDs and ITs effects, quantum mechanical transport simulation is performed and compared with experimental data by solving a set of calibrated 3D density-gradient equation coupling with Poisson equation as well as electron–hole current continuity equations[4,20,21]. This analyzing technique enables us to explore both the individual and coupling effects of randomly existing RD and ITs on characteristic including fluctuations of the threshold voltage, the on-/off-state current, and the gate capacitance in a uni-fied way. The RDs-, ITs-, and the combined RDs and ITs (denoted as ‘‘RDs and ITS’’)-fluctuated DC/AC characteristics are quite different

http://dx.doi.org/10.1016/j.sse.2012.05.017

⇑Corresponding author.

E-mail address:[email protected](Y. Li).

Contents lists available atSciVerse ScienceDirect

Solid-State Electronics

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statistical assumption of independent identical distributions for the RDs-induced and ITs-induced random threshold voltages does not hold at all. Similarly, the impact of combined RDs and ITs on the

r

Ion,

r

Ioff, and

r

CGis estimated and discussed.

This article is organized as follows. In Section2, we describe the simulation settings for RDs-, ITs-, and ‘‘RDs and ITs’’-induced char-acteristic fluctuations. In Section3, we discuss the findings of this study for the ‘‘RDs and ITs’’-fluctuated 16-nm-gate CMOS devices. Finally, we draw conclusions and suggest future work.

2. The simulation technique of combined RDs and ITs

According to ITRS roadmap[22], the validated nominal device characteristic of studied 16-nm-gate HKMG MOSFETs is for low operating power. Using an experimentally quantiﬁed 3D device simulation [4], we calibrate the threshold voltage of the 16-nm-gate N- and P-MOSFETs to 250 mV. The devices we examined are the 16-nm titanium–nitride (TiN) gate planar MOSFETs (the device width is equal to the gate length of 16 nm which is designed for the most critical assessment) with amorphous-based TiN/HfO2

gate stack with an effective oxide thickness (EOT) of 0.8 nm, as shown inFig. 1a. For the RDF simulation, we mainly follow the detail of RDF simulation reported in our recent work [3–7]. As shown inFig. 1a, the RDs in 3D device channel region are statisti-cally incorporated into device simulation running on our parallel computing system [20]. A procedure for the RDF simulation is shown inFig. 1b. Note that, for the best accuracy of our analyzing technique, the implemented statistical device simulation technique for estimating characteristic ﬂuctuation has been exper-imentally validated with silicon data for sub-20-nm devices in our earlier work[4], where the RDs-ﬂuctuated mobility was validated with experimentally measured current–voltage (I–V) data.

For the simulation of ITs ﬂuctuation (ITF), we ﬁrst generate 753 acceptor-like traps marked as orange color in a large 2D plane, as shown inFig. 1a, where the interface trap’s concentration in the large plane is around 1.5 1012_cm2_{(This value is mainly for}

gen-erating the number of interface traps which is not equal to the effective entire density of interface traps.) and the total number of generated traps follows the Poisson distribution. Then, the sta-tistically random generated large 2D plane is partitioned into many sub-planes, where the number of interface traps in the sub-planes varies from 1 to 8 and the average number of interface traps is 4, as shown in the plot of bar chart with orange color. The energy of each interface trap on a sub-plane is random assigned [12– 14,16,17,23]. Thus, each interface trap’s density is estimated according to its randomly assigned energy. Consequently, the en-tire density of interface traps (Dit) varies randomly in the range

of [1 1010eV1_cm2_{, 1 10}12

eV1_cm2_{] which almost}

coin-cides with our experimental characterization for sub-20-nm

3. Results and discussion

Fig. 2shows the ‘‘RDs and ITs’’-ﬂuctuated drain current–gate voltage (ID–VG) curves for the studied 16-nm-gate N- and

P-MOS-FETs, where the solid lines show the nominal ID–VGcurves, the bars

are the results of ‘‘RDs and ITs’’-ﬂuctuated devices. We note that, as shown inFig. 2, the normalized on- and off-state currents (

r

Ionand

r

Ioff) of the N-MOSFETs are 9.75% and 90.97%. For the P-MOSFETs,

r

Ionand

r

Ioffare 17.3% and 76.93%, respectively. The ﬂuctuation of

drain current is minimized when the gate voltage is increased. It was reported that the screening effect can suppress the RDF for de-vices under strong inversion [10,11]. The magnitude of

r

Ion

in-duced by the ‘‘RDs and ITs’’ still has 17% because the ITs locating at HfO2/silicon interface may destroy the screening effect. If only

ITs appear at HfO2/silicon interface, the Vthis simply raised[24];

however, the concurrently existing RDs inside the device channel complicate the Vthas well as the ID–VG, as shown inFig. 2. The

sta-tistically simulated ID–VGcurves enable us to extract the

r

Vth,

in-duced by different sources of ﬂuctuations. Table 1 summarizes the RDs-, ITs- and the ‘‘RDs and ITs’’-induced threshold voltage ﬂuctuations of the studied 16-nm-gate N- and P-MOSFETs. The de-vice exhibits

r

Vth,RDs= 43 mV,

r

Vth,ITs= 26.3 mV and

r

Vth,‘‘RDs and ITs’’= 45.4 mV. We note

r

Vth,‘‘RDs and ITs’’= 45.4 mV is smaller than

the result calculated by (

r

2_V

th,RDs+

r

2Vth,ITs)0.5= 50.4 mV in which

the random variables follow statistically independent identical dis-tribution (iid) is assumed. However, the iid assumption on the ran-dom variables of Vth,RDsand Vth,ITsis not always true owing to local

interaction of surface potentials between RDs and ITs concurrently existing in the surface/channel region of the N-MOSFETs. The rela-tive error between the statistical sum of Vth’s variances and the 3D

simulation is calculated by the expression: Error = ((

r

2_V th,RDs+

r

2_V

th,ITs)0.5

r

Vth,‘‘RDs and ITs’’)/

r

Vth,‘‘RDs and ITs’’ 100%. It is about 11%

overestimation compared with the

r

Vth,‘‘RDs and ITs’’ of the

N-MOSFETs; similarly, for the studied 16 nm P-MOSFETs,

r

Vth,‘‘RDs and ITs’’= 45.1 mV is smaller than the statistically sum

(

r

2

Vth,RDs+

r

2Vth,ITs)0.5= 49.1 mV. The

r

Ion and

r

Ioff induced by

RDs, ITs, and ‘‘RDs and ITs’’, respectively, for the studied CMOS devices are listed inTable 1.

Owing to sizeable threshold voltage ﬂuctuation, the statistical sums of the variances of two random variables induced by RDs and ITs disclose signiﬁcant errors, compared with the 3D device simulation together with the combined RDs and ITs. The large rel-ative errors of

r

Ionand

r

Ioffdirect to the random number and

posi-tion effects of combined RD and ITs. Therefore, to understand the inﬂuence of local interaction of surface potentials, we further examine the RDs-, ITs-, and ‘‘RDs and ITs’’-induced surface poten-tials and the conducting current densities, respectively. The off-state (VD= 0.8 V and VG= 0 V) potential distributions and the

on-state (VD= VG= 0.8 V) current densities for the N-MOSFETs with

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RDs and ITs are shown inFig. 3a–c, respectively. Inside the silicon channel (just below the channel surface), there are 8 RDs (blue

discrete dopants) and the circled RD near channel surface ﬂuctu-ates the surface potential, as shown in the upper left plot of

012 34 5 67 8

(a)

(b)

(c)

Fig. 1. (a) The two sources of randomness (orange dots are interface traps and blue dots are discrete dopants) and statistical 3D device simulation settings for the ﬂuctuations of random ITs and RDs. We ﬁrst generate 753 acceptor-like traps in a large plane for N-MOSFET devices, where the interface trap’s concentration in the plane is around 1.5 1012

cm2

and the total number of generated interface traps follows the Poisson distribution. The energy of each interface trap on the plane is independently assigned according to the distribution of its density. Then, the entire plane is partitioned into sub-planes (size: 16 nm 16 nm), where the number of interface traps in each sub-plane may vary from 1 to 8 and the average number is 4. Thus, the effective density of interface traps (Dit) is in an order of 1011eV1cm2. For the settings of discrete dopants, impurities are randomly generated and distributed in (96 nm)3

cube with the average concentration of 1.5 1018

cm3_{. There will be 1327 discrete dopants within the cube} and the number of discrete dopants varies from 0 to 14 (the average number is six) for all 216 sub-cubes. The size of each sub-cube is (16 nm)3

. The total cubes and sub-planes are then mapped into device’s 3D channel and 2D surface for RDs and ITs’ position and number simulations. (b) and (c) are the procedures for setting the RDs and ITs in the statistical device simulation.

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Fig. 3a, where the absolute value of local spike is 0.4492 eV (i.e. |potential(at the RD-induced peak) potential(at the source end; x = 0 nm)|

= |0.0941(0.5433)| = 0.4492 eV). The associated low current density is found around the local spike of potential barrier as shown in the lower right plot ofFig. 3a. The surface potential ﬂuc-tuated by 4 ITs (orange interface traps), as shown in the upper left plot ofFig. 3b, results in an absolute value of spike of 0.4372 eV which is larger than that of RDs because all ITs locating at HfO2

/sil-icon interface. The conducting current paths from the source end (S) to the drain end (D) are obstructed by the existing ITs, as shown in the lower right plot ofFig. 3b. By considering the same location of the RDs and ITs above, as shown in the lower left pattern of

Fig. 3c, the device possesses rather different potential profile and current density induced by the combined 8 RDs and 4 ITs. The local interaction effect of the combined RDs and ITs on the potential pro-file has an enhanced peak of localized spikes. The 3D simulated absolute values of the local barrier’s peak are 0.4627 eV and 0.4611 eV induced by the combined RDs and ITs, as shown in the upper left plot of Fig. 3c, where the potential profile has about 8.9% enhancement; cutting from S to D, 1D potential profiles pass-ing through the peak of each spike with respect to the aforemen-tioned three cases are shown in the upper right plots of Fig. 3a–c. Note the coverage range of localized spikes in the upper right plot ofFig. 3c is broadened owing to nonlinear potentials’ interac-tion resulting from the combined RDs and ITs. Consequently, the vortex-like on-state current density spreads apart from S to D, as shown in the lower right plot ofFig. 3c. This investigation shows

owing to the increase of space charges, as shown in the com-bined h20_{i and h3}0_{i(denoted as h2}0_{i + h3}0_{i). It implies that the}

cou-pling effect induced by RD and RD is larger than the interaction between RD and IT. Besides, the calculated Vthof the cases h10i +

h20_{i and h2}0_{i + h3}0_{i are 0.312 and 0.362 V which are different from}

their statistical sum: the case of h10_{i and h2}0_{i is:} _(0.1962₊

0.3 042₎0.5_{= 0.362 V and the case of h2}0_{i and h3}0_{i is (0.304}2₊

0.29 82₎0.5_{= 0.426 V. It conﬁrms that the ﬂuctuation sources should}

be considered at the same time in order to get proper ﬂuctuation estimations.

Fig. 5a shows the ‘‘RDs and ITs’’ ﬂuctuated Ion–Ioffcharacteristics

of the N- and P-MOSFETs, respectively. Each symbol indicates the result induced by the combined RDs and ITs. The inset log–log plot shows the scatter relationship for the N- and P-MOSFETs. We con-sider the N-MOSFETs, as shown inFig. 5a, to examine the random number and position effects, where orange dots are ITs and blue dots are RDs. Among all simulation cases, the randomly selected two cases of the ‘‘RDs and ITs’’ with similar Ioffbut different Ion

are shown in Fig. 5b and c. The large random number of the ‘‘RDs and ITs’’ increases the threshold voltage and thus reduces the level of drain current density as shown inFig. 5b, b’ and b’’. 5 RDs inFigs. 5b and 6RDs inFig. 5c are deep into channels which contribute insigniﬁcant ﬂuctuation to the surface potentials. In contrast with RDs, the ITs locating at HfO2/silicon interface alter

the local spike of surface potential; in particular, for ITs near the source end, as shown inFig. 5b’ and 5c’. There are 6 ITs in the case ofFig. 5b, but the impact of most ITs near the drain end on surface potential is dominated and suppressed except those near the source end.Fig. 5b’ discloses that fluctuation of surface potential is suppressed when these ITs are away from S of the channel. Nota-bly, the ITs near the drain end do not have significant potential fluctuations owing to applied high drain bias. On the other hand, ITs locating near S may locally capture the conducting electrons

the 16 nm N- and P-MOSFETs, where the solid lines show the nominal case of ID–VG curves, the bars are the RDs and ITs ﬂuctuated results. The normalizedrIonandrIoff of the N-MOSFETs are 9.75% and 90.97%. For the P-MOSFETs,rIonandrIoffare 17.3% and 76.93%, respectively. The ﬂuctuation of drain current is reduced when the gate bias is increased.

Table 1

Summary of various ﬂuctuations of the Vth, the Ion, and the Ioffinduced by RDs, ITs, and ‘‘RDs and ITs’’, respectively, for the studied 16-nm-gate HKMG N- and P-MOSFETs. The statistical sums of the variances of two random variables induced by RDs and ITs show different errors, compared with the results of the 3D device simulation with combined RDs and ITs. The relative error between the statistical sums of the variances of the Vth and the 3D simulation of the Vth is calculated by the expression: Error = ((r2_V

th,RDs+r2Vth,ITs)0.5rVth,‘‘RDs and ITs’’)/rVth,‘‘RDs and ITs’’ 100%. Similarly, we can calculate the relative errors of the on- and off-state currents. The unit ofrVthis mV and the unit ofrIonandrIoffis A.

Vth,RDs Vth,ITs (r2Vth,RDs+r2Vth,ITs)0.5 rVth,‘‘RDs and ITs’’ Error (%)

N-MOSFETs 43 26.3 50.4 45.4 +11

P-MOSFETs 41 27.1 49.1 45.1 +8.9

rIon,RDs rIon,ITs (r2Ion,RDs+r2Ion,ITs)0.5 rIon,‘‘RDs and ITs’’ Error (%) N-MOSFETs 7.51 107 6.99 107 1.03 106 1.09 106 2.8 P-MOSFETs 3.75 107 5.29 107 6.48 107 4.42 107 +46.6

rIoff,RDs rIoff,ITs (r2Ioff,RDs+r2Ioff,ITs)0.5 rIoff,‘‘RDs and ITs’’ Error (%)

N-MOSFETs 2.94 109 _{7.81 10}10 _{3.04 10}9 _{1.83 10}9 _+66.1

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from S to D and results in a repulsive barrier well around ITs, as shown in the areas of local spikes inFig. 5b’ and c’. The electron is forced to change its conducting path because it cannot transport from S to D directly depending on those ITs near S owing to locally weakened energy and altered velocity, as shown in the areas of low-level current densities inFig. 5b’’ and c’’. Consequently, the cases ofFig. 5b and c have similar Ioff, as shown inFig. 5b’ and c’

but different Ion, as shown inFig. 5b’’ and c’’. The nonlinear coupled

capturing and obstructing effects induced by the ‘‘RD and ITs’’ have clearly shown inFig. 3c. Similarly,Fig. 5c and d are two cases of the ‘‘RDs and ITs’’ with similar Ion but different Ioff. These two cases

have the same number of the ‘‘RDs and ITs’’ (they have 1 ITs and 6 RDs), but their Ioffis different owing to random position of ITs.

The device with ITs near the source end, as shown inFig. 5c, has relatively stronger local spike of potential compared with the case shown inFig. 5d. For the on-state current, the conducting areas are very similar, as shown inFig. 5c’’ and d’’; therefore,Fig. 5c and d have similar Ion. In summary, the random position effect of the

‘‘RDs and ITs’’ induces rather different ﬂuctuation in spite of the same number of the ‘‘RDs and ITs’’. All plots of the off-state poten-tial and the on-state current density are extracted at the channel

(a)

(b)

(c)

Fig. 3. The off-state (VD= 0.8 V and VG= 0 V) potential distributions and the on-state (VD= VG= 0.8 V) current densities of the channel surface for the simulated 16-nm-gate devices with only RDs, only ITs, and combined RD and ITS, respectively. As shown in the lower left plots, the devices are ﬂuctuated by (a) 8 RDs locating inside the silicon channel below the channel surface, (b) 4 random ITs at HfO2/silicon interface, (c) and 12 combined RDs and ITs simultaneously. As shown in the upper left plots, the local interactions of surface potentials resulting from the RDs, ITs, and the combined RDs and ITs exhibit different band proﬁle, measuring from the source (S) to drain (D), and current density, as shown in the right plots. In particular, the combined RDs and ITs complicate the local spikes of the surface potentials.

(a)

(b)

Fig. 4. (a) The schematics of channel and (b) corresponding potentials ﬂuctuated by 1 IT at the interface (the case h10_{i), 1 RD located 2 (the case h2}0_{i) and 4 (the} case h30_{i) nm below the surface, the combined case of h1}0_{i + h2}0_{i, and the case} of h20_{i + h3}0_{i, respectively. All surface potentials are extracted from the source end to} the drain end, where the RDs and/or IT are locating at x = 5 nm.

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surface. The

r

Ionand

r

Ioffof the N- and P-MOSFETs induced by the

RDs, ITs and ‘‘RDs and ITs’’ are summarized inTable 1, respectively, including their statistical sums of variances.

For the AC characteristic ﬂuctuation, the gate capacitance– voltage (CG–VG) of the RDs-, ITs-, and ‘‘RDs and ITs’’-ﬂuctuated

16-nm-gate N-MOSFETs are shown inFig. 6a, d and g, where the red lines show the nominal capacitances, the gray dashed lines are the fluctuated results, and the solid lines with symbols are the averaged values of all fluctuated cases. For the RDs-induced CGfluctuation, as shown inFig. 6a, the lateral shift and the change

of shape are observed for the CG–VGcurves; the shape variation of

the CGcurves is resulted from the placement of RDs in the channel

depletion region. The lateral shift of the CGcurves is due to Vth’s

variation.Fig. 6b and c shows the CGcurves and associated

varia-tions for the devices with the number of RDs less than or equal to the averaged number 6 and for the devices with the number

of RDs more than 6. The RDs-induced CG ﬂuctuations are

sup-pressed for the devices under high gate bias. As shown inFig. 6c, the devices with the number of RDs more than 6 have signiﬁcant CGﬂuctuation in the linear region. For the impact of only ITF, the

lateral shift of the CGcurves is owing to random number effect of

ITs. The slight change of CG’s shape could be attributed to different

position effect of ITs at HfO2/silicon interface, as shown inFig. 6d.

Below the linear region, both the cases inFig. 6e and f have mini-mized CG’s ﬂuctuation which is different from the inﬂuence of RDs;

however, the CG’s ﬂuctuation appear when the devices enter strong

inversion because the ITs capture the induced electrons, destroyed the formulated inversion layers, and weaken the screening effect, where the large number of ITs is severe, compared with the cases of ITs less than or equal to the averaged number 4. Not shown here, the asymmetric shape variation of CGcurves is owing to random

ITs near the source or drain sides. For the local interaction effect

(a)

(b)

(c)

(d)

(d’)

(c’)

(b’)

(b’’)

(c’’)

(d’’)

Fig. 5. (a) Plot of Ioffversus Ionof the simulated N- and P-MOSFETs, where each symbol indicates the result induced by the combined RDs and ITs. The inset is the log–log plot to show the scatter relationship. Without loss of generality, we consider the N-MOSFETs in examining the random number and position effects, where orange dots are ITs and blue dots are RDs. (b) and (c) represent two cases of RDs and ITs with similar Ioffbut different Ion. (c) and (d) are two cases of RDs and ITs with similar Ionbut different Ioff. The corresponding off-state potentials and on-state current densities of (b), (c), and (d) are shown in (b’), (c’), (d’) and (b’), (c’), (d’), respectively. All plots of the off-state potential and the on-state current density are extracted at the channel surface.

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of the combined RDs and ITs, the signiﬁcantly lateral shift and change of shape for the curves of CG–VGare shown inFig. 6g. The

combined RDs and ITs affect the CGcurves nonlinearly, as shown

inFig. 6h and i, which should be modeled for nano-CMOS circuit simulation. The various ﬂuctuations of gate capacitance obtained from Fig. 6a–i with respect to different gate bias are listed in

Fig. 6j. Result shows that the device operates under the saturation region may suffer from the less gate capacitance ﬂuctuation, where the screening effect of inversion layer of device screens the ﬂuctu-ation of gate capacitance for the cases of RDF. However, for the cases of ITF, the

r

CGkeeps similar values in both the low and high

ﬁelds which can not be screened due to ITs are right at the HfO2/

silicon interface. The

r

CGinduced by the ‘‘RDs and ITs’’ is obviously

dominated by ITs under the saturation operation.

Both the DC and AC characteristic fluctuations indicate the im-pact of ITs on device variability is significant. In order to study the fluctuation of devices with low Dit, a tenth of originally studied Dit

is performed.Fig. 7shows the

r

Vthinduced by the RDs, ITs, and the

combined RDs and ITs, where the interface traps have high (the originally studied one) and low Dit. This preliminary study shows

that the magnitude of ﬂuctuation is mainly dominated by RDs, even devices are with low Dit. Therefore, reducing channel doping

level plays a crucial role for device’s ﬂuctuation suppression in the studied 16-nm-gate CMOS devices.

4. Conclusions

In summary, we have explored the local interaction of surface potentials between the combined RDs and ITs for the 16-nm-gate CMOS devices. Due to randomly positioned charges resulting from the RDs and ITs in the 16-nm-gate CMOS devices, the ‘‘RDs and ITs’’ has an enlarged peak of localized spikes compared with the results of individual RDs and ITs, respectively. It implies that the interac-tion and coupling effects should be considered simultaneously for the RDF and ITF in emerging HKMG CMOS devices. Notably, ﬂuctu-ations among RDs, ITs, and random work function of nanosized metal grains are currently under examination.

Acknowledgements

This work was supported in part by National Science Council (NSC), Taiwan under Contract Nos. NSC-99-2221-E-009-175 and NSC-100-2221-E-009-018 and by tsmc, Hsinchu, Taiwan under a 2011–2012 grant.

References

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technology variation. IEEE Trans Electron Dev 2011;58(8):2197–208. [3] Li Y, Hwang C-H, Li T-Y, Han M-H. Process–variation effect, metal-gate

work-function ﬂuctuation, and random-dopant ﬂuctuation in emerging CMOS technologies. IEEE Trans Electron Dev 2010;57(2):437–47.

(j)

(i)

(h)

(g)

(d)

(e)

(f)

(c)

(b)

(a)

Fig. 6. Plots of gate capacitance–voltage (CG–VG) of the RDs-, ITs- and ‘‘RDs and ITs’’-fluctuated 16-nm N-MOSFETs are shown in (a), (d), and (g), respectively, where the red lines are the nominal cases with respect to different settings and the black lines are the averaged results accordingly. (b) is the plot for the cases with the number of RDs is less than or equal to the average number 4 and (c) is the plot for the number of RDs is more than the average number 4. Similarly, (e) and (f) are for ITs, and (h) and (i) are for the combined RDs and ITs. (j) plot of the gate capacitance fluctuation of the simulated N-MOSFETs induced by RDs, ITs and combined RDs and ITs under VG= 0.4 V and 0.8 V. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)

Fig. 7. TherVthinduced by the combined ITs and RDs, where the interface traps have high and low Dit.

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