Design and analysis of a millimeter-wave direct injection-locked frequency divider with large frequency locking range

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Design and Analysis of a Millimeter-Wave Direct

Injection-Locked Frequency Divider With

Large Frequency Locking Range

Chung-Yu Wu, Fellow, IEEE, and Chi-Yao Yu

Abstract—In this paper, direct injection-locked frequency

di-viders (ILFDs), which operate in the millimeter-wave (MMW) band, are analyzed. An analytically equivalent model of the direct ILFDs is developed, and important design guidelines for a large frequency locking range are obtained from it. These guidelines are: 1) maximize the quality factor of the passive load; 2) maintain low output amplitude; and 3) increase the dc overdrive voltage of the input device. A direct ILFD without varactors is designed and fabricated using a 0.13- m bulk CMOS process to verify the developed model and design guidelines. A pMOS current source is used to restrict the output amplitude and to increase the dc overdrive voltage of the input device to achieve a large frequency locking range. The size of the input device is only 3.6 m/0.12 m and the measured frequency locking range is 13.6% at 70 GHz with a power consumption of 4.4 mW from a supply voltage of 1 V. In short, the proposed divider has the potential to be integrated into an MMW phase-locked loop system.

Index Terms—Frequency locking range, injection-locked

fre-quency divider (ILFD), millimeter-wave (MMW) integrated CMOS circuit, phase-locked loop (PLL), 0.13- m bulk CMOS technology.

I. INTRODUCTION

W

ITH RAPID advances in CMOS technology, the CMOS circuit operating in the millimeter-wave (MMW) band has attracted increasing interest and research [1]–[16]. Since fre-quencies around 60 GHz have been opened for unlicensed use in the U.S. and Japan, it seems possible that such circuits can be used in the front-end systems of gigabits/s point-to-point links, wireless local area networks, high data-rate wireless personal area networks, and radars.

In general, phase-locked loops (PLLs) are extensively used in CMOS RF front-end systems as frequency synthesizers or clock sources to generate local oscillating signals. In an MMW PLL, the main blocks with the highest operating frequency are typically the voltage-controlled oscillator (VCO) and the frequency divider. More specifically, the main design issues of an MMW VCO concern the oscillating frequency tuning range, phase noise, power consumption, and output power level [7]–[10]. Most of these degrade as the input capacitance of

Manuscript received February 20, 2007; revised May 22, 2007. This work was supported in part by National Nano Device Laboratories, the Ansoft Corpora-tion, the United Microelectronic CorporaCorpora-tion, and the National Science Council, Taiwan, R.O.C., under Grant NSC95-2215-E-009-023.

The authors are with the Institute of Electronic Engineering, Na-tional Chiao-Tung University, Hsinchu, 300 Taiwan, R.O.C. (e-mail: p9111846@alab.ee.nctu.edu.tw).

Digital Object Identifier 10.1109/TMTT.2007.902067

the next stage, which may be a frequency divider, increases. Therefore, the reduction of the input capacitance of the divider becomes very important as the operating frequency to the MMW band increases. In addition, the wide operating fre-quency range of the divider is also important in the MMW band in order to cover the inevitable shift of the center operating frequency caused by the process variations in the small values of integrated spiral inductance or parasitic capacitance. A small operating frequency range will severely reduce the reliability of the MMW PLL. Therefore, the main design challenge facing the MMW divider designers is to reduce input capacitance while maintaining a wide operating frequency range. As in other integrated CMOS RF circuits, power consumption and noise performance are also important in divider design.

In comparison with flip-flop-based static frequency dividers [11], injection-locked frequency dividers (ILFDs) [12]–[14] generally have lower power consumption and higher frequency capability in bulk CMOS technologies. However, ILFDs usu-ally suffer from narrow locking ranges. This limitation can be significantly improved by proper structure selection and correct design methodology, as will be shown in this paper. As the scaling down of CMOS technology toward a 90- or 65-nm node, ILFDs provide a good low-power design choice besides the static dividers in the MMW PLL integration [16].

A conventional LC-based ILFD is shown in Fig. 1(a). The input stage is used to provide both an input signal path and a dc bias path. Thus, is typically large, resulting in a large input capacitance. Moreover, the input signal is significantly de-graded by the parasitic capacitor in Fig. 1(a). By using a peaking inductor between the drain terminal of and the ground, this problem can be reduced [18]; however, this strategy requires a greater chip area. Moreover, the Miller divider pro-posed in [15] faces the same problems of a large input capaci-tance and the need for a peaking inductor.

The 50-GHz direct ILFD in [12], as shown in Fig. 1(b), provides a solution for MMW operation with a low input capacitance, but it suffers from a narrow frequency locking range. Therefore, the passive loads of a direct ILFD in another study [14] are optimized to increase the frequency locking range. However, the power consumed by the resulting ILFD is relatively large, probably because the devices involved are also large and a current-limiting device is absent. Varactors are used at the output nodes in another ILFD [13] to increase the locking range. However, with a PLL system design, the need to synchronize the controlling voltages between the varactors in both the VCO and divider significantly increases design complexity.

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1650 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 55, NO. 8, AUGUST 2007

Fig. 1. Schematic diagrams of: (a) a conventional ILFD and (b) a direct ILFD [12].

In this study, an analytical model and design guidelines of a direct ILFD are presented. Based on the developed model and guidelines, a direct ILFD without a varactor is designed and fab-ricated using 0.13- m bulk CMOS technology. With a simple pMOS current source and a suitable design, the proposed di-rect ILFD has a low input capacitance, large frequency locking range, low power consumption, and favorable noise suppres-sion capability. Therefore, the proposed direct ILFD can be in-tegrated with an MMW VCO into an MMW PLL system.

The frequency locking range of a conventional ILFD [19] is given by , where and are the resonant fre-quency and the quality factor of the LC resonator, respectively, and is the injection ratio. Accordingly, the locking range is in-versely proportional to the factor of the LC resonator. How-ever, the proposed analytical model herein reveals that for a di-rect ILFD, increasing the factor can reduce the power con-sumption without reducing the locking range. This result dif-fers from the conventional one. For verification, the other direct ILFD with an LC resonator with a lower is fabricated and comparative measurements are made.

The measurements show that the center frequency of the pro-posed direct ILFD is around 70 GHz. The operating frequency range is 13.6% at 70 GHz with 4.4 mW from a supply voltage of 1 V and an input device size of only 3.6 m/0.12 m, which is smaller than that used in another study [12].

This paper is organized as follows. Section II proposes the an-alytical model and design guidelines of a direct ILFD. Based on these design guidelines, the circuit design considerations of the proposed direct ILFD are presented in Section III. The phase-noise analysis is presented in Section IV. The measured results are described and discussed in Section V. Finally, Section VI draws some conclusions.

II. ANALYTICALMODEL ANDDESIGNGUIDELINES

The general block diagram of a differential direct ILFD is shown in Fig. 2. The active cell with positive feedback is designed to provide a negative resistance to compensate for the power loss from the resistive load per oscillating cycle for

Fig. 2. General block diagram of a differential direct ILFD.

the stable output oscillating signals. and represent the equivalent passive loads of the active cell. The input stage is implemented by using an nMOS only. The input voltage ) is applied to the gate node of , where is the input phase. For the sake of convenience, it is assumed that , as shown in Fig. 2. If the input frequency falls into the divided-by-2 locking range, then the differen-tial output voltages at the drain and the source nodes of

are given by , where is the output

phase. If , then can be denoted as , which repre-sents the phase difference between the input and output signals. In this situation, can be regarded as a mixing device and the mixing channel current of is denoted by .

In most cases, the input voltage is a large signal so is operated in the on–off mode. Fig. 3(a) and (b) shows the two sample waveforms of and , as is equal to and , respectively. As shown in Fig. 3, the time interval be-tween the two neighboring turn-on periods of is . Since the frequency of the differential output voltages at the drain and source nodes of the is exactly half of that of the input voltage, the resulting in the two neighboring turn-on periods displays the same shapes, but opposite polarities as those shown in Fig. 3(a) and (b). Therefore, the fundamental frequency of is and the fundamental component of is denoted by .

To develop the desired analytical model, is decomposed into in-phase and quadrature components

(1) As shown in Fig. 3(a) and (b), the shape of strongly de-pends on . Therefore, the amplitudes of both components in (1) should also be the functions of .

In fact, is determined by the input frequency Fig. 4(a)–(c) plots the HSPICE simulated waveforms of

and when is equal to, larger than, or smaller than , where is the resonant frequency of the equivalent passive load in Fig. 2. The waveforms of and calculated from are also shown in each. Fig. 4(a) plots the waveforms in the case of . In this

case, equals and so the phase of is

the same as the output voltage signal. Therefore, can be modeled as a single resistor with the value of . The equivalent model in this case is also shown in Fig. 4(a)

When the input frequency exceeds , as the waveforms plotted in Fig. 4(b), becomes slightly smaller than so

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Fig. 3. Two waveforms ofV ; V 6; and I , as ' is equal to: (a) =2 and (b)=4.

lags behind the output voltage signal. Therefore, is larger than 0 and can be modeled as in parallel with an inductor and are calculated as

(2) and

(3) The equivalent model in this case is also presented in Fig. 4(b). The output frequency can be easily calculated as

(4) Therefore, the maximum available value of is deter-mined by the maximum available value of , which is denoted by , and is given by

(5) The waveforms and equivalent model of the final case in which the input frequency is less than are shown in Fig. 4(c). In this case, becomes slightly larger than such that leads to the output voltage signal. Therefore, is

Fig. 4. Simulated waveforms ofV ; V ; I ; I cos(!t + '); I sin(!t + ') and the equivalent model as: (a) 2! = 2! , (b) 2! > 2! , and (c)2! < 2! .

smaller than 0 and can be modeled as in parallel with a capacitor , whose capacitance is given by

(6) The output frequency can be easily calculated as

(7) Therefore, the minimum available value of is deter-mined by the minimum available , which is denoted by , and can be expressed as

(8) From (5) and (8), the input frequency locking range denoted by

can be calculated as

(9) Given the symmetric differential structure in Fig. 2, for a par-ticular output voltage amplitude equals , and

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(9) can be further simplified as

(10) According to (10), should be designed as large as pos-sible to maximize the locking range for fixed values of and . However, since all voltage signals that are applied to

are large signals, no analytical equation exists for . Therefore, HSPICE is adopted to find the values of in the variously biased cases. Fig. 5(a)–(d) shows contour maps of for various dc overdrive voltages of and output voltage amplitudes with different input voltage amplitudes

. In all these cases, increases with for a fixed and decreases as increases in the high- region.

According to the proposed model, shown in Fig. 4, and the derived locking range equation (10), for a fixed , the quality factor of the passive load in Fig. 4 does not directly influence the locking range. More accurately, the value of only indirectly influences the locking range through a change in or , which changes , as shown in Fig. 5. For example, for a given cell, a low of the passive load results in a smaller and, thus, a larger and the locking range that is given by (10). However, in low and high cases, the locking ranges can more fairly be compared with a fixed and . In this situation, is fixed, as shown in Fig. 5, such that the locking ranges in low and high cases are the same for a fixed and , as determined by (10). Since a lower passive load has a lower , the cell needs to consume more power in order to compensate for to maintain the same output voltage amplitude at resonance. Therefore, for any required , using a higher passive load can reduce the power requirement without any reduction in the locking range.

From the above analysis, some design guidelines for a direct ILFD can be inferred. Firstly, of the input device should be designed as large as possible to maximize the and frequency locking range. Secondly, a tradeoff exists between the output voltage amplitude and the frequency locking range. Therefore, should be set at its minimum tolerant value to maximize the frequency locking range. Finally, the factor of the passive load should be as large as possible to reduce the required dc power consumption without reducing the frequency locking range.

III. CIRCUITDESIGN

A. Circuit Structure

Based on the design guidelines in Section II, the proposed ILFD circuit for high-speed operation is shown in Fig. 6. The circuit structure is simple in that it has no varactor, but it still provides a large frequency locking range.

In order to reduce the input capacitance, nMOS is used as the only input stage to generate the injected current . Fur-thermore, instead of a complementary cross-coupled pair [12], an nMOS cross-coupled pair is used to implement the cell in Fig. 2. Since the frequency locking range is inversely pro-portional to the total capacitance value at the output node, as in (10), the absence of a pMOS cross-coupled pair can signif-icantly increase the frequency locking range. Adding a pMOS current source , as shown in Fig. 6, provides two advantages

Fig. 5. Contour maps ofg as: (a)v = 0:6 V, (b) v = 0:5 V, (c) v = 0:4 V, and (d) v = 0:3 V.

over an ILFD presented in an earlier study [14], increasing the locking range. Firstly, since a tradeoff exists between the output

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Fig. 6. Circuit structure of the proposed direct ILFD.

voltage amplitude and the frequency locking range, the output voltage amplitude can be set to its minimum value by designing an appropriate dc current of to maximize the locking range. Secondly, the dc voltage at the output node can be set much lower than the VDD because the dc current is limited by . Therefore, can be biased in the high overdrive voltage re-gion. Additionally, through the resistor , the dc voltage at the substrate node of can be equal to those at the drain and source nodes such that the threshold voltage of can be kept low to increase overdrive voltage.

B. Size of Input Stage

As the operating frequency increases to the MMW band, the size of the input nMOS shown in Fig. 6 is restricted by the input capacitance since a large input capacitance makes the integration of an ILFD with an MMW VCO difficult. In the design, the target of the operating frequency is 70 GHz, and the width of the input nMOS is designed as 3.6 m, with the minimum length. From the simulation, the input capacitance of is less than 10 fF, which is an acceptable load for an on-chip 70-GHz VCO.

C. Design of pMOS Current Source

The dc current of the pMOS current source denoted by directly influences the output voltage amplitude . According to the model in Fig. 4, can be estimated as [20]. Notably, a tradeoff exists between and the frequency locking range. Therefore, should be designed appropriately such that just equals the required value at the edges of the fre-quency locking range.

D. Design of Integrated Spiral Inductor and Cross-Coupled Pair

Since the small size of constrains the value of , careful design of an integrated spiral inductor and cross-cou-pled pair to achieve a large frequency locking range is impor-tant. It can be seen from (10) that the frequency locking range

Fig. 7. Simulated frequency locking ranges andg with different values of the inductor.

is proportional to the inductor value . Initially, the frequency locking range increases with an increase in inductance. How-ever, as increases over an optimum value, the locking range begins to drop for the following two reasons. Firstly, the output center frequency can be expressed as

where is the width (length) of and in

Fig. 6, is the overlap capacitance per unit width, is the gate–oxide capacitance per unit area, and is capacitance from the next stage. Thus, as increases, must be reduced to maintain the required . At a fixed dc current, this drop increases the dc gate voltages of and and, thus, reduces the overdrive voltage of and and, thus, the locking range. Secondly, if is too small to maintain enough , such that the power loss per oscillating cycle from and in Fig. 4 cannot be compensated for when the input frequency falls in the range specified in (10), then the frequency locking range rapidly declines. Therefore, in this design, iterative simulations are required to find the optimum inductance of the spiral inductor for the maximum frequency locking range.

As mentioned in Section III-C, the factor of the passive load should be designed as large as possible to reduce the power consumption or . Accordingly, no extra resistor is connected in parallel to the inductor in the proposed circuit.

The results of Ansoft’s Nexxim simulation involving the fre-quency locking ranges with various inductances are shown in Fig. 7. In the simulation, the center output frequency is around 70 GHz, the input amplitude is 0.6 V, the input nMOS size is 3.6 m/0.12 m, and the minimum required output voltage am-plitude is 250 mV. The value in each case is obtained from Fig. 5 so the locking range can be given by (10). Fig. 7 also plots the value and the locking range given by (10), which are consistent with the simulation results.

In order to consider the frequency shift resulting from the process and temperature variation [17], the corner models pro-vided by the foundry are used to simulate the performance of the proposed divider. The shift of the center frequency is 6.98% from 0 C FF corner to 100 C SS corner. The simulated input sensitivity curves with an inductance of 400 pH in these two

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Fig. 8. Simulated input sensitivity curves in the corner cases.

extreme cases are shown in Fig. 8. The locking range of the di-vider is sufficient to cover the frequency shift as the input power is larger than 0 dBm.

IV. PHASE-NOISEANALYSIS

Here, the noise model in an earlier study [19] is modified and used to analysis the phase noise of a direct ILFD. The block diagram of a direct ILFD is redrawn in Fig. 9(a) with the active cell replaced by a negative resistor . is now given by a single sinusoidal function

(11) where is the amplitude of and is the phase of , which can be decomposed to and the extra phase . Here, is related to the phase difference between the input and output voltage signal and, thus, it can be given as a function of

.

Fig. 9(b) presents the linear loop for the phase noise analysis, where and are the random variables that represent the small phase fluctuations of the input and output voltage sig-nals. Here, represents the small phase response of the equivalent load in Fig. 9(a) and is given by

(12) where is the quality factor of the equivalent load and

is the offset frequency. The values of the partial differ-entiations in Fig. 9(b) can be easily calculated using

(13) and

(14) where is the derivative of . From (12)–(14), the transfer function of the input and output phase-noise spectral densities

and , respectively, is given by

(15)

Fig. 9. (a) Block diagram of the direct ILFD. (b) Linear loop for the phase-noise analysis.

where

(16) The calculation of the transfer function of the free-running and output phase-noise spectral densities ( and ) is as in an earlier cited study [19]; only the result is shown here as follows:

(17) From (15), the input phase noise appears at the output with a 6-dB reduction and low-pass shaping, dominating the output phase noise when the offset frequency is less than . When the offset frequency exceeds , then from (17), the output phase noise is dominated by the phase noise of the divider in free run. This result is similar to that of a conventional ILFD. The simulated curves of with various and at the central frequency are plotted in Fig. 10. From Fig. 10, increases with and generally exceeds

1 GHz when GHz and . Therefore,

with respect to noise, this structure is also suitable for MMW operations because as becomes large, its internal noise can be suppressed even at a large offset frequency.

V. MEASUREMENTRESULTS

The proposed ILFD shown in Fig. 6 is designed and fab-ricated using 0.13- m bulk CMOS technology with a supply voltage of 1 V. The size of the is only 3.6 m/0.12 m. A low- ILFD with a resistor that is connected in parallel with to reduce the factor is also fabricated on the same chip to observe the relationship between the locking range and the factor. The chip micrographs of both fabricated ILFDs are shown in Fig. 11.

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Fig. 10. Simulated curves ofS =S with different: (a)! , (b) V , and (c)V at the central frequency.

Fig. 11. Micrographs of ILFDs.

After the losses from the cable and buffer have been deem-bedded, the measured output amplitudes versus the input frequencies for the various values of are presented in Fig. 12(a). The locking range can be determined by the dif-ference between the frequencies at the two ends of each curve in Fig. 12(a). Fig. 12(b) plots the curves of the locking range and the minimum output amplitude in throughout the locking

Fig. 12. (a) Measured output amplitude versus input frequency. (b) Measured and calculated/simulated locking range and the minimum output amplitude versusI .

range versus . The simulated and calculated curves are also shown for comparison. The locking range can be increased significantly by choosing a suitable value for at the cost of a reduced output voltage amplitude. This result is consistent with those of the analysis. Notably, should be kept larger than the specific current to maintain a sufficient to com-pensate for the power loss form the equivalent resistive load per oscillating cycle. Otherwise, the stable output oscillating signals cannot be maintained. Thus, the locking range declines rapidly, as shown in the long broken-line regions of the mea-sured curves in Fig. 12(b). The maximum meamea-sured locking range is 13.6% (66.4–76 GHz) with an of 4.4 mA from a 1-V supply. Except at the low , the calculated locking ranges from (10) are consistent with the measurement results.

The measured frequency locking ranges as the supply voltage decreases to 0.8 V are plotted in Fig. 13. The locking ranges are considerably smaller than those in the 1-V case because the drop in the supply voltage reduces the overdrive voltage of and also . This result is also consistent with analytic results.

The measured locking ranges versus the output voltage amplitudes of the proposed and low- ILFDs are plotted

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Fig. 13. Locking range as the supply voltages are 0.8 and 1 V.

Fig. 14. Measured locking ranges versus output voltage amplitudes of both proposed and low-Q ILFDs.

in Fig. 14. The value of in each case is marked on the measured curves. For any required output voltage amplitude, reducing the factor not only increases the required , but also reduces the frequency locking range. The locking range declines because an increase in reduces the overdrive voltage and thereby also . The measured input sensitivi-ties of both dividers are plotted in Fig. 15. The proposed ILFD also has a greater input sensitivity than the low- ILFD.

The measured output phase noise and phase noise of the input signal from the Agilent MMW Source Module E8257DS15 [22] are both plotted in Fig. 16(a). This figure reveals that the output phase noise is determined by the input phase noise below the 300-kHz offset frequency. Beyond the 300-kHz offset, the output phase noise is corrupted by a flat noise floor of approxi-mately 120 dBc/Hz. The waveform of this extra noise is flat and shapeless so its source is not within the closed loop that is shown in Fig. 9(b). Since only the single-ended output signal is measured, this noise floor may be from the common-mode noise from the pMOS current source, supply voltage, and ground, or the instrument itself. The output phase noise and the phase noise in free run are both plotted in Fig. 16(b). Although

Fig. 15. Measured input sensitivities of both ILFDs.

Fig. 16. (a) Measured output phase noise and the phase noise of input signal from Agilent MMW Source Module E8257DS15 [22]. (b) Measured output phase noise and the free-run phase noise.

the output signal in free run is noisy, the output phase noise after locking is almost independent of the phase noise in free run below the 10-MHz offset frequency. Beyond the 10-MHz offset frequency, the phase noise in free run is also corrupted by a flat noise floor at around 120 dBc/Hz. Therefore, the internal noise in the loop in Fig. 9(b) from the ILFD is observ-ably suppressed before the 10-MHz offset frequency at the very least.

The performances of the proposed divider and other CMOS frequency dividers at above 40 GHz are compared in Table I. Without a varactor, the locking range of the proposed divider is 13.6% at 70 GHz. Finally, the device size of the input stage is 3.6 m/0.12 m, which is smaller than that presented elsewhere [12].

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TABLE I

PERFORMANCECOMPARISONBETWEEN THEPROPOSEDCMOS ILFD

ANDOTHERCMOS FREQUENCYDIVIDERS

VI. SUMMARY

In this paper, an analytical model for a direct ILFD is pre-sented. From the proposed model, important design guidelines have been developed. Based on the design guidelines, a 70-GHz direct ILFD has been designed and fabricated using 0.13- m bulk CMOS technology, where a pMOS current source was used to restrict the output voltage amplitude and to increase the overdrive voltage of the input device to improve the frequency locking range. For a direct ILFD, a higher passive load can release the power required without decreasing the frequency locking range. Even if the input device size is small and the varactor is not used, the frequency locking range is large. Therefore, the proposed direct ILFD can be integrated with an MMW VCO easily and is a favorable choice for use in a CMOS MMW PLL system.

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Chung-Yu Wu S’76–M’76–SM’96–F’98) was born

in 1950. He received the M.S. and Ph.D. degrees in electronics engineering from National Chiao Tung University, Hsinchu, Taiwan, R.O.C., in 1976 and 1980, respectively.

Since 1980, he has been a consultant to high-tech industry and research organizations and has built up strong research collaborations with high-tech indus-tries. From 1980 to 1983, he was an Associate Pro-fessor with National Chiao Tung University. From 1984 to 1986, he was a Visiting Associate Professor with the Department of Electrical Engineering, Portland State University, Port-land, OR. Since 1987, he has been a Professor with National Chiao Tung Univer-sity. From 1991 to 1995, he served as the Director of the Division of Engineering and Applied Science, National Science Council, Taiwan, R.O.C. From 1996 to 1998, he was honored as the Centennial Honorary Chair Professor with Na-tional Chiao Tung University. He is currently the President and Chair Professor of National Chiao Tung University. In Summer 2002, he conducted post-doc-toral research with the University of California at Berkeley. He has authored or coauthored over 250 technical papers in international journals and conferences. He hold 19 patents, including nine U.S. patents. His research interests are na-noelectronics, biochips, neural vision sensors, RF circuits, and computer-aided design (CAD) analysis.

Dr. Wu is a member of Eta Kappa Nu and Phi Tau Phi. He was a recipient of 1998 IEEE Fellow Award and a 2000 Third Millennium Medal. He has also been the recipient of numerous research awards presented by the Ministry of Education, National Science Council (NSC), and professional foundations in Taiwan, R.O.C.

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Chi-Yao Yu was born in Taipei, Taiwan, R.O.C., in

1978. He received the Master’s degree in communi-cation engineering from National Tsing Hua Univer-sity, Hsinchu, Taiwan, R.O.C., in 2002, and is cur-rently working toward the Ph.D. degree at National Chiao Tung University, Hsinchu, Taiwan, R.O.C.

His current research is focused on communication systems, mixed-signal integrated circuit design, CMOS MMW circuits, and CMOS RF front-end circuit design.