RF CMOS technology for MMIC
Chun-Yen Chang
*, Jiong-Guang Su, Shyh-Chyi Wong, Tiao-Yuan Huang,
Yuan-Chen Sun
Department of Electronics Engineering, Institute of Electronics, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu 300, Taiwan, ROC
Received6 December 2001
Abstract
This paper presents a high performance RF CMOS technology with a complete portfolio of RF andbase band components for single-chip systems. Using an optimized0.13 lm CMOS topology, fTof 86 GHz and fmaxof 73 GHz
are obtained, in addition to a NFminof 1.5 dB without ground-shielded signal pad. The high-Q accumulation-mode and
diode varactors are optimized to perform a high tuning range of 47% and 25%, respectively. Inductors with a quality factor of 18 at 1.7 nH are obtainedusing copper interconnect, while capacitors with high unit capacitance andquality factor are fabricated with metal-insulator-metal structures. Finally, a deep n-well isolation is adopted to suppress the interblock coupling noise penetrating through substrate by 40 and25 dB at 0.1 and2.4 GHz, respectively. These results clearly demonstrate that CMOS technology can provide a complete solution for single-chip wireless systems. Ó 2002 Elsevier Science Ltd. All rights reserved.
1. Introduction
Successful implementation of the entire circuit blocks in a single-chip requires the integration of precise and high performance passive as well as active components [1]. In recent years CMOS technologies have become quite attractive for RF circuit implementation due to aggressive scaling, high-speedperformance, andcost reduction. In the development of short-range wireless communications, CMOS has receivedtremendous in-terest by integration with high performance digital cir-cuits andhigh-speedanalog circir-cuits [2]. Nonetheless, several major issues need to be addressed for adopting CMOS to RF products. First of all, the RF performance of MOS transistor itself represents a bottleneck due to limitedcut-off frequency (fT), maximum oscillation
fre-quency (fmax), andhigh-frequency noise performance
(NFmin) [3]. Secondly, the fabrication of RF passive
components with high quality factor (Q) is in direct conflict with the fine-pitch andthin-line metallization
used in advanced CMOS technologies. Thirdly, the coupling noise propagation through the substrate, due to noise generated during CMOS digital switching, complicates the integration of digital, analog and RF blocks on the same chip [4,5]. Isolation among each individual RF blocks become crucial in implementing high precision andhigh quality RF circuits.
In this paper, optimization of device design using an existing logic CMOS baseline for RF circuit applications is discussed [3,6–11]. This approach is quite promising because of its compatibility with existing logic CMOS technology andinherent reliability. Various high-Q var-actors are investigated. The resultant integrated varac-tors can be successfully implementedas the capacitive tuning elements for monolithic microwave ICs (MMIC). The on-chip inductors, which often are a performance limiting component in many important RF circuits, such as voltage-controlledoscillators (VCO) phase noise [12], low-noise amplifiers (LNA) bandwidth [13], and passive filters loss, are also presented. Additionally, the metal-insulator-metal (MiM) capacitors with their highly linearity, are discussed by observing their RF charac-teristics. Finally, the use of a deep n-well isolation for integrating RF blocks with low coupling noise is also discussed.
www.elsevier.com/locate/microrel
*
Corresponding author. Tel.: 571-8083; fax: +886-3-572-1500.
E-mail address: [email protected] (C.-Y. Chang).
0026-2714/02/$ - see front matterÓ 2002 Elsevier Science Ltd. All rights reserved. PII: S 0 0 2 6 - 2 7 1 4 ( 0 2 ) 0 0 0 0 6 - 9
This paper is organizedas follows. After a brief in-troduction in Section 1, RF performance of MOSFET is described in Section 2. Section 3 describes the varactors, while Section 4 discusses the on-chip inductors. The MiM capacitors are discussed in Section 5, and the substrate coupling is discussed in Section 6. Finally, a brief conclusion is given in Section 7.
2. RF performance of MOSFET
2.1. Small-signal model analysis of MOSFET
To investigate the RF figure of merit (FOM) for MOSFET, we first concentrate on the small-signal model of MOSFET. The cross-section of a MOSFET is shown in Fig. 1. The intrinsic parts of the MOSFET, enclosedin the box with broken lines in Fig. 1, are re-sponsible for the transistor action, andconsist of the gate, gate oxide, inversion layer and the depletion region between source anddrain. The extrinsic parts of MOS-FET, which are locatedoutside the box, consist of all the parasitics. The complete small-signal equivalent circuit for RF application is as shown in Fig. 2(a). The gate transconductance gm, source-drain conductance gdsand
body transconductance gmb describe the channel
trans-port current [14] with the following relation:
iT¼ gmvgsiþ gdsvdsiþ gmbvbsi; ð1Þ
where vgsi, vdsiand vbsi represent the voltage changes of
the intrinsic parts. In addition to the transport current, charge storage effects are governedby the intrinsic ca-pacitance Cgsi, Cgdi, Csbi, Cdbi and Cgbi.
The gate resistance Rg is composedof the resistance
of polygate andcontact, while the source/drain resis-tance Rs=Rd includes the spreading resistance, diffusion
resistance, andcontact resistance of source/drain. The p-well resistance is modeled by Rsb, Rdband Rdsbwhich is
the proximity resistance between source anddrain [15, 16]. Finally, capacitance Cgse and Cgde comprise the
overlap capacitance andthe outer fringing capacitance between gate andsource/drain, which is in parallel with Cgsi and Cgdi. Hence, the whole gate-to-source
capaci-tance Cgsandgate-to-drain capacitance Cgd can be
rep-resentedas Cgs¼ Cgsiþ Cgse;
Cgd¼ Cgdiþ Cgde:
ð2Þ In addition, source and drain junction capacitance Cjsb
and Cjdbare in parallel with Csbi and Cdbi, respectively.
Hence, the whole source-to-body capacitance Csb and
drain-to-body capacitance Cdbcan be representedas
Csb¼ Csbiþ Cjsb;
Cdb¼ Cdbiþ Cjdb:
ð3Þ
Lastly, the extrinsic gate-to-body capacitance Cgbe and
intrinsic capacitance Cgbi can be incorporatedinto the
whole gate-to-body capacitance Cgb, as shown below:
Cgb¼ Cgbiþ Cgbe: ð4Þ
Hence, the small-signal equivalent circuit can be further constructedas shown in Fig. 2(b) by taking into account (2)–(4). For two-port common-source S-parameter measurements, the source andbody are tied to the ground, while the gate and drain are connected to the input andoutput ports respectively. So to obtain Y-parameters that reflect the configuration of measure-ment, source and body nodes in Fig. 2(b) should be grounded. The Y-parameters can be derived according to Fig. 2(b), andis shown below [15,16]:
y11ffi jxCgg 1þ jxRgCgg ffi x2 R gC2gg þ jxCgg; y12ffi jxCgd 1þ jxRgCgg ffi x2R gCggCgd jxCgd; y21ffi gm jx Cmþ Cgd 1þ jxRgCgg ffi gm x2RgCgg Cm þ Cgd jx Cm þ Cgdþ gmRgCgg ; y22ffi gdsþ jx Cbdþ Cgd 1þ jxRgCgg ffi gdsþ x2RgCgg Cbd þ Cgd þ jx Cbd þ Cgd gdsRgCgg ; ð5Þ
where Cgg¼ Cgsþ Cgdþ Cgb, and Cm is the
transcapac-itance that equals to the difference between intrinsic drain-to-gate capacitance and gate-to-drain capacitance (i.e., Cdgi Cgdi). The derivation of (5) neglects the
source/drain resistance and the p-well resistance, and assumes RgCgg 1. The Y-parameters are very useful
for analyzing RF FOM of MOSFET. 2.2. Layout of MOSFET cell
The schematic top-view of MOSFET with finger-type gate andp-well contacts, which will be called‘‘MOSFET cell’’ in this paper, is shown in Fig. 3(a). All fingers have the same gate length Lg. The total gate width Wt thus
equals to the unit finger length (Wf) multipliedby the
total finger number (m). A wide gate width is often used to improve the transconductance of the MOSFET cell, however, gate resistance increases because of the wide gate width. To alleviate this undesirable effect, multi-finger gate structure is generally employedto effectively reduce the gate resistance. For MOSFET cell with multi-finger gate structure, the gate resistance is reduced by the square of the finger number. Further, since gate contacts are designed on both sides of each finger, the gate re-sistance is reduced by a factor of 12 due to the
distri-bution nature in high-frequency range [17]. In this study, multiple ohmic contacts to p-well substrate are formed to surroundthe active region, as shown in Fig. 3(a). These contacts serve as guard-ring to further reduce the
substrate resistance andcoupling noise [18,19]. It should be notedthat ohmic contacts to p-well substrate can also be designed on only the two sides of the active region.
Fig. 1. The cross-section of MOSFET including the parasitics for small-signal equivalent circuit.
Fig. 2. Quasi-static small-signal model of MOSFET for RF applications: (a) incorporating all parasitics, and(b) a simpli-fiedversion.
Fig. 3. (a) Top-view of MOSFET cell with multi-finger gates for RF applications. The gate contacts are locatedat the two ends of polygate. Wf and m represent unit finger length and
The latter layout has the advantages of easy character-ization andmodeling of the substrate resistance [20,21]. However, substrate resistance increases due to increased physical distance of the current path in the MOSFET cell. An increase in substrate resistance raises the in-trinsic p-well bias level, causing an undesirable kink effect that is different from the kink effect in SOI technology. The output resistance of MOS transistors is also degraded. To alleviate this undesirable effect, the ‘‘guard-ring type’’ p-well contacts are adopted for all MOS cells usedin this work.
In order to scale up the total gate width Wt, e.g., to
scale up MOSFET cell with Wt¼ 2w to Wt¼ 6w, three
methods can be used as described in Fig. 3(b). The first methodis to scale up the unit finger length Wf while
maintaining the original finger number. The second methodis to scale up the finger number m while main-taining the original unit finger length. Finally, the third methodis to scale up both the finger number andunit finger length. However, secondary effects due to finger-type structure affect not only the static but also the RF behaviors of MOSFET cells. The dependence of unit finger length andthe finger number on RF parameters shouldtherefore be investigatedseparately in order to exactly analyze the impact of finger-type layout on the transistors’ RF performance. In general, MOSFET cell with finger-type gates can be regarded as consisting of multiple transistors that are arrangedin parallel with respect to each other. Each individual transistor shares its source/drain with its adjacent transistors, therefore its source/drain region is not surrounded by shallow trench isolation.
2.3. Unity-current-gain cut-off frequency, fT
The fTof transistor is a common FOM for the speed
of a transistor. The fT is measuredin our study by
finding the regression line ofjH21j andthen extrapolated
tojH21j ¼ 1. This methodis more reliable than the
gain-bandwidth product method. The fTcan be derived from
the Y-parameters of MOSFET by setting jy21=y11j ¼ 1
[14,15,22], andis shown as fTffi gm 2p ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiC2 gg C 2 gd q : ð6Þ
The fTof a 0.13 lm MOSFET cell versus the drain
current (Ids) with Vds as a parameter (1.2 and0.6 V) is
shown in Fig. 4. Peak fTis foundto occur at the
max-imum gate transconductance gmx[3,22]. In addition, no
obvious drain bias dependence is found. According to (6), fTof MOSFET cell shouldbe proportional to 1=L2g,
so the dependence on technology scaling can be esti-mated. The reported fT as a function of feature size
(some in gate length andsome in channel length) available from the literature are plottedin Fig. 5(a)
Fig. 4. Cut-off frequency versus drain current with Vds¼ 0:6 V
and1.2 V.
Fig. 5. (a) The reported fTwith respect to technology shrinkage
from literature. (b) Cut-off frequency with various geometric parameters. The fT’s in this figure were obtainedwith Vgsbiased
[1,3,9,10,23–29]. It can be seen that when the gate length is shrunk below 0.1 lm, fTwill exceed100 GHz.
The dependence of finger number on fTof MOSFET
cells is shown in Fig. 5(b). All fT’s in Fig. 5(b) were
obtainedwith Vgsbiasedat gmx. With a given Wf, fT is
degraded with increasing finger number (i.e., which corresponds to the second method illustrated in Fig. 3(b)). It is foundthat the peak fTdecreases from 86 to 67
GHz when m increases from 18 to 36 for Wf¼ 4 lm. In
addition, increasing Wfwith a given m increases fT(i.e.,
which corresponds to the first method illustrated in Fig. 3(b)). As shown in Fig. 5(b), the peak fT can be
enhancedfrom 72.7 to 86 GHz when Wf decreases from
8 to 4 lm for m¼ 18.
2.4. Maximum oscillation frequency, fmax
The fmaxis the bandwidth of a transistor as an active
component. In contrast to fT, fmaxis very sensitive to the
layout due to its strong dependence on parasitic resis-tance. Two methods can be used to extrapolate fmax, i.e.,
MSG/MAG andMason’s power gain methods [30].
Since the stability factor (i.e., k-factor) of MOSFET is relatively small over a wide frequency range for deep-submicron technology [11,29], the extraction of fmax
from MSG/MAG is difficult. Rather, Mason’s unilateral power gain U is usedto findfmax. Although U is a
popular methodto determine fmax in recent literatures
[3,31], however, it is worthy to note that U couldbecome negative under certain conditions especially in lower frequency range for MOSFET because of the relatively small k-factor. It can be shown that the necessary con-dition for U < 0 is k-factor < 1. Basedon the small-signal model of MOSFET, fmaxcan be derived [3,28]
fmax¼
fT
2 ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffigdsðRgþ RsÞ þ 2pfTRgCgd
p : ð7Þ
The fmaxversus Idswith various Wtis shown in Fig. 6.
The bias dependence of fmaxis mainly due to gmand gds
as shown in (7). So the peak fmaxdoes not occur at the
Vgs corresponding to the maximum gate
transconduc-tance. For Ids larger than 10 mA, fmax is degraded
be-cause of increased gds. The reported dependence on gate
length from the literature can be foundin Fig. 7(a). Although the trendthat fmaximproves with reduced gate
length can be found, data are more scattered, when compared to the technology dependence on fT. This is
because some of the reportedresults were not basedon the optimal layouts. In addition, some of the fmax was
not extractedat the optimal biases. Finally, in some cases the measuredfrequency was limitedto obtain the exact fmax. Even though, to design MOSFET cell with
optimal fmax, geometric parameters Wf and m shouldbe
properly chosen. The Wf dependence with a given m can
be observedin Fig. 6. It is clearly shown that MOSFET
cell with larger Wf at a given finger number exhibits
higher Rg, Cgd and gds andsmaller fT (i.e., Fig. 5(b)),
therefore a lower fmax. In addition, the finger number
Fig. 6. Bias dependence of fmaxwith various Wt.
Fig. 7. (a) The reported fmax with respect to technology
shrinkage from literature, (b) maximum oscillation frequency with various geometric parameters.
dependence of fmax is shown in Fig. 7(b). The fmax
ex-hibits only minor dependence on m at a given Wf. Only 3
GHz variations were foundin our experiments. This result can be further confirmedby (7) while normalizing Wtof each terms in (7).
2.5. High-frequency noise of MOSFET cell
The noise sources in MOSFET include terminal re-sistive noise, channel noise, induced gate noise, 1=f noise, andsubstrate resistive noise. Among them, 1=f noise is dominant in lower frequency range (i.e., lower than 100 MHz). The terminal resistive noise is attributed to the parasitic resistance of MOSFET, including the gate resistance and source/drain diffusion resistance. Channel noise is mainly due to the thermal noise gen-eratedby the channel carriers [14,16,22,32–36]. Sub-strate resistive noise is ascribedto the resistive subSub-strate. The fluctuation of Vbs due to resistive noise can be
coupled by the body transconductance gmbto the drain
current [33,37,38]. Lastly, the induced gate noise is at-tributedto the channel voltage fluctuation andis cou-pledby the gate capacitance [13,14,22,33]. Contrary to the 1=f noise, this noise source increases with frequency. To investigate the noise in MOSFET cells, a mea-surable parameter, the minimum noise figure NFmin can
be used. The NFminof MOSFET can be derived from the
small-signal model by incorporating all noise sources, andthen transforming the noisy two-port network to the equivalent noise-free network with external noise sour-ces at the input. Detailedderivation can be foundin [22]. Hence, NFmin of MOSFET is as shown below [3,28]:
NFmin¼ 1 þ K f fT ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi gm Rgþ Rs q ; ð8Þ
where K in (8) is a fitting parameter. It is clearly shown in (8) that NFmin improves with the bandwidth. The bias
dependence of NFmin andassociatedgain of MOSFET
cells can be foundin Fig. 8(a). NFmin minimum can be
obtainedat a certain bias. The noise measurements shown in Fig. 8(a) were performed without de-embed-ding the probing pads. Hence, the thermal noise of re-sistive p-substrate will be coupledto the pads and increases NFmin. The determination of Wf and m
depen-dences of MOSFET cells without pad parasitics is questionable. Therefore, discussions in Wf and m
de-pendence are not included here. However, based on (8) andthe reportedresults in [22], NFmin will be degraded
with increased Wf, albeit independent with m. Additional
discussions in parallel–series configuration and cascade configuration of noise de-embedding can be found in [39] and[40–42], respectively.
Fig. 8(b) shows the reported NFminwith respect to the
technologies from literature. It can be seen that NFminat
2 GHz for technologies below 0.25 lm is lower than 0.5
dB. For the 0.1 lm technology, NFmin smaller than 0.2
dB at 2 GHz can be obtained as expected from (8).
3. Varactors
The varactors play an indispensable role in the suc-cessful monolithic solutions with RF CMOS technology. Because of their bias-variable capacitance, varactors are widely used in many applications including parametric amplification, harmonic generation, frequency conver-sion andfrequency tuning [43,44]. The key criteria for designing high-performance varactors are high quality factor, high tuning range, voltage compatibility with technology scaling, high self-resonant frequency, and unit high capacitance [45–47].
3.1. Characteristics of varactors
The tuning range of varactors can be determined by performing C–V measurements, andshouldbe as high
Fig. 8. (a) Bias dependence of NFmin various Wt. (b) The
re-ported NFminwith respect to technology shrinkage from
as possible to reduce the power consumption. To cal-culate the tuning range, the bias range shouldbe defined first. Next, the maximum capacitance Cmax
andmini-mum capacitance Cminare determined in this range, the
tuning range of a varactor can be calculatedas follows [47,48]:
tuning range¼ DC Ccenter
100%; ð9Þ
where Ccenter¼ 0:5ðCmaxþ CminÞ, and DC ¼ Cmax Cmin.
Besides the tuning range, quality factor Q is also an important RF FOM of varactors. Fig. 9 shows a simple equivalent circuit of varactor. Rs is the equivalent
in-series resistance, Cjis the equivalent in-series
capaci-tance, Rp is the in-parallel resistance, and Ls is the
in-series inductance. Traditionally, Q value can be obtained basedon the network theory as shown below:
Q¼ImðY11Þ ReðY11Þ
: ð10Þ
Fig. 9. Small-signal equivalent circuit of varactor.
However, definition of Q in this manner is only validfor low-frequency regime. At low frequency, xLs can be
neglectedso Q is roughly estimatedas 1=xRsCj. At high
frequency, however, distribution effect as well as paras-itics needs to be incorporated into Y11, anda more
pre-cise representation shouldbe usedfor more accurate estimation of varactor’s Q value. Although several methods have been proposed for calculating Q values of passive components, such as phase stability, bandwidth, andthe maximum energy methods [49,50], Eq. (10) can still be usedto estimate the varactor’s Q values in the applied frequency range. In addition, the S-parameter measurements of varactors shouldbe performedextra care in order to extract consistent Q value. This is be-cause the in-series resistance Rsof a varactor is typically
only a few ohms, thus the contact resistance between the probe-tips and G–S–G pads will distort the varactor’s Q value, andshouldbe taken into account for reliable measurement.
3.2. Types of varactors in RF CMOS technology In principle, two types of varactors, diode-type and MOS-type varactors, are commonly usedfor RF appli-cations as illustrated in Fig. 10. The diode-type varactor can be formedin pþdiffusion/n-well and nþ
diffusion/p-well. The commonly usedvaractor is the pþ
diffusion/n-well diode due to the smaller diffusion/n-well resistance and the isolation between n-well/p-substrate. C–V characteristics of pþ diffusion/n-well varactors based on 0.18 lm
CMOS technology are shown in Fig. 11(a). The usable bias range for diode-type varactor is between the weak forwardbias andthe reverse bias. The 2-V tuning range (i.e., 0.5 to1.5 V) of the smallest diode varactors are 25.9%, and25.7% and25.5% for the medium andlargest diode varactors, respectively. The corresponding Q–V characteristics at 2.4 GHz are shown in Fig. 11(b). The quality factor of varactors decreases with increased bias andpþarea due to the higher capacitance.
Even the diode varactor exhibits excellent RF per-formance. The bias range of diode varactor is reduced with the technology scaling [47,48]. For example, diodes can be biasedbetween 0.5 and1.8 V for 0.18 lm tech-nology, but biasedbetween 0.5 and1.2 V for 0.13 lm technology. Contrary to the diode varactors, MOS varactors have wider bias range. MOS varactors can be classified as inversion-mode and accumulation-mode MOS varactors, as shown in Fig. 10. The inversion-mode MOS varactor is basically the MOSFET with source, drain and body connected together as one-end. The channel resistance of this type of varactor serves as the main power loss while biasedat strong inversion, thus lowering the quality factor [46]. In addition, the gate andwell resistance also dissipates power. For the accumulation-mode MOS varactor, as illustrated in Fig. 10, the doping of source, drain, well and gate are of the
same type. Advantages of the accumulation-mode MOS varactors are smaller resistive loss, higher capacitance per area and better linearity [1]. In addition, with the trendof technology scaling, the ultrathin gate dielectric andheavy channel doping will increase the unit capac-itance. Fig. 12(a) is the C–V characteristics of accumu-lation-mode MOS varactor with 3.2 nm oxide. All three varactors depict almost the same tuning range of 47.7%. Compared to the diode-type varactor, accumulation-mode MOS varactor depicts better tuning range. The corresponding quality factor at 2.4 GHz is shown in Fig. 12(b). Again, Q value of MOS varactor decreases with increasedcapacitance, as expected.
4. On-chip inductors
In silicon-basedRF technologies, inductor represents an important andpotential limitation in RF circuit
Fig. 11. (a) C–V characteristics of pþ diffusion/n-well diode
performance for circuits such as VCO, LNA, passive element filters, etc. [12,13,51]. A desirable inductor shouldpossess several features, including high quality-factor for low power loss andhigh storage energy, high self-resonance frequency for minimum inductance vari-ation with various frequencies, high unit inductance for high integration efficiency [45], andhigh robustness for minimal process derivation. Considerable efforts have been devoted to meet these goals [52,53].
For silicon-basedMMIC, the quality factor degra-dation of inductor is mainly due to metal loss and sub-strate eddy current loss. The metal loss includes the ohmic and eddy current loss. To reduce the metal loss in order to enhance the quality factor, there are two ap-proaches. The first approach is to use low resistive metal as the inductor coils. The second approach is to employ taper inductor to reduce eddy current loss of metal line [54–57]. To achieve a low resistive metal, an effective way is to use a low-resistivity metal and/or increase the metal thickness. Fig. 13 shows the Q andinductance of
copper metal in top-wiring layer with a thickness of 2.8 lm. The Cu inductor gives, for a 1.7 nH inductor, a peak Q of 18 at 4.8 GHz and Q of 14 at 2.4 GHz. It shouldbe
Fig. 12. (a) C–V characteristics of accumulation-mode MOS varactor. (b) The corresponding quality factor.
Fig. 13. Quality factor andinductance versus frequency of a 2.8-lm thick copper top-wiring layer.
Fig. 14. (a) The spiral inductors with arithmetically progressive width. (b) The quality factor.
notedthat to improve Q value by thickening the metal is limitedby the skin depth of the metal, hence, an even thicker Cu wouldnot help improve the Q value obvi-ously. On the other hand, eddy current loss, that shows much stronger frequency dependence [58,59], can be reduced by using arithmetically progressive width pat-tern as shown in Fig. 14(a). Since the distribution of magnetic fieldis concentratedin the inner turns of the spiral inductor, rather than in the outer turns, the in-duced eddy current loss is more significant in inner turns of the spiral inductor. In addition, the eddy current loss is proportional to the metal stripe area in which the magnetic fieldpenetrates. With a larger DW , the eddy current loss is more significantly reduced, because of the larger reduction in metal width of the inner turns. The experimental results can be foundin Fig. 14(b), the broadening spiral inductor with DW ¼ 3 lm exhibits a high Q of 9.68 at 2.0 GHz. Comparedto the conven-tional inductor (with constant W), the Q-factor has improvedby 18.8%.
In addition, pattern ground plate underneath the inductor can be used to reduce the substrate loss. Pat-tern groundshielding using polysilicon has been recog-nized as a useful method to prevent substrate eddy loss [60]. In our work, three kinds of materials for ground-shieldwere investigated, i.e., metal, ploysilicon and silicide without polysilicon underneath it. The improve-ment of Q-factor can be obtainedby the polysilicon and
silicide pattern ground as shown in Fig. 15, both pro-viding 16% peak Q increase. In contrast, no improve-ment is foundfor the metal-1 pattern ground. This is because the silicide and polysilicon provided better eddy current shielding, while metal does not.
5. Metal–insulator–metal capacitors
Even the varactors can provide the capacitive char-acteristics for RF blocks, however, in some specific
Fig. 15. Quality factor of spiral inductor by using pattern groundplate to reduce the substrate loss.
cases, varactors cannot satisfy the demand of linear capacitance for matching network. Instead, MiM ca-pacitor can be developed to serve this purpose. Three types of MiM capacitors are commonly developed. The first type is the mesh capacitor, which adopts the inter-connect arrays that are arrangedas mesh fixture [61]. The secondtype is the plate capacitor fabricatedwith existing metal layers [45], for example, metal-4 and metal-5. The thirdtype is the plate capacitor with thin oxide, which can be fabricated by depositing an extra metal layer [1]. The first two types can be fabricated without additional process steps or mask, however, the unit capacitance is relatively small comparedto the plate capacitor with thin oxide.
Fig. 16(a) shows the cross-section of a MiM capaci-tor that exhibits high capacitance per area. The bottom plate of MiM capacitor is made of metal-5, with an additional thin metal layer between metal-5 and metal-6 as the top plate. The dielectric of MiM capacitor is the PECVD oxide with a thickness of 37.2 nm. The quality factor of MiM capacitor is 118 at 2.4 GHz as shown in Fig. 16(b). Capacitance per area of this capacitor is 1 fF/ lm2, which is about 30 times higher than that of the
plate capacitor with crude metal layer (i.e., the second type of MiM capacitor as described in Section 5). In addition to the quality factor, the voltage coefficient andthe temperature coefficient are 61.6 ppm/V and 52.25 ppm/°C, respectively. These results indicate that MiM capacitor depicts highly linear characteristics. Finally, the leakage current of this MiM capacitor is smaller than 1 fA/lm2 at a dc bias of 10 V (data not
shown).
6. Coupling noise
A critical issue in system integration is the substrate coupling noise [4], which could be induced by digital circuits disturbing small-signal analog circuits, or by a large-signal RF circuit (such as oscillators, power am-plifiers) disturbing a small-signal circuit. The noise propagation is aggravatedin standardCMOS technol-ogy using low-resistivity substrate. High-resistivity sub-strate, though capable of improving coupling noise as well as reducing component signal loss [62], may induce serious latch-up problems. The coupling noise reduction can be achievedby either reducing the noise source or adding a noise stopper. The latter approach is more popular, andcan be accomplishedby using pþ
guard-ring or deep n-well isolation [18,19]. As shown in Fig. 17, with pþ diffusion representing a noise injector, the
deep n-well can be placed around the pþ injector and
biasedthrough a surface n-well that is connectedto the deep n-well. The proposed deep n-well should be deep enough to minimize disturbing the dc characteristics of MOSFETs, but not so deep so that it can be connected
to the regular n-well. Consequently, the receivednoise power is measuredfrom another pþ diffusion, namely
the noise receiver, using a network analyzer to measure its forwardpower gain S21. As shown in Fig. 18(a), the
coupling noise measuredfrom the receiver is improved by 40 and25 dB at 100 MHz and2.4 GHz, respectively. Distance between the noise source andthe receiver in this experiment is 100 lm. These results demonstrate
Fig. 17. Illustration of substrate coupling experiment.
Fig. 18. (a) Comparison between pþdiffusion with and without
deep n-well isolation. (b) Substrate coupling for various pþ
that placing a deep n-well around the noisy circuits can successfully eliminate the coupling noise to other sensi-tive circuits. It shouldbe notedin Fig. 18(b) that, al-though increasing the inter-pþspacing also reduces the
injectednoise, the amount of noise power reduction is only around5 dB per 50 lm spacing increase, which is mush less effective than applying a deep n-well.
7. Conclusion
In this paper, the dimensional analysis of RF FOMs of 0.13 lm RF CMOS were characterized and discussed. It is shown that fTof 86 GHz and fmaxof 70 GHz can be
obtainedwith nMOSFET cells with Wt¼ 72 lm, Wf¼ 4
lm and m¼ 18. The NFmin of 1.5 dB without pads
de-embedding was observed in nMOSFET with Wt¼ 144
lm, Wf¼ 4 lm and m ¼ 36. In addition, high
perfor-mance passive components such as varactors, inductors andMiM capacitors can be implementedby adopting CMOS technology for RF networks. Finally, noise due to substrate coupling can be effectively suppressedby adding a deep n-well isolation. The successful imple-mentation of all active andpassive components offers a complete solution for single-chip application.
Acknowledgement
This work was supportedin part by National Science Council, Taiwan, ROC, under Contract NSC90-2215-E009-072.
References
[1] Hsu HM, Chang JY, Su JG, Tsai CC, Wong SC, Chen CW, et al. A 0.18 lm foundry RF CMOS technology with 70 GHz FTfor single chip system solutions. In: IEEE Symp
Microwave Theory Tech, 2001. p. 1869–72.
[2] Chatterjee A, Vasanth K, Grider DT, Nandakumar M, Pollack G, Aggarwal R, et al. Transistor design issues in integrating analog functions with performance digital CMOS. In: IEEE Symp VLSI Tech Dig, 1999. p. 147–8. [3] Burghartz JN, Hargrove M, Webster C, Groves R, Keene
M, Jenkins K, et al. RF potential of a 0.18-lm CMOS logic technology. IEEE Trans Electron Dev 2000;47(4):864–70. [4] Pfost M, Rein HM. Modeling and measurement of substrate coupling in Si-bipolar IC’s up to 40 GHz. IEEE J Solid-State Circ 1998;23(4):582–91.
[5] Subbanna S. Prospects of silicon–germanium-basedtech-nology for very high-speedcircuits. In: IEEE MTT-S Dig, 2000. p. 361–4.
[6] Shaver DC. Microwave operation of submicrometer chan-nel-length silicon MOSFET’s. IEEE Electron Dev Lett 1984;6:36–9.
[7] Camillieri N, Costas J, Lovelace D, Ngo D. Silicon MOSFET’s, the microwave device technology for the
90’s. In: IEEE Symp Microwave Theory Tech, 1993. p. 545–8.
[8] Vanoppen RRJ, Geelen JAM, Klaassen DBM. The high-frequency analogue performance of MOSFET’s. In: Proc IEDM, 1994. p. 173–6.
[9] Voinigescu SP, Tarasewicz SW, MacElwee T, Ilowski J. An assessment of the state-of-the-art 0.5 lm bulk CMOS technology for RF applications. In: Proc IEDM, 1995. p. 721–4.
[10] Morifuji E, Momose HS, Ohguro T, Yoshitomi T, Kimijima H, Matsuoka F, et al. Future perspective and scaling down roadmap for RF CMOS. In: Symp VLSI Tech Dig, 1999. p. 163–4.
[11] Su JG, Wong SC, Chang CY, Chiu KY, Huang TY, Ou CT, et al. New insights on RF CMOS stability relatedto bias, scaling, andtemperature. In: IEEE Proc Hong-Kong Electron Dev Meeting, 2000. p. 40–3.
[12] Craninckx J, Steyaert MSJ. A 1.8-GHz low-phase-noise CMOS VCO using optimizedhollow spiral inductors. IEEE J Solid-State Circ 1997;32(5):736–44.
[13] Schaeffer DK, Lee TH. A 1.5-V, 1.5-GHz CMOS low noise amplifier. IEEE J Solid-State Circ 1997;32(5):745–59. [14] Tsividis Y. Operation and modeling of the MOS transistor.
2nded. Singapore: McGraw-Hill; 1999.
[15] Jen SHM, Enz CC, Pehlke DR, Schr€ooter M, Sheu BJ. Accurate modeling and parameter extraction for MOS transistors validup to 10 GHz. IEEE Trans Electron Dev 1999;46(11):2217–27.
[16] Enz CC, Cheng Y. MOS transistor modeling for RF IC design. IEEE Trans Solid-State Circ 2000;35(2):186–201. [17] Kolding TE. Calculation of MOSFET input gate
imped-ance. Technology report of RISC. 1998.
[18] Joardar K. A simple approach to modeling cross-talk in integratedcircuits. IEEE J Solid-State Circ 1994;29(10): 1212–9.
[19] Joardar K. Signal isolation in BiCMOS mixed mode integratedcircuits. In: IEEE Proc Bipolar/BiCMOS Circ Tech Meeting, 1995. p. 178–81.
[20] Kolding TE. Test structure for universal estimation of MOSFET substrate effects at gigahertz frequencies. In: IEEE Proc Bipolar/BiCMOS Circ Tech Meeting, 2000. p. 106–11.
[21] Koolen MCAM, Geelen JAM, Versleijen MPJG. An improved de-embedding technique for on-wafer high-frequency characterization. In: IEEE Proc Bipolar/BiC-MOS Circ Tech Meeting, 1991. p. 188–91.
[22] Manku T. Microwave CMOS––device physics and design. IEEE J Solid-State Circ 1999;34(3):277–85.
[23] Taur Y, WindS, Mii YJ, Lii Y, Moy D, Jenkins KA, et al. High performance 0.1 mm CMOS devices with 1.5 V power supply. In: IEEE IEDM, 1993. p. 127–30. [24] Biber C, Morf T, Benedickter H, Lott U, Bachtold W.
Microwave frequency measurements andmodeling of MOSFETs on low resistivity silicon substrate. In: Proc IEEE Int Conf Microelectronic Test Structure, 1996. p. 211–5.
[25] Nakahara Y, Yano H, Hirayama T, Suzuki Y, Furukawa A. Impact of interconnect capacitance reduction on RF-Si device performance. In: IEEE IEDM, 1999. p. 861–4. [26] Momose HS, Morifuji E, Yoshitomi T, Ohguro T, Saito
1.5-nm gate oxide CMOS. IEEE Trans Electron Dev 2001;48:1165–74.
[27] Saito M, Ono M, Fujimoto R, Tanimoto H, Ito N, Yoshitomi T, et al. 0.15-mm RF CMOS technology compatible with logic CMOS for low-voltage operation. IEEE Trans Electron Dev 1998;45:737–42.
[28] Woerlee PH, Knitel MJ, van Langevelde R, B.M. Klaassen D, Tiemeijer LF, Scholten AJ, et al. RF-CMOS perfor-mance trends. IEEE Trans Electron Dev 2001;48:1776–82. [29] Su JG, Hsu HM, Wong SC, Chang CY, Huang TY, Sun YC. The dimensional analysis of RF performance in 0.13 lm CMOS technology for MMIC. IEEE J Solid-State Circ, submittedfor publication.
[30] Mason SJ. Power gain in feedback amplifiers. IRE Trans Circuit Theory 1954;CT-1:20–5.
[31] Zamdmer N, Ray A, Plouchart JO, Wagner L, Fong N, Jenkins KA, et al. A 0.13-lm SOI CMOS technology for low-power digital and RF applications. In: Symp VLSI Tech Dig, 2001. p. 85–6.
[32] Klein P. An analytical thermal noise model of deep submicron MOSFET’s. IEEE Electron Dev Lett 1999; 20(8):399–401.
[33] van der Ziel A. Noise in solid-state devices and circuits. New York: John Wiley andSons; 1986.
[34] Abidi A. High-frequency noise measurements on FET’s with small dimensions. IEEE Trans Electron Dev 1986; ED-33(11):1801–5.
[35] Wang B, Hellums JR, Sodini CG. MOSFET thermal noise modeling for analog integrated circuits. IEEE J Solid-State Circ 1994;29(7):833–5.
[36] Triantis DP, Birbas AN, Kondis D. Thermal noise modeling for short-channel MOSFET’s. IEEE Trans Electron Dev 1996;43(11):1950–5.
[37] Jindal RP. Distributed substrate resistance noise in fine-line NMOS field-effect transistors. IEEE Trans Electron Dev 1985;ED-32(11):2450–3.
[38] Jindal RP. High-frequency noise in fine line NMOS field effect transistors. In: Proc IEDM, 1985. p. 68–71. [39] Aufinger K, B€oock J. A straightforward noise de-embedding
methodandits application to high-speedsilicon bipolar transistors. In: Proc ESSDERC, 1996. p. 957–60. [40] Biber CE, Schmatz ML, Morf T, Lott U, Morifuji E,
B€aachtold W. Technology independent degradation of mini-mum noise figure due to pad parasitics. In: IEEE Symp Microwave Theory Tech, 1998. p. 145–8.
[41] Chen CH, Deen MJ. A general procedure for high-frequency noise parameter de-embedding of MOSFETs by taking the capacitive effects of metal interconnections into account. In: Int Conf Microelectron Test Struct, vol. 14, March 2001. p. 109–14.
[42] Chen CH, Deen MJ. A general noise and S-parameter deembedding procedure for on-wafer high-frequency noise measurements of MOSFETs. IEEE Trans Microwave Theory Tech 2001;49(5):1004–5.
[43] Sze SM. Physics of semiconductor devices. New York: John Wiley andSons; 1981.
[44] Chang K. Microwave solid-state circuits and application. New York: John Wiley andSons; 1994.
[45] Burghartz JN, Soyuer M, Jenkins KA. IntegratedRF and microwave components in BiCMOS technology. IEEE Trans Electron Dev 1996;43(9):1559–70.
[46] Lee TH. The design of CMOS radio-frequency integrated circuits. USA: Cambridge University Press; 1998. [47] Porret AS, Melly T, Enz CC, Vittoz EA. Design of high-Q
varactors for low-power wireless applications using a standard CMOS process. IEEE J Solid-State Circ 2000; 35(3):337–45.
[48] Svelto F, Erratico P, Manzini S, Castello R. A metal-oxide-semiconductor varactor. IEEE Electron Dev Lett 1999;20(4):164–6.
[49] FloydBA, Hung CM, O KK. The effects of sub-strate resistivity on RF component andcircuit perfor-mance. In: Proc IEEE Interconnect Tech Conf, 2000. p. 164–6.
[50] NiknejadAM, Meyer RG. Analysis, design, andoptimi-zation of spiral inductors and transformers for Si RF IC’s. IEEE J Solid-State Circ 1998;33(10):1470–81.
[51] Gray PR, Meyer RG. Future directions in silicon ICs for RF personal communications. In: Proc Custom Integrated Circ Conf, 1995. p. 83–90.
[52] Ashby KB, Koullias IA, Finley WC, Bastetek JJ, Moinian S. High Q inductors for wireless applications in a comple-mentary silicon bipolar process. IEEE J Solid-State Circ 1996;31(1):4–9.
[53] Burghartz JN, Soyuer M, Jenkins KA. Microwave induc-tors andcapaciinduc-tors in standardmultilevel interconnect silicon technology. IEEE Trans Microwave Theory Tech 1996;44(1):100–4.
[54] Laker KR, Sansen WMC. Design of analog integrated circuits andsystems. New York: McGraw-Hill; 1994. p. 156.
[55] Zanchi A, Samori C, Levantino S, Lacaita AL. A 2-V 2.5-GHz––104-dBc/Hz at 100 kHz fully integrated VCO with wide-band low-noise automatic amplitude control loop. IEEE J Solid-State Circ 2001;36(4):611–9.
[56] Lopez-Villegas JM, Samitier J, Cane C, Losantos P, Bausells J. Improvement of quality factor of RF integrated inductors by layout optimization. In: IEEE Symp RFIC, 1998. p. 169–72.
[57] Lopez-Villegas JM, Samitier J, Cane C, Losantos P, Bausells J. Improvement of quality factor of RF integrated inductors by layout optimization. IEEE Trans Microwave Theory Tech 2000;48(1):76–83.
[58] Park M, Kim CH, Kim CS, Park MY, Kim SD, Youn YS, et al. Frequency-dependent series resistance of monolithic spiral inductors. IEEE Microwave Guided Wave Lett 1999;9(12):514–6.
[59] Hsu HM, Su JG, Wong SC, Sun YC, Chang CY, Huang TY, et al. Silicon integratedhigh performance inductors in a 0.18 lm CMOS technology for MMIC. In: IEEE VLSI Circ Symp, 2001. p. 199–200.
[60] Yue CP, Wong SS. On-chip spiral inductors with patterned ground shields for Si-based RF ICs. IEEE J Solid-State Circ 1998;33(5):743–52.
[61] Christensen KT. Design andcharacterization of vertical mesh capacitors in standard CMOS. In: IEEE VLSI Circ Symp, 2001. p. 201–2.
[62] Ono M, Suematsu N, Kubo S, Iyama Y, Takagi T, Ishida O. A 1.9 GHz/5.8 GHz-bandon-chip matching Si-MMIC low noise amplifiers fabricatedon high resistive Si sub-strate. In: Tech Dig Int Microwave Symp (IMS), vol. 2, 1999. p. 493–6.
