以四埠散射參數量測射頻金氧半電晶體特性並製作其高頻等效電路模型

180  Download (0)

全文

(1)國 立 交 通 大 學 電子工程學系電子研究所. 博 士 論 文. 以四埠散射參數量測射頻金氧半電晶體特性並製 作其高頻等效電路模型 Characterization and Modeling of RF MOSFET’s Based on Four-Port Scattering-Parameter Measurement. 研 究 生 :吳師道 指導教授 :張俊彥 博士. 中華民國 九十四 年 七 月.

(2) 以四埠散射參數量測射頻金氧半電晶體特性並製作其高頻 等效電路模型 Characterization and modeling of RF MOSFET’s Based on Four-Port Scattering-Parameter Measurement. 研 究 生:吳師道. Student:Shih-Dao Wu. 指導教授:張俊彥 博士. Advisor:Dr. Chun-Yen Chang. 國立交通大學 電子工程學系 電子研究所 博 士 論 文. A Dissertation Submitted to Department of Electronics Engineering & Institute of Electronics College of Electrical Engineering and Computer Science National Chiao Tung University in partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy In Electronics Engineering June 2005 Hsinchu, Taiwan, Republic of China. 中華民國九十四年六月.

(3) 以四埠散射參數量測射頻金氧半電晶體特性並製作其高頻 等效電路模型. 學生:吳師道. 指導教授:張俊彥 博士. 國立交通大學 電子工程學系 電子研究所. 摘. 要. 先進的互補金氧半製程使得射頻金氧半電晶體成為製造快速成長的無 線通訊產品的候選者之一,以金氧半電晶體設計無線通訊電路,將有 希望把無線通訊系統中的前端射頻模組、基頻電路、數位處理電路三 部分整合在單一晶片中,如此不但可降低生產成本,也增加了通訊產 品的可攜性。然而以金氧半電晶體設計射頻電路具有一定的挑戰性, 因為元件內部會產生複雜的訊號耦合,特別是基板的部分,因此提供 可以準確預測元件高頻特性的元件模型供電路設計者使用,是當前的 要務。傳統雙埠量測方式並無法有效的完整探測四端點金氧半電晶體 特性,通常必須將金氧半電晶體設定為共源組態,將源極和基板連接 在一起並接地,以配合雙埠量測系統,如此將無法量測源極與基板之 間的訊號耦合效應,也無法將汲極與基板間的耦合效應從汲極的輸出 特性中分離。本論文提出並實現了以四埠散射參數在晶量測金氧半電 晶體的量測方式。 在本論文中,首先重新整理基本的單埠散射參數原理,並將其觀念延 i.

(4) 伸至多埠的應用,另外也簡介了本研究所使用的四埠參數量測系統及 其校正的原理。 接著提出了四埠量測所使用的在晶量測結構,包括了去除量測結構本 身寄生效應的傀儡結構,並發展了去除量測結構寄生效應的方法。利 用這些四埠測試結構,實現了以四埠參數量測射頻電晶體的構想,一 次的四埠參數量測,即可獲得電晶體操作在共源、共閘、共汲的高頻 特性。 此外本論文也提出了具有合理基板電容電阻寄生元件的金氧半電晶體 小訊號等效電路模型,並根據四埠量測所得的金氧半電晶體高頻特 性,發展粹取小訊號等效電路模型中各元件參數值之方法,實驗中並 粹取了不同尺寸的金氧半電晶體等效電路模型中的相關參數,粹取得 隨元件尺寸縮小放大的模型參數。 最後,將小訊號等效墊路模型以及根據四埠量測資料粹取出的電路參 數以電路模擬軟體模擬其輸出特性,並將此模擬特性與實際量測的高 頻特性比較,在 100MHz 到 20GHz 的量測頻率範圍內,獲得優良的模 擬結果。. ii.

(5) Characterization and modeling of RF MOSFET’s Based on Four-Port Scattering-Parameter Measurement student:Shih-Dao Wu. Advisors:Dr. Chun-Yen Chang. Department of Electronics Engineering and Institute of Electronics National Chiao Tung University. ABSTRACT. With superior advancement of CMOS technologies, RF MOSFET’s have become an important candidate for the rapid growing wireless communication applications. Communication applications base on COMS technologies are potential to integrate the RF front end, base-band and DSP module together on a single chip, which not only improve the production cost but also the portability of modern communication applications. However, designing RF circuit base on CMOS devices is a challenge since the complex signal coupling inside the device, especially the substrate coupling effect. Therefore, establishing a model accurately predicts the RF behaviors of CMOS devices is an urgent mission. The traditional two-port characterization method is inefficient to investigate the detail RF behavior of a four terminal MOSFET. The MOSFET is a device with four terminals and will be always arranged in two-port common source configuration with its source and body grounded to fit the traditional two-port measurement system. Tying the source and body together iii.

(6) will result in some consequences that the coupling path between the source and body will not be able to be characterized and the coupling between drain and body will not be able to separated from the output characteristics either. In this thesis, the four-port S-parameter measurement was proposed and demonstrated for the usage of on-wafer characterization of RF MOSFET’s. First of all, the basic principles of one-port scattering parameter were reviewed and were extended for multi-port application. The four-port system was also introduced including the calibration methodology. Next, the four-port test structures for characterizing RF MOSFET’s including dummy structures were proposed. The corresponding de-embedding method was also developed. With the proposed test structures and MOSFET device, the RF characteristics of the MOSFET configured in common source, common gate, and common drain mode was characterized at one four-port measurement procedure. Then, small-signal equivalent circuits with reasonable substrate R-C network for device in different operation mode were proposed and discussed. Extraction methods of the components in these equivalent circuits according to the four-port measurement data were deduced in detail. The extractions of the components for devices in different dimensions were also demonstrated, good scalability of the extracted values with the device dimensions was observed. Finally, the output characteristics of the proposed small-signal equivalent circuits were simulated according to the components extracted from the four-port measurement. The simulated results were compared with the measurement data; good agreement of the Y-parameters from 100MHz to 20GHz was obtained, which suggest the feasibility of applying four-port on-wafer measurement for characterizing RF MOSFET’s.. iv.

(7) Contents Chinese Abstract ................................................................................................................i English Abstract ...............................................................................................................iii Figure Captions .................................................................................................................v Table Captions ................................................................................................................xiii Chapter 1 Introduction ...................................................................................................1 Chapter 2 Multi-Port Scattering Parameters and Four-Port Measurement System .................................................................................7 2.1 Introduction ...................................................................................................7 2.2 Multi-Port Scattering Parameters ...............................................................8 2.3 Four-Port Measurement System ................................................................16 2.3.1 Four-Port Measurement System ...........................................................16 2.3.2 Calibration ............................................................................................16 2.4 Summary ......................................................................................................18. Chapter 3 Characterizing RF MOSFET’s by Four-Port Measurement .....25 3.1 Motivation ....................................................................................................25 3.2 Four-Port RF MOSFET’s ...........................................................................26 3.3 Dummy Structures and De-Embedding Procedure..................................27 3.4 Four-Port Y-parameters and Port Reduction ...........................................29 3.5 Measurement Results and Discussions ......................................................30 3.5.1 Measurement Results of Devices with Different Dimensions..............30 3.5.2 Two-Port Scattering Parameter of The Common Source, Common Drain, and Common Gate RF MOSFET,s ............................................32 3.6 Summary ......................................................................................................35. Chapter 4 Small-Signal Equivalent Circuit Model of RF MOSFET and Parameter Extraction...............................................................................59 v.

(8) 4.1 Motivation ....................................................................................................59 4.2 Small-Signal Equivalent Circuits of RF MOSFET’s................................61 4.3 Parameter Extraction..................................................................................64 4.3.1 Extraction of Extrinsic Parasitic Components in the Equivalent circuit of Cold MOSFET’s...............................................................................64 4.3.2 Extraction of Components in the Equivalent Circuit of MOSFET’s in Linear Region .......................................................................................68 4.3.3 Extraction of intrinsic components in saturation region.......................69 4.4 Results and Discussions...............................................................................72 4.4.1 Extractied Results of Cold Devices ......................................................73 4.4.2 Extracted Results of Devices Linear Region........................................74 4.4.3 Extracted Results of Saturation Devices ..............................................76 4.5 Summary ......................................................................................................77. Chapter 5 Verification of Small-Signal Equivalent Circuit Model .............135 5.1 Motivation ..................................................................................................135 5.2 Simulation of the Equivalent Circuits .....................................................135 5.3 Results and Discussions.............................................................................136 5.4 Summary ....................................................................................................139. Chapter 6 Conclusion and Suggestions for Future Works ............................157 6.1 Conclusion of This Study ..........................................................................157 6.2 Suggestions for Future Works ..................................................................158. References .......................................................................................................................159 Publication List .............................................................................................................163. vi.

(9) Figure Captions. Chapter 1. Fig.1.1. (a) Conventional two-port test structure for common source MOSFET. (b) Fictional two-port test structure for common gate MOSFET. (c) Fictional two-port test structure for common drain MOSFET.. Chapter 2. Fig.2.1. One port network.. Fig.2.2 Generator with conjugate matched load used to define “incident” components Ii and Vi. Fig.2.3 An n-port network with generators. Fig.2.4 Agilent N1957B Physical Layer Test System. Fig.2.5 Architecture of VNA test ports and the systematic errors. Fig.2.6 The full 4-port error model and the 48 error terms.. Chapter 3. Fig.3.1 (a) Schematics of test structure and the RF MOSFET. (b) The top view photograph of the test structure and the RF MOSFET. Fig.3.2 Test structure for the four-port measurement. Fig.3.3 OPEN dummy structure for the four-port measurement. Fig.3.4 The equivalent circuit of the test structure.. v.

(10) Fig.3.5 SHORT dummy structure for the four-port measurement. Fig.3.6 The difference of input admittance at port2 (body signal pad) between the open dummy shown in Fig.3.3 and an ordinary open dummy without substrate contact ring. Fig.3.7 SGG, SDD, SSS, and SBB of M1( 3.6µ m × 4 ), M2( 7.2 µ m × 4 ), and M3(12 µ m × 4 ). devices, which are biased at VG=VD=1V. Fig.3.8 SGB of M1( 3.6µ m × 4 ), M2( 7.2 µ m × 4 ), and M3(12 µ m × 4 ) devices, which are biased at VG=VD=1V. Fig.3.9 SGD of M1( 3.6µ m × 4 ), M2( 7.2µ m × 4 ), and M3(12 µ m × 4 ) devices, which are biased at VG=VD=1V. Fig.3.10 SGS of M1( 3.6µ m × 4 ), M2( 7.2µ m × 4 ), and M3(12 µ m × 4 ) devices, which are biased at VG=VD=1V. Fig.3.11 SBG of M1( 3.6µ m × 4 ), M2( 7.2 µ m × 4 ), and M3(12 µ m × 4 ) devices, which are biased at VG=VD=1V. Fig.3.12 SBD of M1( 3.6µ m × 4 ), M2( 7.2 µ m × 4 ), and M3(12 µ m × 4 ) devices, which are biased at VG=VD=1V. Fig.3.13 SBS of M1( 3.6µ m × 4 ), M2( 7.2 µ m × 4 ), and M3(12 µ m × 4 ) devices, which are biased at VG=VD=1V. Fig.3.14 SDG and SSG of M1( 3.6µ m × 4 ), M2( 7.2µ m × 4 ), and M3(12 µ m × 4 ) devices, which are biased at VG=VD=1V. Fig.3.15 SDB and SSB of M1( 3.6µ m × 4 ), M2( 7.2 µ m × 4 ), and M3(12 µ m × 4 ) devices, which are biased at VG=VD=1V. Fig.3.16 SSD and SDS of M1( 3.6µ m × 4 ), M2( 7.2 µ m × 4 ), and M3(12 µ m × 4 ) devices, which are biased at VG=VD=1V. Fig.3.17 SGG and SDD of M1( 3.6µ m × 4 ), M2( 7.2µ m × 4 ), and M3(12 µ m × 4 ) devices in common source configuration, which are biased at VG=VD=1V. vi.

(11) Fig.3.18 SDG and SGD of M1( 3.6µ m × 4 ), M2( 7.2µ m × 4 ), and M3(12 µ m × 4 ) devices in common source configuration, which are biased at VG=VD=1V. Fig.3.19 SGG and SSS of M1( 3.6µ m × 4 ), M2( 7.2 µ m × 4 ), and M3(12 µ m × 4 ) devices in common drain configuration, which are biased at VG=VD=1V. Fig.3.20 SGS and SSG of M1( 3.6µ m × 4 ), M2( 7.2 µ m × 4 ), and M3(12 µ m × 4 ) devices in common drain configuration, which are biased at VG=VD=1V. Fig.3.21 SSS and SDD of M1( 3.6µ m × 4 ), M2( 7.2 µ m × 4 ), and M3(12 µ m × 4 ) devices in common gate configuration, which are biased at VG=VD=1V. Fig.3.22 SDS and SSD of M1( 3.6µ m × 4 ), M2( 7.2 µ m × 4 ), and M3(12 µ m × 4 ) devices in common gate configuration, which are biased at VG=VD=1V. Fig.3.23 The common source S-parameters obtained from a 4-port NMOSFET and a conventional 2-port NMOSFET biased at VG=VD=1V. The gate widths of these two devices are 7.2µ m × 4 .. Chapter 4 Fig.4.1 The cross-sectional structure and top view of a four-terminal MOSFET. Fig.4.2 The small signal equivalent circuit of a four-terminal RF MOSFET including the intrinsic and extrinsic parts. Fig.4.3 The small signal equivalent circuit of a cold MOSFET, in which the intrinsic part of the MOSFET is neglected. Fig.4.4 The small signal equivalent circuit of a cold MOSFET with RS and RD neglected. Fig.4.5 The small signal equivalent circuit of a MOSFET biased in linear region. Fig.4.6 The small signal equivalent circuit of a saturated MOSFET with the RS and RD neglected. Fig.4.7 The measured Re[YGG] and Im[YGG] of M1( 3.6µ m × 4 ), M2( 7.2µ m × 4 ), and M3(12 µ m × 4 ) devices, which are biased at VG=VD=VS=VB=0. vii.

(12) Fig.4.8 The measured Im[YDG] and Im[YSG] of M1( 3.6µ m × 4 ), M2( 7.2µ m × 4 ), and M3(12 µ m × 4 ) devices, which are biased at VG=VD=VS=VB=0. Fig.4.9 (a) The measured Im[YBD] and Im[YBS] of M1( 3.6µ m × 4 ), M2( 7.2 µ m × 4 ), and M3(12 µ m × 4 ) devices, which are biased at VG=VD=VS=VB=0. (b) The measured Re[YBD] and Re[YBS] of M1( 3.6µ m × 4 ), M2( 7.2 µ m × 4 ), and M3(12 µ m × 4 ) devices, which are biased at VG=VD=VS=VB=0. Fig.4.10 (a) The measured Im[YGB] of M1( 3.6µ m × 4 ), M2( 7.2 µ m × 4 ), and M3(12 µ m × 4 ) devices, which are biased at VG=VD=VS=VB=0. (b) The measured Re[YGB] of M1( 3.6µ m × 4 ), M2( 7.2 µ m × 4 ), and M3(12 µ m × 4 ) devices, which are biased at VG=VD=VS=VB=0. Fig.4.11 The extracted CGSO and CGDO of M1( 3.6µ m × 4 ), M2( 7.2µ m × 4 ), and M3(12 µ m × 4 ) devices, which are biased at VG=VD=VS=VB=0. Fig.4.12 -Im[YSB]/ω of M1( 3.6µ m × 4 ), M2( 7.2 µ m × 4 ), and M3(12 µ m × 4 ) devices, which are biased at VG=VD=VS=VB=0. Fig.4.13 The extracted CSBO and CSBE of M1( 3.6µ m × 4 ), M2( 7.2µ m × 4 ), and M3(12 µ m × 4 ) devices, which are biased at VG=VD=VS=VB=0. Fig.4.14 The extracted CDBO and CDBE of M1( 3.6µ m × 4 ), M2( 7.2µ m × 4 ), and M3(12 µ m × 4 ) devices, which are biased at VG=VD=VS=VB=0. Fig.4.15 The extracted CGBO and CGBE of M1( 3.6µ m × 4 ), M2( 7.2µ m × 4 ), and M3(12 µ m × 4 ) devices, which are biased at VG=VD=VS=VB=0. Fig.4.16 The extracted RSB and RDB of M1( 3.6µ m × 4 ), M2( 7.2 µ m × 4 ), and M3(12 µ m × 4 ) devices, which are biased at VG=VD=VS=VB=0. Fig.4.17 The extracted RGB of M1( 3.6µ m × 4 ), M2( 7.2 µ m × 4 ), and M3(12 µ m × 4 ) devices, which are biased at VG=VD=VS=VB=0. Fig.4.18 The extracted RSDB of M1( 3.6µ m × 4 ), M2( 7.2 µ m × 4 ), and M3(12 µ m × 4 ) devices, which are biased at VG=VD=VS=VB=0. viii.

(13) Fig.4.19 (a) The extracted CGS of M1( 3.6µ m × 4 ) biased at different VG. (b) The extracted CGS of M2( 7.2µ m × 4 ) biased at different VG. (c) The extracted CGS of M3(12 µ m × 4 ) biased at different VG. Fig.4.20 (a) The extracted CGD of M1( 3.6µ m × 4 ) biased at different VG. (b) The extracted CGD of M2( 7.2µ m × 4 ) biased at different VG. (c) The extracted CGD of M3(12 µ m × 4 ) biased at different VG. Fig.4.21 (a) The extracted –Im[YGB]/ω of M1( 3.6µ m × 4 ) biased at different VG. (b) The extracted –Im[YGB]/ω of M2( 7.2µ m × 4 ) biased at different VG. (c) The extracted –Im[YGB]/ω of M3(12 µ m × 4 ) biased at different VG. Fig.4.22 (a) The extracted RG of M1( 3.6µ m × 4 ) biased at different VG. (b) The extracted RG of M2( 7.2µ m × 4 ) biased at different VG. (c) The extracted RG of M3(12µ m × 4 ) biased at different VG. Fig.4.23 (a) The extracted RCH+RS+RD of M1( 3.6µ m × 4 ) biased at different VG. (b) The extracted RCH+RS+RD of M2( 7.2µ m × 4 ) biased at different VG. (c) The extracted RCH+RS+RD of M3(12 µ m × 4 ) biased at different VG. (d) RCH+RS+RD versus (VG − VTH ). −1. of M1( 3.6µ m × 4 ), M2( 7.2µ m × 4 ), and. M3(12 µ m × 4 ). Fig.4.24 (a) The extracted CSB of M1( 3.6µ m × 4 ) biased at different VG. (b) The extracted CSB of M2( 7.2µ m × 4 ) biased at different VG. (c) The extracted CSB of M3(12 µ m × 4 ) biased at different VG. Fig.4.25 (a) The extracted CSBE of M1( 3.6µ m × 4 ) biased at different VG. (b) The extracted CSBE of M2( 7.2µ m × 4 ) biased at different VG. (c) The extracted CSBE of M3(12 µ m × 4 ) biased at different VG. Fig.4.26 (a) The extracted CDB of M1( 3.6µ m × 4 ) biased at different VG. (b) The extracted CDB of M2( 7.2µ m × 4 ) biased at different VG.. ix.

(14) (c) The extracted CDB of M3(12 µ m × 4 ) biased at different VG. Fig.4.27 (a) The extracted CSBE of M1( 3.6µ m × 4 ) biased at different VG. (b) The extracted CSBE of M2( 7.2µ m × 4 ) biased at different VG. (c) The extracted CSBE of M3(12 µ m × 4 ) biased at different VG. Fig.4.28 (a) The extracted CGB of M1( 3.6µ m × 4 ) biased at different VG. (b) The extracted CGB of M2( 7.2µ m × 4 ) biased at different VG. (c) The extracted CGB of M3(12 µ m × 4 ) biased at different VG. Fig.4.29 (a) The extracted CGBE of M1( 3.6µ m × 4 ) biased at different VG. (b) The extracted CGBE of M2( 7.2µ m × 4 ) biased at different VG. (c) The extracted CGBE of M3(12 µ m × 4 ) biased at different VG. Fig.4.30 (a) The extracted RSB of M1( 3.6µ m × 4 ) biased at different VG. (b) The extracted RSB of M2( 7.2µ m × 4 ) biased at different VG. (c) The extracted RSB of M3(12 µ m × 4 ) biased at different VG. Fig.4.31 (a) The extracted RDB of M1( 3.6µ m × 4 ) biased at different VG. (b) The extracted RDB of M2( 7.2µ m × 4 ) biased at different VG. (c) The extracted RDB of M3(12 µ m × 4 ) biased at different VG. Fig.4.32 (a) The extracted CGS and CGD of saturation M1( 3.6 µ m × 4 ). (b) The extracted CGS and CGD of saturation M2( 7.2 µ m × 4 ).. (c) The extracted CGS and CGD of saturation M3(12 µ m × 4 ). Fig.4.33 (a) The extracted gm and gmb of saturation M1( 3.6µ m × 4 ). (b) The extracted gm and gmb of saturation M2( 7.2 µ m × 4 ). (c) The extracted gm and gmb of saturation M3(12 µ m × 4 ). Fig.4.34 (a) The extracted Cm and Cmb of saturation M1( 3.6µ m × 4 ). (b) The extracted Cm and Cmb of saturation M2( 7.2µ m × 4 ). (c) The extracted Cm and Cmb of saturation M3(12 µ m × 4 ). Fig.4.35 (a) The extracted RG of saturation M1( 3.6µ m × 4 ). x.

(15) (b) The extracted RG of saturation M2( 7.2µ m × 4 ). (c) The extracted RG of saturation M3(12 µ m × 4 ). Fig.4.36 (a) The extracted CSB and CDB of saturation M1( 3.6µ m × 4 ). (b) The extracted CSB and CDB of saturation M2( 7.2µ m × 4 ). (c) The extracted CSB and CDB of saturation M3(12 µ m × 4 ). Fig.4.37 (a) The extracted RSB and RDB of saturation M1( 3.6µ m × 4 ). (b) The extracted RSB and RDB of saturation M2( 7.2µ m × 4 ). (c) The extracted RSB and RDB of saturation M3(12 µ m × 4 ).. Chapter 5 Fig.5.1 (a) Measured and simulated Im[YGG] of M1, M2, and M3 biased VG=VD=1V. (b) Measured and simulated RE[YGG] of M1, M2, and M3 biased VG=VD=1V. Fig.5.2 (a) Measured and simulated Im[YDD] of M1, M2, and M3 biased VG=VD=1V. (b) Measured and simulated RE [YDD] of M1, M2, and M3 biased VG=VD=1V. Fig.5.3 (a) Measured and simulated Im[YSS] of M1, M2, and M3 biased VG=VD=1V. (b) Measured and simulated RE[YSS] of M1, M2, and M3 biased VG=VD=1V. Fig.5.4 (a) Measured and simulated Im[YBB] of M1, M2, and M3 biased VG=VD=1V. (b) Measured and simulated RE[YBB] of M1, M2, and M3 biased VG=VD=1V. Fig.5.5 (a) Measured and simulated Im[YGD] of M1, M2, and M3 biased VG=VD=1V. (b) Measured and simulated RE[YGD] of M1, M2, and M3 biased VG=VD=1V. Fig.5.6 (a) Measured and simulated Im[YGS] of M1, M2, and M3 biased VG=VD=1V. (b) Measured and simulated RE[YGS] of M1, M2, and M3 biased VG=VD=1V. Fig.5.7 (a) Measured and simulated Im[YGB] of M1, M2, and M3 biased VG=VD=1V. (b) Measured and simulated Re [YGB] of M1, M2, and M3 biased VG=VD=1V. Fig.5.8 (a) Measured and simulated Im[YBG] of M1, M2, and M3 biased VG=VD=1V. (b) Measured and simulated Re [YBG] of M1, M2, and M3 biased VG=VD=1V. xi.

(16) Fig.5.9 (a) Measured and simulated Im[YBD] of M1, M2, and M3 biased VG=VD=1V. (b) Measured and simulated Re [YBD] of M1, M2, and M3 biased VG=VD=1V. Fig.5.10 (a) Measured and simulated Im[YBS] of M1, M2, and M3 biased VG=VD=1V. (b) Measured and simulated Re [YBS] of M1, M2, and M3 biased VG=VD=1V. Fig.5.11 (a) Measured and simulated Im[YDG] of M1, M2, and M3 biased VG=VD=1V. (b) Measured and simulated Re[YDG] of M1, M2, and M3 biased VG=VD=1V. Fig.5.12 (a) Measured and simulated Im[YDB] of M1, M2, and M3 biased VG=VD=1V. (b) Measured and simulated Re [YDB] of M1, M2, and M3 biased VG=VD=1V. Fig.5.13 (a) Measured and simulated Im[YDS] of M1, M2, and M3 biased VG=VD=1V. (b) Measured and simulated Re[YDS] of M1, M2, and M3 biased VG=VD=1V. Fig.5.14 (a) Measured and simulated Im[YSG] of M1, M2, and M3 biased VG=VD=1V. (b) Measured and simulated Re[YSG] of M1, M2, and M3 biased VG=VD=1V. Fig.5.15 (a) Measured and simulated Im[YSB] of M1, M2, and M3 biased VG=VD=1V. (b) Measured and simulated RE[YSB] of M1, M2, and M3 biased VG=VD=1V. Fig.5.16 (a) Measured and simulated Im[YSD] of M1, M2, and M3 biased VG=VD=1V. (b) Measured and simulated RE[YSD] of M1, M2, and M3 biased VG=VD=1V.. xii.

(17) Table Caption. Chapter 5 Table 5.1. (a) The extracted values of the components for the small-signal equivalent circuit model of M1 devices ( 3.6µ m × 4 ).. (b) The extracted values of the components for the small-signal equivalent circuit model of M2 devices ( 7.2µ m × 4 ). (c) The extracted values of the components for the small-signal equivalent circuit model of M3 devices (12µ m × 4 ).. xiii.

(18) Chapter 1 Introduction 1.1 Introduction and motivation The metal-oxide-semiconductor field-effect transistor (MOSFET) is the most important device for VLSI, ULSI circuits such as microprocessors and semiconductor memories. It has many acronyms including IGFET (insulated-gate field-effect transistor), MISFET (metalinsulator-semiconductor field-effect transistor), and MOST (metal-oxide-semiconductor transistor). The principle of the surface field-effect transistor was first proposed in the early 1925 by Julius Lilienfeld [1], but he never constructed a working device. Before co-inventing the bipolar transistor, William Shockley also tried to modulate the conductivity of a semiconductor to create a field-effect transistor [2], however, problems with his materials system, copper oxide, prevented his success. In 1960, Kahng and Atalla [3]-[4] proposed and fabricated the first MOSFET using a thermally oxidized silicon structure. Than the basic device characteristics, device physics, and applications were widely studied and reviewed. Traditionally, the high frequency properties of silicon MOSFETs have been considered inferior to other technologies, including silicon bipolar transistors and transistors based on ⅢⅤmaterials such as gallium arsenide. However, the CMOS technology has now reached a state of evolution, in terms of both frequency and noise, where it is becoming a serious contender for radio frequency applications in the GHz range. Nowadays, the cutoff frequency of deep-submicron CMOS processes typically reaches 100GHz for 0.13mm technology making them capable to operate well into GHz range which covers many popular wireless products such as cell phones, global position system, Bluetooth. Adopting CMOS processes to radio frequency applications has great benefits of low cost, high-level integration, and the ability to combine the RF front-end and base band circuits together [5]-[7].. 1.

(19) An important issue on adopting CMOS for RF applications is the availability of accurate model of RF CMOS for circuit design. However, differences between the RF MOSFET and conventional high frequency transistors make the proper modeling of RF MOSFET complicated and difficult. Two major differences exist; one is related to the substrate materials. MOSFET’s are fabricated on a silicon substrate, which lacks of semi-insulating property as a gallium arsenide substrate. Essentially, the intrinsic resistivity of silicon ( 2.3 × 105 ohm-cm) is much lower lower than that of gallium arsenide ( 108 ohm-cm) due to more plentiful carriers in the intrinsic condition. In addition to intrinsic condition, in a practical CMOS process, the silicon substrate is typically doped to have carrier concentration ranging from about 1015 cm-3 to about 1018 cm-3, which corresponds to resistivity of 0.01 to 10 ohm-cm. The lower resistivity of the silicon substrate results in larger and lossier parasitics related to the substrate. The performance of the integrated CMOS RF circuits is often limited by these parasictics. In RF MOSFET’s, the influence of the distributed substrate resistance becomes significant as the operation frequency increases [8]-[12]. At low frequencies, the impedance of the junction capacitance is large that the substrate resistance may not be seen from the drain terminal. However, as operation frequency increases, the impedance of the junction capacitance reduces and the effects of the substrate resistance become obvious. At high frequencies, the signals in RF MOSFET’s are coupled through the substrate R-C network in a complex way. The substrate signal coupling mainly affects the small signal output characteristics, which are important for RF design. The other difference arises form the device structure of MOSFET’s. The conventional high-frequency FET’s have three terminals: a gate, a source, and a drain. Bipolar transistors are also three terminal devices, having an emitter, a base, and a collector. However the MOSFET has a fourth terminal, the body. The body is doped opposite to source and drain regions to isolate these two regions by reverse-biased p-n junctions. The body terminal is typically connected to ground (the lowest potential used in the circuit) for an n-MOSFET and Vdd (the highest potential used in the circuit) for a p-MOSFET to prevent the source and drain junctions from being forward-biased in any case. In many 2.

(20) cases, the source and body of the MOSFET are tied together. Even for this configuration, a MOSFET cannot be treated as a three-terminal device since the potential of the intrinsic body node is neither as the extrinsic body terminal nor as the source. It is much more difficult to explain and predict the behavior of the four-terminal device than that of the three-terminal device. A three-terminal device can be treated as a two-port network, where the four complex numbers are enough to characterize the device. However, nine complex numbers are required to characterize a four-terminal device. In other word, multi-port (at least three-port required) on wafer measurement technique is required, but unfortunately there is still no such solution. In most cases, the test structure of RF MOSFET is usually arranged in common source configuration with the source and body terminals are tied together and grounded. And the device can be characterized by performing an on-wafer S-parameter measurement by a 2-port network analyzer. Figure 1(a) shows the test structure of an RF nMOSFET schematically. Since the source and body are tied together and the 2-port measurement can only provide 4 independent complex s-parameters, the internal coupling between intrinsic source/body and drain/body could not be directly observed according the 2-port measurement data. The coupling effect arisen from the substrate can only be fitted or guessed according limited 2port data. In addition to common source configuration, common gate and common drain condition also appears in RF analog circuits like cascade-type LNA [13]-[15] and transimpedance amplifiers [16]. However, characterizing a MOSFET in common gate (CG) or common drain (CD) configuration by using the traditional 2-port test structure will encounter some problems. Figure 1(b) shows the CG NMOSFET within a traditional 2-port Ground-Signal-Ground RF test structure. In order to operate the device in saturation region, the DC bias voltage applied on gate terminal has to be larger than that applied on the source. However, the body terminal of the device is also connected to the ground metal of the test structure, it will cause the substrate-source junction to be forward biased. There exists the similar situation in common drain configuration shown in Fig. 1(c), the substrate-source junction will be forward biased if. 3.

(21) the applied drain voltage were larger than source voltage. There is another method to obtain CG and CS s-parameters which similar to the method used in BJT. In BJT amplifiers, the 2port network parameters of common base and common collector configurations can be converted from measured common emitter data [17]-[18]. However, unlike BJT’s, MOSFET’s are 4-terminal devices, adopting this method to a MOSFET device may cause error. In real CMOS IC’s, the body terminals are not always connected to source terminals of every single device. In fact, they are connected to the ground for nMOSFET (Vdd for pMOSFET) while source terminals maybe not. The source and body terminals may have voltage drops between them. The traditional 2-port GSG test structure is unable to adapt this bias condition since the source and body are tied together. As discussed above, characterizing a RF MOSFET by using 2-port measurement really limits the further exploration of inside signal coupling behavior of this device. To overcome the insufficiency of 2-port measurement, a multi-port on-wafer measurement technique is required.. 1.2 Organization of the thesis In this thesis, issues about characterization of RF MOSFET’ based on four-port system, parameters extraction for small-signal equivalent circuits, and the performance of the device model will be coverd. In chapter 1, an introduction to this thesis is brief addressed. In chapter2, the basic concepts of the scattering parameters will be reviewed. And the fourport measurement system adopted in this study will be briefly introduced. In chapter 3, the characterization of RF MOSFET’s based on the four-port measurement will be demonstrated. The test structures for the DUT’s and the dummy stuructures for deembedding process will also be addressed.. 4.

(22) In chapter 4, small-signals equivalent circuits for the devices with different bias conditions and the corresponding parameter extractions will be discussed. In chapter 5, the proposed model and the parameters extracted from the four-port measurement will be verified. Finally, conclusions for this thesis and suggestions for future works will be given in chapter 6.. 5.

(23) Ground. Ground B. S. G. S. D. S. Ground. Ground. (a) Common Source. Ground. Ground. B. S. D Signal. Signal. G. Ground. Ground. (b) Common Gate. Ground. Ground B. Signal. G. S. Signal. D. Ground. Ground. (c) Common Drain. Fig.1.1 (a) Conventional two-port test structure for common source MOSFET. (b) Fictional two-port test structure for common gate MOSFET. (c) Fictional two-port test structure for common drain MOSFET.. 6.

(24) Chapter2 Multi-Port Scattering Parameters and Four-Port Measurement System 2.1 Introduction To model an RF MOSFET to the giga-hertz range relies on reliable DC and high- frequency measurement. The characterization of electronic components in the DC domain is relatively simple and only requires a voltmeter and amperemeter. However, characterizing the frequency performance of the device is more complex since it involves the magnitude dependence and phase shift of the currents and voltages on each terminal of an RF MOSFET. The modeling device is operated under its originally intended conditions with DC bias is applied to all the terminals and additional small-signal RF excitation is applied. The sine currents and voltages at all terminals of the device have to be measured, with magnitude and phase. A natural choice for such characterization would be open-circuit impedance characterization (z-parameters), short-circuit admittance characterization (y-parameters), or hybrid characterization (h-parameters) from linear network theory. These parameters can be used to describe the electrical behavior of the device (or network), including any source and load conditions. For such parameters, the voltage or current as a function of frequency and bias at the ports of the device must be measured. However, at high frequency, it is very hard to implement pure “open” or “short” terminations at the device ports. One cannot simply connect a voltmeter or current probe and get accurate measurement due to the parasitic impedances of the test structure and probes themselves. Therefore, some other way of characterizing high-frequency networks is required that doesn’t have these drawbacks. The scattering parameter (s-parameter) that relate to familiar parameters such as gain, loss, and reflection coefficient is developed. The s-parameters are relatively simple to measure, and do not require pure “open”, “short” terminations to the. 7.

(25) device. Different to Y, Z, or H parameters, they relate to the traveling waves that are scattered or reflected when a network is inserted into a transmission line of a certain characteristic impedance Z0. While s-parameters are measured, Z, Y, or H-parameters can all be derived from the measured s-parameters if necessary. At high frequencies above about 1 GHz, S-parameter measurement is the easiest and the most reliable way to measure the network characteristics of a certain functional block. A great number of models and corresponding parameter extraction methods from S-parameter measurement data have been proposed for various kinds of two-port networks such as passive devices and transistors [19]-[23]. In present, the most common system used for s-parameter measurement is 2-port system. Its core is a 2-port network analyzer. However, a multi-port system has similar theory with a multi-port system, and it’s rather simple to extend 2-port concept to multi-port system. In this chapter, the fundamental one-port s-parameter and characterization method will be briefly introduced first. Than the theory of extending one-port s-parameter to multi-port s-parameters will be discussed. Additionally, the methods of transferring multi-port s-parameters to Z-, Y-parameters will also be addressed. Finally, the 4port equipment and calibration method used in this study will be presented.. 2.2 Multi-Port Scattering Parameters Scattering implies causing something to separate into different components, and scattering parameters provide a measure of the degree of separation and the magnitude of different components. Scattering is relatively easy to visualize when the scattered components actually exist. For example, when light falls on an atom, the electronic motions are changed such that light is reemitted. This reemitted light is called scattered light, and its amplitude is related to a scattering constant of the atom. However, the scattering concept is more difficult to visualize when the incident and reflected components do not actually exist. Such is the case for a transistor connects to its load through a lumped matching network. Here it is necessary to define what is meant by “incident” and 8.

(26) ‘reflected” components because they cannot be identified otherwise. Therefore the incident current is defined as the current which the transistor would deliver to a conjugate matched load. The fact that the matching network which is actually connected to the transistor may not necessarily provide a conjugate-matched load. It dose not alter the validity of the incident current definition since the incident current can be different from the actual current delivered to the matching network, their difference is defined as the reflected current. Defining statements are also made for incident and reflected voltages. Therefore, when the scattering concept is applied to lumped circuit, the actual currents and voltages can be separated components according to appropriate definitions. 2.2.1 the one-port network The scattering concept is perhaps best illustrated by considering the one-port network shown in Fig. 2.1. The actual current and voltage are I=. E Z0 + Z L. (1). V=. EZ L Z0 + Z L. (2). and. in which Z0 is considered to be internal impedance of the generator. The incident components are obtained when the generator is connected to a conjugate matched load Z0*, as in Fig. 2.2. Thus Ii =. E E = * Z 0 + Z 0 2 Re Z 0. (3). Vi =. EZ 0* EZ 0* = Z 0 + Z 0* 2 Re Z 0. (4). and. where Re stands for real part of the value. The reflected components are calculated using the defining decomposition equations I = Ii − I r. (5). 9.

(27) and V = Vi − Vr. (6). Using (1) and (3) in (5), the reflected current can be expressed as I r = Ii − I ⎛ Z − Z 0* ⎞ =⎜ L I ⎜ Z + Z ⎟⎟ i 0 ⎠ ⎝ L. (7). = S I Ii. where S I = ( Z L − Z 0* ) ( Z L + Z 0 ) is a current scattering parameter for the one port circuit. Similarly, using (2) and (4) in (6), the reflected voltage can be expressed as Vr = Vi − V =. Z 0 ⎛ Z L − Z 0* ⎞ ⎜ ⎟ Vi Z 0* ⎜⎝ Z L + Z 0 ⎟⎠. =. Z0 I S Vi = SV Vi Z 0*. (8). where SV = ( Z 0 Z 0* ) S I is a voltage scattering parameter for the one-port circuit. It is also readily shown that Vi = Z 0* I i. (9a). Vr = Z 0 I r. (9b). and. The incident and reflected components are related to each other through the impedances and the scattering parameters as defined. Each scattering parameter and reflected component is zero when Z L = Z 0* . The impedance Z0 is often made to be a pure resistance R0 > 0 , so that Z 0 = R0 , and it is used as a normalizing or reference resistance. It is usual to consider the reference resistance equal to 50Ω, particularly if scattering-parameter measurements are made using 50Ω lines and termination. If Z 0 = R0 and Z 0* = R0 , then S I = SV =. Z L − R0 Z L + R0. (10). 10.

(28) For this case the current and voltage scattering parameters of the one-port circuit are equal, and have exactly the same form as the reflection coefficient of a transmission line having a characteristic resistance R0 and terminated in a load ZL. The scattering parameters of the port are equal to zero if its impedence is the same as the reference resistance R0. Also, for this case (9a) and (9b) become Vi = R0 I i. (11a). Vr = R0 I r. (11b). and. 2.2.2 the n-port network the scattering parameters for the n-port network shown in Fig. 2.3 are developed using matrix algebra. It is assumed that the individual generators are independent of each other. This means that the matrix [Z0] representing internal impedances contains no cross-coupling terms, and is given by the diagonal matrix ⎡ Z 01 ⎢ 0 [ Z 0 ] = ⎢⎢ # ⎢ ⎣⎢ 0. 0 Z 02. # 0. 0 ⎤ 0 ⎥ ⎥ # ⎥ ⎥ " Z 0n ⎦⎥ " ". (12). The incident and reflected components at the ports are related to the actual voltages and currents by the column matrices. [ I ] = [ Ii ] − [ I r ]. (13a). [V ] = [Vi ] − [Vr ]. (13a). and. The incident and reflected components are related by. [Vi ] = ⎡⎣ Z0* ⎤⎦ [ Ii ]. (14a). [Vr ] = [ Z0 ][ I r ]. (14b). and. which correspond to the one-port case of (9a) and (9b).. 11.

(29) The open-circuit impedance-parameter relationship for the n-port network is. [V ] = [ z ][ I ]. (15). The incident and reflected components can be determined from (12)-(15) as follows:. [Vr ] = [V ] − [Vi ] = [ z ][ I ] − ⎡⎣ Z0* ⎤⎦ [ Ii ] or. [ Z 0 ][ I r ] = [ z ] ([ I i ] − [ I r ]) − ⎡⎣ Z0* ⎤⎦ [ I i ] Combine terms to obtain. ([ z ] + [ Z0 ]) [ I r ] = ([ z ] − ⎡⎣ Z0* ⎤⎦ ) [ Ii ] Multiply by ([ z ] + [ Z 0 ]). −1. to obtain. [ I r ] = ([ z ] + [ Z0 ]) ([ z ] − ⎡⎣ Z 0* ⎤⎦ ) [ I i ] −1. (16). = ⎡ S I ⎤ [ Ii ] ⎣ ⎦. where ⎡ S I ⎤ = ([ z ] + [ Z 0 ]) ⎣ ⎦. −1. ([ z ] − ⎡⎣ Z ⎤⎦) * 0. (16a). is the current scattering-parameter matrix that is analogous to that for the one-port case given in (7). Similarly, using the short-circuit admittance-parameter relationship. [ I ] = [ y ][V ]. (17). it is found that. [Vr ] = − ([Y0 ] + [ y ]) ([ y ] − ⎡⎣Y0* ⎤⎦ ) [Vi ] −1. = ⎡ SV ⎤ [Vi ] ⎣ ⎦. (18). where. [ y ] = [ z ]−1 , [Y0 ] = [ Z0 ]−1 and ⎡ SV ⎤ = − ([Y0 ] + [ y ]) ⎣ ⎦. −1. ([ y ] − ⎡⎣Y ⎤⎦) * 0. (19). 12.

(30) is the voltage scattering-parameter matrix. 2.2.3 normalized scattering parameters The normalized incident and reflected components is defined as. [a] =. 1 2. ([ Z ] + ⎡⎣ Z ⎤⎦ ). = [ Re Z o ]. 12. 12. * 0. 0. [ Ii ]. (20). [ Ii ]. and. [b ] =. (. 1 [ Z 0 ] + ⎡⎣ Z 0* ⎤⎦ 2. = [ Re Z o ]. 12. ). 12. [ Ir ]. (21). [ Ir ]. where 1 2. ([ Z ] + ⎡⎣ Z ⎤⎦ ) 0. 12. * 0. = [ Re Z o ]. 12. ⎡ Re Z 01 ⎢ ⎢ 0 =⎢ ⎢ # ⎢ 0 ⎣. 0. ". Re Z 02. ". # ". 0. ⎤ ⎥ 0 ⎥ ⎥ # ⎥ Re Z 0 n ⎥⎦ 0. (22). Then combining (16) with (20) and (21) yields. [ Re Z 0 ] [b] = [ I r ] = ⎡⎣ S I ⎤⎦ [ Ii ] −1 2 = ⎡⎣ S I ⎤⎦ [ Re Z 0 ] [ a ] −1 2. Multiplying by [ Re Z 0 ]. 12. yields. [b] = [ Re Z 0 ]. 12. ⎡⎣ S I ⎤⎦ [ Re Z 0 ]. −1 2. [a]. or. [b] = [ S ][ a ]. (23). where 13.

(31) [ Re Z o ]. −1 2. ⎡ 1 ⎢ Re Z 01 ⎢ ⎢ ⎢ 0 =⎢ ⎢ # ⎢ ⎢ ⎢ 0 ⎢⎣. 0. ". 1 Re Z 02. ". # ". 0. ⎤ ⎥ ⎥ ⎥ 0 ⎥ ⎥ ⎥ # ⎥ 1 ⎥ Re Z 0 n ⎥⎥⎦ 0. (24). and. [ S ] = [ Re Z 0 ]. 12. ⎡⎣ S I ⎤⎦ [ Re Z 0 ]. −1 2. (25). The matrix [ S ] thus obtained is called the normalized scattering matrix, and its elements are called normalized scattering parameters, or simply scattering parameters. These are the parameters that are usually meant when reference is made to scattering parameters. It can be shown that ⎡⎣ S I ⎤⎦ = [ Z 0 ] ⎡⎣ S V ⎤⎦ ⎡⎣ Z 0* ⎤⎦ −1. (26). If the impedance matrix does not exist for a particular n-port network, but the admittance matrix exists, the scattering parameters can be calculated using (19), (25), and (26). If [ Z 0 ] = ⎡⎣ Z 0* ⎤⎦ = [ R0 ] , then. ⎡⎣ S I ⎤⎦ = ([ z ] + [ R0 ]). −1. ([ z ] − [ R ]) 0. (27). and. [ S ] = [ R0 ]. 12. ⎡⎣ S I ⎤⎦ [ R0 ]. −1 2. (28). Expansion (28) shows that. 14.

(32) [ S ] = ⎡⎣ S I ⎤⎦. (29). if the reference resistances at all ports are equal. Using the typical conditions ⎡1⎤ ⎥ = [ R0 ] Y ⎣ 0⎦. [ Z 0 ] = ⎡⎣ Z 0* ⎤⎦ = ⎢. (30). with all resistances equal results in. [ S ] = ⎡⎣ S I ⎤⎦ = ⎡⎣ S V ⎤⎦. (31). Thus (16a) becomes. ([ z ] + [ R0 ]) [ S ] = [ z ] − [ R0 ]. (32). Solve for [ z ] to obtain. [ z ] = [ R0 ] ([ I ] + [ S ]) ([ I ] − [ S ]). −1. (33). where [ I ] is the unit diagonal matrix. Since [ R0 ] has equal value along the diagonal, (33) becomes ⎡ z ⎤ −1 ⎥ = ([ I ] + [ S ]) ([ I ] − [ S ]) ⎣ 0⎦. [ z '] = ⎢ R. (34). where [ z '] represents the normalized parameters obtained by dividing the actual z-parameters by R0. Also, using (30) and (31) yields for (19). ([Y0 ] + [ y ]) [ S ] = − ([ y ] − ⎡⎣Y0* ⎤⎦ ). (35). Solve for [ y ] to obtain. 15.

(33) [ y ] = [Y0 ] ([ I ] − [ S ]) ([ I ] + [ S ]). −1. (36). Since [Y0 ] has equal values along the diagonal, (36) becomes. [ y '] = [ R0 y ] = ([ I ] − [ S ]) ([ I ] + [ S ]). −1. (37). where [ y '] represents the normalized parameters obtained by multiplying the actual yparameters by R0.. 2.3 Four-port measurement system 2.3.1 Four-port measurement system. A vector network analyzer (VNA) is an instrument, which sends stimulus and receives response to characterize a device under test (DUT). A sine wave is transmitted into the DUT while tuned receiver are swept in lockstep, providing both reflection and transmission properties. VNA is known to have the most accurate calibration standard of any test and measurement instrumentation. The raw measurement results of a VNA are calibrated using frequency domain artifacts – each measurement is accurate, repeatable and traceable, and its measurements are often expressed as scattering parameters. The 4-port VNA used for characterizing RF MOSFET’s in this study is the Agilent N1957B Physical Layer Test System and is shown in Fig. 2.4. This system consists of a standard 2-port VNA (Agilent E8364B) capable to perform s-parameter measurements from 10MHz to 50GHz, a test set (Agilent N4421B), and PC-based control software. The test set converts the standard 2-port VNA to a 4-port VNA, thus enabling characterization of a 4-port DUT. In addition to the 4port NWA, an Agilent 4156 used as a 4-channel DC source is incorporated with 4 bias-tees to provide the required DC bias voltage during s-parameter measurement. 2.3.2 Calibration. 16.

(34) Measurement calibration is an accuracy enhancement procedure that effectively removes the measurement errors that cause uncertainty in measuring a DUT. Measurement errors can be classified into three categories: drift errors, random errors, and systematic errors. Drift errors are caused by deviations in performance of the measuring instrument that occur after calibration. Major causes are the thermal expansion of connecting cables and the thermal drift of the frequency converter within the measuring instrument. These errors can be reduced by carrying out frequent calibrations as the ambient temperature changes or by maintaining a stable ambient temperature during the course of a measurement. Random errors occur irregularly along the time axis. Since random errors are unpredictable, they cannot be eliminated in a calibration. The main contributors to random errors are instrument noise such as, source phase noise, sampler noise, and IF noise. The accurate source and phase-locked receiver of the network analyzer greatly minimizes these random errors. Systematic errors are caused by imperfections in the measuring instrument and the test setup (cables, connectors, RF probe, etc.). Assuming these errors are repeatable and their characteristics do not change relative to time, then it is possible to eliminate these errors mathematically at the time of measurement by determine the characteristics of these errors in a calibration. There are six types of systematic errors: directivity and crosstalk related to signal leakage, source and load impedance mismatches related to signals being reflected, and frequency response error caused by reflection and transmission tracking with the test receivers. A VNA has 2 receivers for each test port, the reference receiver and the test receiver (transmission measurement or reflection measurement) and allows one to perform measurements using these receivers at the same time. Figure 2.5 shows the architecture of the test ports of a VNA and systematic errors. For the 4-port VNA, there exist four directivity-error terms (Ed), twelve crosstalk-error terms (Ex), four source-mismatch error terms (Es), twelve load-mismatch error terms (El), four reflection tracking error terms (Er), and twelve transmission tracking error terms (Et). The full 4-port error model and the 48 error terms mentioned above are shown schematically in Fig. 2.6. The most common calibration method used to characterize the systematic errors is Short-. 17.

(35) Open-Load-Through (SOLT) calibration [24]-[25]. In full 4-port calibration, calibration data are measured by connecting an SHORT standard, OPEN standard, an LOAD standard to the 4-test port, and THRU standard between each two ports. According to SOLT method, the 48 error terms for the 4-port NWA can be calculated from the measured calibration data. The calibration data will be stored in the memory of VNA, and the measured RAW data will be processed automatically during the measuring procedure is going. The imperfection effect of the VNA and the parasitics of the cables, connectors, and probes can all be eliminated and results in a measurement data as close to the intrinsic data of the DUT as possible.. 2.4 Summary In this chapter, the fundamental one-port scattering parameter is brief introduced. Then, deduce of multi-port scattering parameters according to the one-port concept is demonstrated. The conversion of multi-port scattering parameters to Z- and Y- parameters, which are important in the following studies of RF MOSFET modeling are also addressed. Finally, the 4-port vector network analyzer used in this study is introduced; the calibration of this 4-port VNA is also described conceptually.. 18.

(36) I Z0. + V. + E -. -. Fig.2.1 One port network.. 19. ZL.

(37) Ii Z0 + Vi + E -. ZL *. -. Fig.2.2Generator with conjugate matched load used to define “incident” components Ii and Vi.. 20.

(38) I1 E1. +. Z01. +. V1. V9. -. -. n-port network. I4 E4 -. Z04. Vn. -. -. + V8 -. Z05. Z08. + E5 -. + E8 -. Fig.2.3 An n-port network with generators.. 21. E9 -. +. V4 + V5 -. +. In. +. I5. +. Z09. -. I8. +. I9. Z0n. +. En -.

(39) PORT1. PORT3. Agilent E8364B PORT3. Agilent N4421B. PORT4. Fig.2.4 Agilent N1957B Physical Layer Test System.. 22.

(40) Fig.2.5 Architecture of VNA test ports and the systematic errors.. 23.

(41) Fig.2.6 The full 4-port error model and the 48 error terms.. 24.

(42) Chapter 3 Characterizing RF MOSFET’s by Four-Port Measurement. 3.1 Motivation The high Ft and high-level integration ability of modern CMOS technology make that GHz range applications of RF MOSFET more popular today. In most cases, MOSFET’s are designed as common source amplifiers in analog and RF circuits. Therefore, the characterization method of a MOSFET is usually arranging the device as a 2-port amplifier in common source configuration, and perform on-wafer S-parameter measurement by conventional 2-port network analyzer. In addition to common source configuration, common gate and common drain condition also appears in RF analog circuits as mentioned in chapter one. To characterize a MOSFET in common gate (CG) or common drain (CD) configuration by using the traditional 2-port test structure will encounter problems. While fitting a RF MOSFET in a 2-port test structure, two of the four terminals of the MOSFET must be connected together. On the other word, the body must be connected to the other terminal witch is intended to be “commoned”. In the case of common source, since the source and body are tied together and connected to ground, the DC bias can be easily applied for the device to operate in saturation mode. In the case of common gate configuration, however, the common terminal gate cannot be tied with body. The DC bias voltage applied on gate terminal has to be larger than that applied on the source in order to operate the device in saturation region. If the body was tied with gate, it will cause the substrate-source junction to be forward biased, which violates the principle of operating a MOSFET. There exists similar situation in the case of common drain configuration. The substrate-source junction will be forward biased if the body was tied with the drain. Besides the bias problem of common gate and common drain cases, in real CMOS IC’s, the body terminals are not always connected to. 25.

(43) source terminals of every single device. In fact, they are connected to the ground or the most negative potential in the circuits while source terminals maybe not. The source and substrate terminals may have voltage drops between them. The traditional 2-port GSG test structure is unable to adapt this bias condition. An efficient way to overcome theses problems is to fit the four-terminal RF MOSFET to a multi-port test structure that has at least three ports. In this chapter, a four-port test structure for s-parameter measurement of RF MOSFET’s is proposed. The DC bias voltage on each terminal will be applied independently. The data of RF MOSFET in CS, CG, and CD configurations can all be characterized by a single proposed four-port test structure. Besides, the s-parameters of RF MOSFET’s in common source configuration under different substrate biases are also observed.. 3.2 Four-Port RF MOSFET’s The devices used in this study are RF MOSFET’s fabricated with 0.13µm CMOS process of UMC. General multi-finger gate structure is adopted for the devices, and the finger number is four for all devices but with different finger length. Four gate fingers means the devices are unsymmetrical, since there will be two source and three drain junctions or two drain and three source junctions depend on the connection and applied voltage of source/drain terminals. The layout of the RF MOSFET is designed as the gate, drain, source and body terminals were connected individually to four signal pads of a four-port test structure. Figure 3.1a shows the test structure and the RF MOSFET schematically. Figure 3.1b is the top view photograph of the DUT. These four signal pads incorporated with a reference ground form a 4-port GroundSignal Ground (GSG) test structure and the RF MOSFET can be treated as a 4-port device and characterized by 4-port measurement.. 26.

(44) The on-wafer four-port measurement of this test structure was accomplished by the Agilent PLTS 50GHz 4-port system incorporated with a Cascade Microtech probe station and four RF probes. Since the port positions in this test structure are orthogonal, the generally used SOLT (short, open, load, thru) calibration procedure is not usable in this condition [10,11]. In SOLT calibration procedure, the RF properties of the four standard (SHORT, OPEN, LOAD, THRU) must be define clearly. In conventional two-port SOLT calibration, the THRU standards are always fabricated short and strait and has characteristic impedance of 50Ω. This kind of well behavior THRU line can be simply specified by a delay time and character impedance. However, specifying an orthogonal THRU standard just by delay time and characteristic impedance is inefficient since the behavior of orthogonal THRU is much more complex. One solution for this kind of orthogonal or other undefined THRUs is conducting a SOLR calibration procedure. By SOLR calibration method, the definite THRU specification is not necessary. The only thing it needs about the THRU standard is the approximate delay time. According to the SOLR and the approximate delay time, a set of two-port scattering parameters represent the orthogonal THRU can be obtained. And the error terms can still be calculated out. However, the PLTS system used to conduct the four-port measurement doesn’t equip with SOLT calibration procedure in its control software. The calibration method used this study is still the SOLT method, but with the specification of orthogonal THRU obtained by a two-port measurement in which the two-port were posited in right angle and calibrated by SOLR method.. 3.3 Dummy Structures and De-Embedding Procedure The proposed four-port test structure is shown in Fig.3.2 three-dimensionally. The signal metal connections are mainly routed by top metal layer and are shielded by the bottom metal layer connected to ground. The test structure with the body signal pad connected to substrate. 27.

(45) is shown in Fig.3.3. This test structure exhibits several parasics and the equivalent circuit of the test structure is shown in Fig. 3.4. In this circuit, the four Ypad components represent the shunt admittances across the individual signal pad and the surrounding ground metal. In this 4-port test structure, the signal pad of port2 corresponding to the body terminal is connected to the silicon substrate through substrate contacts. The substrate contacts is arranged in ringtype and surrounding the active area of the NMOSFET. This, however, will cause a kind of unique parasitic in the area outside the active region. The substrate area outside the contact ring will exhibit as extrinsic shunt parasitics between substrate and the ground metal which shields the substrate loss form coupling to the signal metal connections of the other three terminals. The components Ysub are corresponding to this parasitic. The substrate area outside the contact ring but isn’t shielded by the bottom metal layer (M1) will form another shunt parasitic components between substrate and each signal metal traces of other three terminals. In other words, the substrate loss will be coupled to the signal metal traces of the other three terminals via these shunt parasitics and they are corresponding to the three Yps components in Fig.3.4. The four Zs components in Fig.3.4 represent the series impedances of signal metal trace. To obtain the intrinsic RF characteristic of the DUT, these parasitics must be removed firstly. The Ypad, Ysub, Yps, and the shunt admittance components exist between each 2 signal pads that aren’t shown in Fig.3.4 can be de-embedded from the raw measurement data of 4-port NMOSFET by performing open de-embedding procedure according to the same structure shown in Fig.3.3. This is the same test structure with the proposed 4-port NMOSFET except that the NMOSFET is taken out. It can be treated as a special open dummy for the four-port test structure. The Zs components can be de-embedded out by performing short de-embedding procedure, and the short dummy structure shown in Fig.3.5. In this short dummy structure, all signal connections including the vias between metal layers are shorten by the bottom metal layer.. 28.

(46) During the de-embedding process, the raw 4-port S-parameters matrix SRAW of the 4port nMOSFET is firstly transferred to Y-parameters YRAW according to Eq. 1 [12].. [Y ] = [I − S ]• [I + S ]−1. (3-1). The I in Eq.3-1 represents a 4x4 identity matrix. According to Eq.3-1, the measured four-port S-parameters of the special open dummy shown in Fig.3.3 can also obtained as Yopen. According to Eq.3-2, the 4-port Z-parameters of the short dummy structure can be obtained as Zshort.. [Z ] = [I + S ]• [I − S ]−1. (3-2). The intrinsic Y-parameters of the 4-port NMOSFET Yd can be derived from Eq.3-3.. [Yd ] = [[YRAW − Yopen ]−1 − Z short ]. −1. (3-3). Figure 3.6 compares the difference of input admittance at port2 (body signal pad) between the special open dummy and an ordinary open dummy without substrate contact ring. The proposed open dummy exhibits the parasitic Ysub shown in Fig.3.4, which need to be deembedded from the raw measurement data of the DUT while the ordinary open dummy exhibits merely the Ypad parasitic component.. 3.4 Four-Port Y-parameters and Port Reduction According the definition, the Y-parameters of the proposed NMOSFET can be expressed as: ⎡iG ⎤ ⎡ yGG ⎢i ⎥ ⎢ y ⎢ D ⎥ = ⎢ DG ⎢ iS ⎥ ⎢ y SG ⎢ ⎥ ⎢ ⎣iB ⎦ ⎣ y BG. yGD. yGS. y DD. y DS. y SD y BD. y SS y BS. yGB ⎤ ⎡ vG ⎤ y DB ⎥ ⎢v D ⎥ ⎥⎢ ⎥ y SB ⎥ ⎢ v S ⎥ ⎥⎢ ⎥ y BB ⎦ ⎣ v B ⎦. (3-4). In the proposed NMOSFET test structure, the NMOSFET has its four terminals connecting to four signal pads, therefore, the Y-matrix of this device represent a NMOSFET without any common terminal. According to Eq. 3-4, grounding a terminal is simply giving the. 29.

(47) corresponding voltage source a zero value, and the remained sub-matrix will be the Y-matrix represents the resulting configuration of the NMOSFET. Therefore, the 4x4 matrix of fourport Y-parameters will be easily reduced to three-port or two-port Y-matrix depending on the requirement. The grounded terminals of CS configuration is source and body terminals, therefore, the CS two-port Y-matrix can be obtained by setting vS = 0 and vB = 0 in Eq.3-4. And the two-port CS Y-matrix is just the sub-matrix corresponding to [iG, iD] and [vG,vD], it can be expressed as Eq. 3-5. ⎡iG ⎤ ⎡ yGG ⎢i ⎥ = ⎢ y ⎣ D ⎦ ⎣ DG. yGD ⎤ ⎡ vG ⎤ y DD ⎥⎦ ⎢⎣v D ⎥⎦. (3-5). Similarly, the CG and CD Y-matrix can be also obtained in the same manner and can be expressed as Eq.3-6 and Eq.3-7, respectively. ⎡ iS ⎤ ⎡ y SS ⎢i ⎥ = ⎢ y ⎣ D ⎦ ⎣ DS. y SD ⎤ ⎡ v S ⎤ y DD ⎥⎦ ⎢⎣v D ⎥⎦. (3-6). ⎡iG ⎤ ⎡ yGG ⎢i ⎥ = ⎢ y ⎣ S ⎦ ⎣ SG. yGS ⎤ ⎡vG ⎤ y SS ⎥⎦ ⎢⎣ v S ⎥⎦. (3-7). 3.5 Measurement Results and Discussions 3.5.1 Measurement Results of Devices with Different Dimensions Three 0.13 µm multi-finger NMOSFET’s with different gate widths were characterized from 100MHz to 20GHz. The gate finger lengths are 3.6 (M1), 7.2 (M2) and 12 µm (M3), and with the same finger number four. And the total gate width of each device is 14.4, 28.8 and 48. µm for M1, M2, and M3, respectively. The devices are biased at VG=1V, VD=1V,VS=0V, and VB=0V. The drain currents are 6, 11, 20 mA corresponding to M1, M2, and M3.. 30.

(48) Figure 3.7 shows the reflection four-port scattering parameters SGG, SDD, SSS, and SBB on each terminal of M1, M2, and M3 in a smith chart. The three SGG curves almost extend along the same R circle but with different length as frequency increases. The wider the gate width of the device is, the longer the SGG curve goes. It represents the input capacitance at gate scales with total gate width of each device. The SDD curves show the finite output resistance of the devices. The wider the device gate width is, the smaller the output resistance presents at drain. They also reveal that the output capacitance of each device also scale with the device dimension. The SSS curves of the three devices are also shown. It shows there exists inductive input impedance at source terminal and is also scaled with the device dimension. The input inductance appears at source is mainly caused by two factors. The first one is the resistance appears at gate terminal, which will produce an input inductance component at source. The second one is the imaginary part of the current source (-ωCm), witch will also produce an input inductance at source terminal. This inductance component can be deduced from the small-signal equivalent circuit of an RF NMOSFET, but was observed from directly measured data for the first time since it cannot be observed from two-port measurement data. Figure 3.8 shows the measured SGB of the three devices, the test signal transmitted from body to gate via substrate resistances and small capacitance that exists between substrate and gate. The measured SGD, SGS, SBG, SBD, and SBS are shown in Fig. 3.9, Fig 3.10, Fig. 3.11, Fig. 3.12, and Fig. 3.13, respectively. They all exhibits test signal transmitted from one port to another via capacitive and resistive components. These components are passive in a RF MOSFET. It can be easily observed that these parameters are also scaled with the device dimension. A particular phenomenon is observed that the SGB and SBG of saturation MOSFET’s are different while they are identical if the devices are not applied bias voltages on each terminal. This is due to that the when signal is sent to body, it will transmit to gate via substrate resistance and parasitic capacitance between this terminal. In the other hand, the signal applied at substrate will influence the carriers in the channel of the device due to body effect. However, if the signal is sent to gate, the carriers in the channel of the NMOSFET will be influenced directly 31.

(49) by the test signal, and the fluctuation of carriers in channel than couple to the substrate. The different mechanism results in different SGB and SBG. Figure 3.14 shows the SDG and SSG of the three devices. SDG represents a measurement of signal transmits form gate to drain resembles to the S21 in the case of the DUT is arranged in two-port common source configuration. SDG is primarily caused by the transconductance of the devices and exhibit 180 degrees phase at low frequency. SSG, which cannot be measured from two-port DUT’s, is the measurement of test signal transmits from gate to source. This transmission is also caused by the transconductance of the DUT, but will be in phase with the signal applied at gate. The SSG is related to the forward transmission of the device configured in two-port common drain mode, or so-called source follower. Figure 3.15 shows the measured SDB and SSB. SDB is caused mainly by back-gate bias effect or so called body effect. According to this effect, the body acts as a second gate of the device and will slightly control the drain current. Therefore, SDB is similar to SDG and has 180 degrees phase at low frequency. The SSB is also induced by body effect. The signal applied on body will result a signal at source with the same phase at low frequency. Figure 3.16 shows the SDS and SSD of the three devices. SDS is a measurement of signal transmits from source to drain, which is related to the device configured in two-port common gate configuration. While a test signal is applied at source, the channel current will be controlled by this signal hence the results an output signals at drain. The test signal will be in phase with the resulted signal at drain at low frequency, therefore, the contour of SDS started from the 0 degree axis of the polar chart. The SSD mainly induced from the finite resistance exists between drain and source, which is resulted from the channel length modulation effect of MOSFET devices. 3.5.2 Two-Port Scattering Parameter of The Common Source, Common Drain, and Common Gate RF MOSFET,s. 32.

(50) The measured four-port scattering parameters were transferred to the two-port scattering parameters of devices in common source, common drain, and common gate configurations according to Eq. 3-1, Eq. 3-4, Eq. 3-5, Eq. 3-6, and Eq 3-7. Figure 3.17 shows two-port common source reflection parameters, SGG and SDD, which are transferred from four-port data. Figure. 3.18 shows the corresponding transmission parameters, SGD and SDG. Since the 50W termination connected between source and ground in the fourport VNA is shorten (short the source and ground) theoretically while converting the four-port scattering parameters to two-port case, it is obviously the two-port parameters are all different with the correspondent parameters in four-port case. The most easily to be observed is the SDG, whose magnitude was enlarged since the 50Ω resistance was removed. The SGG curves in Fig. 3.17 also shows that common source devices have larger input capacitance than the four-port MOSFET’s since more serious Miller effect due the larger gain of common source devices. Comparing the SDD curves in Fig. 3.7 and Fig. 3.18, it’s also observed that the drain output resistances of common source devices are smaller than that of four-port devices since the source terminals of the common source devices are grounded. Figure 3.19 shows the two-port reflection parameters of devices in common drain configuration. A MOSFET in common drain configuration is also called a source follower, which theoretically can produce an output signal almost identical to the input signal but with a smaller output resistance. The contours of reflection parameters at gate (SGG) are similar to the SGG contours of common source configuration shown in Fig. 3.17, but with a shorter length in the smith chart. This means the input capacitance at gate terminal of a MOSFET in common source configuration is much larger than the input capacitance at the same gate terminal of the same device but is configured in common drain configuration. This is due to the well-known Miller effect, the input capacitance of the common source MOSFET will be amplified approximately by the magnitude of the voltage gain (1-AV) of the device. The SSS curves in Fig. 3.19 show the output impedance is also inductive. As have mentioned. 33.

(51) previously, the inductive impedance at source is caused by the resistance appears at gate and the transcapacitance Cm. Figure 3.20 shows the two-port transmission scattering parameters of devices in common drain configuration. The two-port reflection scattering parameters of the devices in common gate configuration, SSS and SGG, are shown in Fig. 3.21. Devices operated in this configuration are mainly used as a current buffer. SSS curves show that the input impedances are inductive, resistive or capacitive depends on the device dimension. This is due to the gate terminals are grounded, which in terms reduces the resistance appears at gate terminal (without 50Ω termination). Therefore the inductive components at source terminals are reduced. In addition to the inductive component induced from the gate resistance and transconductance Cm, the input impedance at source terminal is also affected by the source/substrate junction capacitance. In lager device M3, the inductive component induced from larger gate resistance and Cm will larger enough to maintain the inductive input impedance at source. However, as the device dimension decreases, the input impedance caused by inductive component due to smaller gate resistance and Cm combined with the capacitive source/substrate junction will become resistive or capacitive. Figure 3.22 shows the two-port SDS and SSD parameters of the devices in common gate mode. A conventional two-port test structure with a NMOSFET configured in common source mode was measured with two-port VNA. The dimension of this two-port NMOSFET is the same with the M2 ( 7.2µ m × 4 ) four-port counterpart. The measured two-port scattering parameters. are compared to the two-port common source data conversed from the four-port scattering parameters of M2 device. The results are shown in Fig.3.23 and they rather agree with each other. However, devices in common gate and common drain configuration cannot be implemented by conventional two-port test structure as described in previous section, the comparisons similar to the common source case are absence.. 34.

(52) 3.6 Summary Four-port test structure for characterizing MOSFET’s is presented in this chapter. The dummy structures including a special open dummy are also shown. The parasitic components of the proposed test structure and de-embedding procedures are clearly explained. Than the measured sixteen four-port scattering parameters are all illustrated by figures and explained in detail. The theory and method of reducing four-port Y-parameters to two-port Y-parameters of MOSFET’s in common source, common gate and common drain configurations is also demonstrated. The common source, common gate, and common drain data can be directly conversed from the measured four-port scattering parameter of the proposed test structure. Only one single DUT and one measurement procedure are needed to obtain these data. Three MOSFET’s in different dimensions are characterized by 4-port measurement, and all the obtained parameters are scaled with the device dimensions. In contrast with the limitation of a conventional 2-port test structure, the 4-port test structure will more powerful for fully characterizing MOSFET devices.. 35.

(53) G. G. drain. G S. S. G body. gate. S source. G G. S. G G. (a). Drain. Gate. Body. Source. (b) Fig.3.1 (a) Schematics of test structure and the RF MOSFET. (b) The top view photograph of the test structure and the RF MOSFET.. 36.

(54) u Gro To. e pm. nd. tal. nal Sig dy) (Bo. nal Sig in) a (Dr. d un o r G. d un Gro l na Sig ate) (G. Me. tal. l ay er s. tr bs Su. ate. u Gro an d. nal Sig rce) u (So nd. un Gro. g ldin h ie s d. b Su via. s Ox. Fig.3.2. ate str. ide. Test structure for the four-port measurement.. 37.

(55) d un Gro nal Sig dy) (Bo. nal Sig in) a (Dr d un Gro. te stra Sub tacts Con. d un Gro. l na Sig ate) (G Me tal. lay. d un Gro ers. an d. nal Sig rce) u (So 1 g) tal eldin e M shi nd u o e ( Gr rat bst u S. v ia s id Ox. Fig.3.3. e. OPEN dummy structure for the four-port measurement.. 38.

(56) port3. Yps. Ypad Zs D port1 Zs. G. B. DUT. port2 Zs Ypad. Ypad. S Yps Zs Yps. Ysub. Ypad. port4. Fig.3.4. The equivalent circuit of the test structure.. 39.

數據

Updating...

參考文獻

Updating...