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Chapter 5 Verification of Small-Signal Equivalent Circuit Model

5.2 Simulation of the Equivalent Circuits

To obtain the output characteristics of a circuit, one needs a simulator, which can input the circuit in text or graphic form includes the information such as nodes, resistors, inductors, capacitors, and dependent or independent current/voltage sources. The simulator will compute the electrical behavior of the circuit according to basic electrical laws. The most well-known circuit simulator is the SPICE program developed by university of California, Berkeley. In this study, commercial software named Advanced Design System (ADS) presented by Agilent Technologies is used for the simulation of the equivalent circuit. The equivalent circuit can be input to the simulator in the form of electrical circuit diagram by a graphical input interface, than the simulator can output the simulated results in form of network parameters such as Y-,

Z-, or S-parameters. The y-parameters were chosen for the output form since the components in the equivalent circuits are all extracted from the y-parameters of the devices.

Three set of the components for the equivalent circuits extracted from three devices with different dimensions are used. The bias condition is set at VG=VD=1.0V. The values of the components are shown in table 5.1a, 5.1b, and 5.1c. In these tables, the value of each component was selected approximately from the figures shown in previous chapter. Some extracted values have large deviation in figure, however, its found that these values are not sensitive to the simulation results. That is also the reason why their extracted values have certain deviation. Choosing an approximate value usually gives fair well simulation results.

Some values were fine tuned in the range during the deviation of the extracted values to obtain better results. The simulation frequency range is from 100MHz to 20GHz.

5.3 Results and Discussions

The simulated and measured four-port y-parameters of each device are shown in real parts and imaginary parts individually from 100MHz to 20GHz. Figure 5.1a and 5.1b show the simulated and measured results of YGG. It can be observed the simulated imaginary parts of YGG agreed with the measured counterparts very well during the entire frequency range. The imaginary part of YGG is mainly determined by CGS, CGD and CGBE. The results of real parts show slight difference between simulated and measured data in Fig. 5.1b. Since the amplitude of Re[YGG] are rather small, this deviations are still acceptable. The real part of YGG is a complex result determined by RG, RS, RD, CGS, CGD, and CGBE.

Figure 5.2a and 5.2b show the modeling results for YDD of the three devices. YDD is an important output admittance for a RF MOSFET, since MOSFET’s are usually arranged in

RS, and RD. As frequencies increases, the amplitude of YDD will rise due to the output signal at drain terminal couples to the substrate via the reverse-biased drain/bulk junction. Therefore, at higher frequencies, the CDB, CGS, RD, RCH, RS, RDB, RSB, and RDSB all have contribution to YDD.

The measured and simulated input admittances of the source terminals of the three devices are shown in Fig.5.3a and 5.3b. The imaginary part of YSS will be influenced by RG, CGS, CSB, gm, gmb and transcapcitance Cm, Cmb, Cmx. However, the Cmx has not been extracted from the measurement data, since the difference between CGB and CBG are very small and irregular. It’s hardly to tell the Cmx from the measurement error. It’s also found that the input admittance at source become more inductive as the device dimension increases, which is believed due to the larger RG, Cm, and Cmb of the larger device. The real part of the YSS is dominated by gm and gmb of the device.

Figure 5.4a shows distinguish difference between the simulated and measured Im[YBB], this probably caused by the over de-embedding of the parasitics of the substrate pad. The shunt capacitance between substrate pad and ground is over de-embedded. However, the input admittance at the body terminal is the last thing one would care, since the body terminal of a MOSFET is always ac grounded.

Figure 5.5a shows the measured and simulated Im[YGD]’s, which are mainly caused by the CGDO of these devices. The Im[YGD] is primarily determined by CGDO. Figure 5.5b shows the modeling results of Re[YGD], which are mainly determined by CGDO, RG, and RD.

The YGS of the three devices, which mainly caused by CGS and series RG, RS are shown in Fig.5.6a and 5.6b. They are obviously modeled well.

Figure 5.7a and 5.7b show the YGB of the three devices. The amplitudes of YGB including imaginary and real part are very close to the YBG‘s show in Fig. 5.8a and 5.8b, except for the case of M3. The YBG of M3 under VG=VD=1V bias condition exhibit irregular behavior, however, its amplitude is very small and has no effect on the entire device behavior.

Figure 5.9a and 5.9b show the measured and simulated YBD’s of the devices. The modeling results are also fair well. YBD is mainly caused by CDB and RDB. It is also the main contributor to the output admittance of drain terminal at high frequency range.

Figure 5.10a and 5.10b demonstrate the simulation results of the YBS’s, which are mainly caused by CSB and RSB. YBS can be used as an evaluation for the accuracy of extracted CSB

and RSB. Poor extracted values of CSB and RSB will worse the modeling of entire substrate network, since the intrinsic body terminal is located between the CSB and RSB.

The simulated and measured YDG’s are shown in Fig. 5.11a and 5.11b. The imaginary part of YDG is caused by RG, CGS, CGD, gm, and Cm, and represents the signal delay from gate to drain terminal. The real part of YDG is very close to, however, slight smaller than the transconductance, gm.

Figure 5.12a and 5.12b illustrate the modeling results of YDB’s, which are the main parameter to evaluate the substrate transconductance gmb. The imaginary part of YDB is similar the imaginary part of YDG that it also influence by transcapacitance. During the simulation process, it is found that the Im[YDG] will be influenced by CSB, RSB, gm, gmb and Cmb, the simulation results will be exact only if these components are extracted correctly. The Re[YDB] is close related to gmb. In fact, the Re[YDB] at very low frequency range is equal to gmb, since at lower frequency, vBS will approach to vBsi. As frequency increases, the vBSi will decrease due to the decreasing of the impedance of CSB. Therefore the Re[YDB] decreases as frequency increases. Similarly, the Re[YDB] will be modeled well only if the values of gmb, CSB, and RSB are extracted exactly.

Figure 5.13a and 5.13b show the modeling results of YDS’s. YDS corresponds to the trans-admittance of a two-port common gate device. It is observed that the Im[YDS] shows inductive property, as had mentioned, it is contributed by the transcapacitance Cm and Cmb. The Re[YDS] is dominated by gm and gmb.

in spite of CGS exists between gate and source. This inductive component is induced by RG, CGS, and gm, it is also a contributor to the inductive input impedance at source terminal. The Re[YSG] is also dominated by gm of the device and approximately equals to the amplitude of Re[YDG].

Figure 5.15a shows the imaginary part of YSB, in which a “bending” is observed. Similar with the effect of RG, CGS, gm act on YSG, the RSB, CSB, gmb make YSB “inductive”. However, the value of gmb is much smaller than gm, and the vBSi decreases as frequency decreases. The

“inductive” components produced by gmb will decrease to a level, which will less than the original capacitance value of CSB. Therefore, the YSB “bends” beneath the x-axis.

Figure 5.16a and 5.16b show the measured and simulated YSD’s of the devices. The YSD is another contributor to the output admittance at drain, which is mainly cause by the channel resistance 1/gDS.

5.4 Summary

The simulated y-parameters of the equivalent circuit for saturation devices are demonstrated and compared with the measurement data of the devices. Most of the measured and simulated y-parameters are agreed with each other. Phenomena arisen from each component in the equivalent circuit of an active RF MOSFET are observed and analyzed. The RF small-signal behaviors of the four-terminal RF MOSFET are modeled pretty well.

M1: VG=1V, VD=1V

gm(mS) Cm(fF) gmb(mS) Cmb(fF) gds(S) RS(Ω) RD(Ω) RG(Ω) CGS(fF) 11.8 4.4 1.33 2 1/840 6.9 6.9 35 13.5 CGD(fF) CSB(fF) CSBE(fF) RSB(Ω) CDB(fF) CDBE(fF) RDB(Ω) CGBE(fF) RDSB(Ω)

5.8 7.2 3 1500 3.5 1.5 3000 0.6 1300 (a)

M2: VG=1V, VD=1V

gm(mS) Cm(fF) gmb(mS) Cmb(fF) gds(S) RS(Ω) RD(Ω) RG(Ω) CGS(fF) 23.3 14 2.64 4 1/423 3.6 3.6 23 25.6 CGD(fF) CSB(fF) CSBE(fF) RSB(Ω) CDB(fF) CDBE(fF) RDB(Ω) CGBE(fF) RDSB(Ω)

10.2 14.5 4.5 800 7.2 2 1500 0.9 700 (b)

M3: VG=1V, VD=1V

gm(mS) Cm(fF) gmb(mS) Cmb(fF) gds(S) RS(Ω) RD(Ω) RG(Ω) CGS(fF) 38.3 27 4.15 5 1/242 2.5 2.5 40 42.5 CGD(fF) CSB(fF) CSBE(fF) RSB(Ω) CDB(fF) CDBE(fF) RDB(Ω) CGBE(fF) RDSB(Ω)

16 30 6 400 13 2.5 800 1 400 (c)

Table 5.1 (a) The extracted values of the components for the small-signal equivalent circuit model of M1 devices (3.6µm× ). 4

(b) The extracted values of the components for the small-signal equivalent circuit model of M2 devices ( 7.2µm× ). 4

(c) The extracted values of the components for the small-signal equivalent circuit model of M3 devices (12µm× ). 4

0 5 10 15 20 FREQUENCY (GHz)

0 0.002 0.004 0.006 0.008

Im[YGG] (S)

Measured Im[YGG] of M1, M2, and M3 Simulated Im[YGG] of M1 Simulated Im[YGG] of M2 Simulated Im[YGG] of M3

(a)

0 5 10 15 20

FREQUENCY (GHz) 0

0.0005 0.001 0.0015 0.002 0.0025

Re[YGG] (S)

Measured ReYGG] of M1, M2, and M3 Simulated Re[YGG] of M1

Simulated Re[YGG] of M2 Simulated Re[YGG] of M3

(b)

Fig.5.1 (a) Measured and simulated Im[YGG] of M1, M2, and M3 biased VG=VD=1V.

(b) Measured and simulated Re[YGG] of M1, M2, and M3 biased VG=VD=1V.

0 5 10 15 20 FREQUENCY (GHz)

0 0.002 0.004 0.006 0.008

Im[YDD] (S)

Measured Im[YDD] of M1, M2, and M3 Simulated Im[YDD] of M1

Simulated Im[YDD] of M2 Simulated Im[YDD] of M3

(a)

0 5 10 15 20

FREQUENCY (GHz) 0

0.002 0.004 0.006 0.008

Re[YDD] (S)

Measured Re[YDD] of M1, M2, and M3 Simulated Re[YDD] of M1

Simulated Re[YDD] of M2 Simulated Re[YDD] of M3

(b)

Fig.5.2 (a) Measured and simulated Im[YDD] of M1, M2, and M3 biased VG=VD=1V.

0 5 10 15 20 FREQUENCY (GHz)

-0.006 -0.004 -0.002 0 0.002

Im[YSS] (S)

Simulated Im[YSS] of M1 Simulated Im[YSS] of M2 Simulated Im[YSS] of M3

Measured Im[YSS] of M1, M2, and M3

(a)

0 5 10 15 20

FREQUENCY (GHz) 0

0.02 0.04 0.06 0.08

Re[YSS] (S)

Simulated Re[YSS] of M1 Simulated Re[YSS] of M2 Simulated Re[YSS] of M3

Measured Re[YSS] of M1, M2, M3

(b)

Fig.5.3 (a) Measured and simulated Im[YSS] of M1, M2, and M3 biased VG=VD=1V.

(b) Measured and simulated Re[YSS] of M1, M2, and M3 biased VG=VD=1V.

0 5 10 15 20 FREQUENCY (GHz)

0 0.001 0.002 0.003 0.004

Im[YBB] (S)

Simulated Im[YBB] of M1 Simulated Im[YBB] of M2 Simulated Im[YBB] of M3

Measured Im[YBB] of M1, M2, and M3

(a)

0 5 10 15 20

FREQUENCY (GHz) 0

0.0005 0.001 0.0015 0.002 0.0025

Re[YBB] (S)

Simulated Re[YBB] of M1 Simulated Re[YBB] of M2 Simulated Re[YBB] of M3

Measured Re[YBB] of M1, M2, and M3

(b)

Fig.5.4 (a) Measured and simulated Im[YBB] of M1, M2, and M3 biased VG=VD=1V.

0 5 10 15 20 FREQUENCY (GHz)

-0.002 -0.0015 -0.001 -0.0005 0

Im[YGD] (S)

Simulated Im[YGD] of M1 Simulated Im[YGD] of M2 Simulated Im[YGD] of M3

Measured Im[YGD] of M1, M2, and M3

(a)

0 5 10 15 20

FREQUENCY (GHz) -0.0006

-0.0005 -0.0004 -0.0003 -0.0002 -0.0001 0

Re[YGD] (S)

Simulated Re[YGD] of M1 Simulated Re[YGD] of M2 Simulated Re[YGD] of M3

Measured Re[YGD] of M1, M2, and M3

(b)

Fig.5.5 (a) Measured and simulated Im[YGD] of M1, M2, and M3 biased VG=VD=1V.

(b) Measured and simulated Re [YGD] of M1, M2, and M3 biased VG=VD=1V.

0 5 10 15 20 FREQUENCY (GHz)

-0.006 -0.005 -0.004 -0.003 -0.002 -0.001 0

Im[YGS] (S)

Simulated Im[YGS] of M1 Simulated Im[YGS] of M2 Simulated Im[YGS] of M3

Measured Im[YGS] of M1, M2, and M3

(a)

0 5 10 15 20

FREQUENCY (GHz) -0.002

-0.0015 -0.001 -0.0005 0

Re[YGS] (S)

Simulated Re[YGS] of M1 Simulated Re[YGS] of M2 Simulated Re[YGS] of M3

Measured Re[YGS] of M1, M2, and M3

(b)

Fig.5.6 (a) Measured and simulated Im[YGS] of M1, M2, and M3 biased VG=VD=1V.

0 5 10 15 20 FREQUENCY (GHz)

-0.00025 -0.0002 -0.00015 -0.0001 -5e-05 0

Im[YGB] (S)

Simulated Im[YGB] of M1 Simulated Im[YGB] of M2 Simulated Im[YGB] of M3

Measured Im[YGB] of M1, M2, and M3

(a)

0 5 10 15 20

FREQUENCY (GHz) -0.00015

-0.0001 -5e-05 0

Re[YGB]

Simulated Re[YGB] of M1 Simulated Re[YGB] of M2 Simulated Re[YGB] of M3

Measured Re[YGB] of M1, M2, and M3

(b)

Fig.5.7 (a) Measured and simulated Im[YGB] of M1, M2, and M3 biased VG=VD=1V.

(b) Measured and simulated Re [YGB] of M1, M2, and M3 biased VG=VD=1V.

0 5 10 15 20

Simulated Im[YBG] of M1 Simulated Im[YBG] of M2 Simulated Im[YBG] of M3

Measured Im[YBG] of M1, M2, and M3

Simulated Re[YBG] of M1 Simulated Re[YBG] of M2 Simulated Re[YBG] of M3

Measured Re[YBG] of M1, M2, and M3

M3

M2

(b)

Fig.5.8 (a) Measured and simulated Im[YBG] of M1, M2, and M3 biased VG=VD=1V.

0 5 10 15 20 FREQUENCY (GHz)

-0.0008 -0.0006 -0.0004 -0.0002 0

Im[YBD] (S)

Simulated Im[YBD] of M1 Simulated Im[YBD] of M2 Simulated Im[YBD] of M3

Measured Im[YBD] of M1, M2, and M3

(a)

0 5 10 15 20

FREQUENCY (GHz) -0.0008

-0.0006 -0.0004 -0.0002 0

Re[YBD] (S)

Simulated Re[YBD] of M1 Simulated Re[YBD] of M2 Simulated Re[YBD] of M3

Measured Re[YBD] of M1, M2, and M3

(b)

Fig.5.9 (a) Measured and simulated Im[YBD] of M1, M2, and M3 biased VG=VD=1V.

(b) Measured and simulated Re [YBD] of M1, M2, and M3 biased VG=VD=1V.

0 5 10 15 20 FREQUENCY (GHz)

-0.0025 -0.002 -0.0015 -0.001 -0.0005 0

Im[YBS] (S)

Simulated Im[YBS] of M1 Simulated Im[YBS] of M2 Simulated Im[YBS] of M3

Measured Im[YBS] of M1, M2, and M3

(a)

0 5 10 15 20

FREQUENCY (GHz) -0.002

-0.0015 -0.001 -0.0005 0

Re[YBS] (S)

Simulated Re[YBS] of M1 Simulated Re[YBS] of M2 Simulated Re[YBS] of M3

Measured Re[YBS] of M1, M2, and M3

(b)

Fig.5.10 (a) Measured and simulated Im[YBS] of M1, M2, and M3 biased VG=VD=1V.

0 5 10 15 20 FREQUENCY (GHz)

-0.02 -0.015 -0.01 -0.005 0

Im[YDG] (S)

Simulated Im[YDG] of M1 Simulated Im[YDG] of M2 Simulated Im[YDG] of M3

Measured Im[YDG] of M1, M2, and M3

(a)

0 5 10 15 20

FREQUENCY (GHz) 0

0.02 0.04 0.06 0.08

Re[YDG] (S)

Simulated Re[YDG] of M1 Simulated Re[YDG] of M2 Simulated Re[YDG] of M3

Measured Re[YDG] of M1, M2, and M3

(b)

Fig.5.11 (a) Measured and simulated Im[YDG] of M1, M2, and M3 biased VG=VD=1V.

(b) Measured and simulated Re[YDG] of M1, M2, and M3 biased VG=VD=1V.

0 5 10 15 20 FREQUENCY (GHz)

-0.004 -0.003 -0.002 -0.001 0

Im[YDB] (S)

Simulated Im[YDB] of M1 Simulated Im[YDB] of M2 Simulated Im[YDB] of M3

Measured Im[YDB] of M1, M2, and M3

(a)

0 5 10 15 20

FREQUENCY (GHz) 0

0.001 0.002 0.003 0.004 0.005

Re[YDB] (S)

Simulated Re[YDB] of M1 Simulated Re[YDB] of M2 Simulated Re[YDB] of M3

Measured Re[YDB] of M1, M2, and M3

(b)

Fig.5.12 (a) Measured and simulated Im[YDB] of M1, M2, and M3 biased VG=VD=1V.

0 5 10 15 20 FREQUENCY (GHz)

0 0.005 0.01 0.015

Im[YDS] (S)

Simulated Im[YDS] of M1 Simulated Im[YDS] of M2 Simulated Im[YDS] of M3

Measured Im[YDS] of M1, M2, and M3

(a)

0 5 10 15 20

FREQUENCY (GHz) -0.08

-0.06 -0.04 -0.02 0

Re[YDS] (S)

Simulated Re[YDS] of M1 Simulated Re[YDS] of M2 Simulated Re[YDS] of M3

Measured Re[YDS] of M1, M2, and M3

(b)

Fig.5.13 (a) Measured and simulated Im[YDS] of M1, M2, and M3 biased VG=VD=1V.

(b) Measured and simulated Re[YDS] of M1, M2, and M3 biased VG=VD=1V.

0 5 10 15 20 FREQUENCY (GHz)

-0.002 0 0.002 0.004 0.006 0.008

Im[YSG] (S)

Simulated Im[YSG] of M1 Simulated Im[YSG] of M2 Simulated Im[YSG] of M3

Measured Im[YSG] of M1, M2, and M3

(a)

0 5 10 15 20

FREQUENCY (GHz) -0.08

-0.06 -0.04 -0.02 0

Re[YSG] (S)

Simulated Re[YSG] of M1 Simulated Re[YSG] of M2 Simulated Re[YSG] of M3

Measured Re[YSG] of M1, M2, and M3

(b)

Fig.5.14 (a) Measured and simulated Im[YSG] of M1, M2, and M3 biased VG=VD=1V.

0 5 10 15 20 FREQUENCY (GHz)

-0.0002 0 0.0002 0.0004 0.0006 0.0008 0.001

Im[YSB] (S)

Simulated Im[YSB] of M1 Simulated Im[YSB] of M2 Simulated Im[YSB] of M3

Measured Im[YSB] of M1, M2, and M3

(a)

0 5 10 15 20

FREQUENCY (GHz) -0.008

-0.006 -0.004 -0.002 0

Re[YSB] (S)

Simulated Re[Y

SB] of M1 Simulated Re[YSB] of M2 Simulated Re[YSB] of M3

Measured Re[YSB] of M1, M2, and M3

(b)

Fig.5.15 (a) Measured and simulated Im[YSB] of M1, M2, and M3 biased VG=VD=1V.

(b) Measured and simulated Re[YSB] of M1, M2, and M3 biased VG=VD=1V.

0 5 10 15 20 FREQUENCY (GHz)

-0.004 -0.003 -0.002 -0.001 0

Im[YSD] (S)

Simulated Im[YSD] of M1 Simulated Im[YSD] of M2 Simulated Im[YSD] of M3

Measured Im[YSD] of M1, M2, and M3

(a)

0 5 10 15 20

FREQUENCY (GHz) -0.008

-0.006 -0.004 -0.002 0

Re[YSD] (S)

Simulated Re[YSD] of M1 Simulated Re[YSD] of M2 Simulated Re[YSD] of M3

Measured Re[YSD] of M1, M2, and M3

(b)

Fig.5.16 (a) Measured and simulated Im[YSD] of M1, M2, and M3 biased VG=VD=1V.

Chapter6

Conclusion and Suggestions for Future Works

6.1 Conclusion of This Study

With amazing advancement of CMOS technologies, RF MOSFET’s have become an important candidate for the rapid growing wireless communication applications.

Communication applications base on COMS technologies are potential to integrate the RF front end, base-band and DSP module together on a single chip, which not only improve the production cost but also the portability of modern communication applications. However, designing RF circuit base on CMOS devices is a challenge since the complex signal coupling inside the device, especially the substrate coupling effect. Therefore, establishing a model accurately predicts the RF behaviors of CMOS devices is an urgent mission. The traditional two-port characterization method is inefficient to investigate the detail RF behavior of a four terminal MOSFET. In this thesis, the four-port S-parameter measurement was proposed and demonstrated for the usage of on-wafer characterization of RF MOSFET’s.

In chapter 2, the basic principles of one-port scattering parameters were reviewed and were extended for multi-port application.

In chapter 3, the four-port system was introduced including the calibration methodology. Moreover, test structures for characterizing RF MOSFET’s including dummy structures were proposed. With the proposed test structures and MOSFET device, the RF characteristics of the MOSFET configured in common source, common gate, and common drain mode can be characterized at one four-port measurement procedure.

In chapter 4, small-signal equivalent circuits with reasonable substrate R-C network for device in different operation mode were proposed and discussed. Extraction methods of the components in these equivalent circuits were deduced in detail. The extractions of the components for devices in different dimensions were also demonstrated, good scalability of the extracted values with the device dimensions was observed.

Finally, the output characteristics of the proposed small-signal equivalent circuits were simulated according to the components extracted from the four-port measurement. The simulated results were compared with the measurement data; good agreement of the Y-parameters from 100MHz to 20GHz was obtained, which suggest the feasibility of applying four-port on-wafer measurement for characterizing RF MOSFET’s.

6.2 Suggestions for Future Works

In this thesis, most studies were focus on characterization, parameter extraction, and modeling of RF MOSFET’s. Some issues such as the behaviors of MOSFET’s suffer from body effect or under different substrate bias could be further investigated.

Moreover, applying the model based on four-port measurement to the circuit design process would be interesting and which can evaluate the accuracy of the model further.

Reference

[1] J. E. Lilienfeld, U.S. Patent 1,745,175, 1930.

[2] W. Shockley and G. L. Pearson, “Modulation of Conductance of Thin Films of Semiconductors by Surface Charges,” Phy. Rev., 74, 232, 1948

[3] D.Kahng and M. M. Atalla, “Silicon-Silicon Dioxide Field Induced Surface Devices,” IRE Solid-State Device Res. Conf., Carnegie Institute of Technology, Pittsburgh, Pa., 1960.

[4] D. Kahng, “A Historical Perspective on the Development of MOS Transistors and Related Devices,” IEEE, Trans., Electron Devices, ED-23, 655, 1976

[5] T. Cho, E. Dukatz, M. Mack, D. MacNally, M. Maringa, S. Mehata, C. Nilson, L, Plouvier, and S. Rabii, “ A Single-Chip CMOS Direct-Conversion Transceiver for 900MHz Spread-Spectrum Digital Cordless Phones,” Int, Solid-State Circuit Conf., 1999, p.228-229

[6] J. Rudell, J. Ou, T. Cho, G. Chien, F. Brianti, J. Weldon, and P. Gray, “ A 1.9 GHz Wide-Band IF Double Conversion CMOS Integrated Receiver For Cordless Telephone Applications,” Int. Solid-State Circuits Conf., 1997, p.304-305.

[7] A. Rofougaran, J. Y-C. Chang, M. Rofougaran, and A. Abidi, “ A 1GHz CMOS RF Front-End IC for a Direct-Conversion Wireless Receiver,” IEEE, J.

Solid-State Circuits, Vol.31, July 1996, p.880-889.

[8] M. B. Das, “High frequency network properties of MOS transistors including the substrate resistivity effects,” IEEE Trans. Electron Devices, Vol. Ed-16, No.12, Dec. 1969, p.1049-1069.

[9] W. Liu, R. Gharpurey, M. C. Chang, U. Erdogan, R. Aggarwal, and J. P. Mattia,

“ RF MOSFET modeling accounting for distributed substrate and channel resistances with emphasis on the BSIM3v3 SPICE model,” Int. Electron Devices

Meeting, 1997, p.309-312.

[10] J.J. Ou, X. Jin, I. Ma, C. Hu, and P.R. Gray, “CMOS RF modeling for GHz communication IC’s” IEDM, 1998, 94-95.

[11] S.F. Tin, A.A. Osman, K. Mayaram, and C. Hu, “ A simple subcircuit extension of the BSIM3V3 model for CMOS RF design,” IEEE, J. Solid-State Circuits, Vol.35, no.4, Apr. 2000, 612-624.

[12] D.R. Pehlke, M. Schroter, A. Burstein, M. Matloubian, and M.F. Chang,

“High-frequency application of MOS compact models and their development for scalable RF model libraries,” Custom Integrated Circuits Conf., 1998, p.219-222.

[13] Y. Ge, and K. Mayaram, “ A Comparative analysis of CMOS Low Noise Amplifiers for RF Applications,” IEEE Proc. ISCAS 98, Vol.4, 1998, pp.

349-352.

[14] X. Li, H.S. Kim, M. Ismail and H. Olsson, ”A Novel Design Approach for GHz CMOS Low Noise Amplifiers,” IEEE RAWCON 99, 1999, pp. 285-288.

[15] F. Bruccoleri, E. A. M. Klumperink, and B. Nauta, “Generating All Two-MOS-Transistor Amplifiers Leads to New Wide-Band LNAs,” IEEE Journal of Solid-State Circuits, Vol. 36, No.7 pp. 1032-1040 July 2001.

[16] J. Martinez-Castillo, A. Diaz-Sanchez and M. Linares-Aranda, “Differential Transimpedance Amplifiers for Communications Systems Based on Common-Gate Topology,” IEEE ISCAS 2002, Vol.2, 2002, pp. 97-100.

[17] G. Gonzalez, “Microwave Transistor Amplifiers Analysis and Design,” 2nd ed., New Jersey: Prentice Hall, 1996, pp. 60-61.

[18] F. Sischka, “IC-CAP Modeling Reference,” Agilent Technologies, 2000, pp.

3_49-3_51.

[19] D.C. Benson, Y. Xuan, J. He, C.M. Lin, C.R. Hodges, and E. A. Logan,

Communication Conf., 1997, 175-180.

[20] D. Lovelace, J. Costa, and N. Camilleri, “Extracting small-signal parameters of silicon MOSFET transistors,” IEEE Trans. Microwave Theory and Techniques Symp., 1994, p.865-868.

[21] C.E. Biber, M.L. Schmatz, T. Morf, U. Lott, and W. Bachtold, “A nonlinear microwave MOSFET model for Spice simulators,” IEEE, Trans. Microwave Theory and Techniques, Vol.46, no.5, May, 1998, p.604-610.

[22] R. Sung, P. Bendix, and M.B. Das, “Extraction of high-frequency equivalent circuit parameters of submicron gate-length MOSFET’s,” IEEE Trans. Electron Devices, vol.45, no.8, Aug. 1998, p.1769-1775.

[23] S.H.M. Jen, C.C. Enz, D.R. Pehlke, M. Schroter, and B.J. Sheu, ”Accurate Modeling and parameter extraction fro MOS transistors valid up to 10 GHz,”

IEEE Tran. Electron Devices, vol.46. No.11, PP.2217-2227, Nov. 1999.

[24] A. Ferrero, U. Pisani, “Two-Port Network Analyzer Calibration Using an Unknown “thru””, IEEE Microwave and Guided Wave Letters, Vol.2, No.12, Dec 1992.

[25] S. Basu, L. Hayden, “An SOLR Calibration for Accurate Measurement of Orthogonal on-wafer DUTs”, pp. 1335-1338, 1997 IEEE MTT-S Digest.

[26] Y. Cheng et al., ”A physical and scalable BSIM3V3 IV model for analog/digital circuit simulation,” IEEE Trans. Electron Devices, Vol.44, p.277-287, Feb, 1997.

[27] Mos9 manual, http://www.semiconductors.philips.com/Philips_Models.

[28] Y. Cheng, M. Schroter, C. Enz, M. Matloubian and D. Pehlke, “RF modeling Issue of deep-submicron MOSFET’s for circuit design,” Proc. of the IEEE Int.

Conf. On Solid-State and Integrated Circuit Technology, p.416-419, Otc. 1998.

[29] C.C. Enz, Y. Cheng, “MOS transistor modeling for RF IC Design,” IEEE Tran.

Solid-State Circuits, vol.35, No.2, Feb. 2000.

[30] C.C. Enz, “An MOS transistor model for RF IC Design Valid in all regions of operation,” IEEE Tran. Microwave Theory and Techniques, vol. 50, No. 1, Jan.

2002.

[31] W. Liu, R. Gharpurey, M.C. Chang, U. Erdogan, R. Aggarwal, and J.P. Mattia,

“RF MOSFET modeling accounting for distributed substrate and channel resistances with emphasis on the BSIM3v3 SPICE model,” Technical Digest of international Electron Device Meeting, p.309-312, Dec, 1997.

[32] Y.P. Tsividis, “Operation and Modeling of the MOS Transistor”, New York:

McGraw-Hill, 1988.

[33] J. Han, M. Je, and H. Shin, “A simple and accurate method for extracting

[33] J. Han, M. Je, and H. Shin, “A simple and accurate method for extracting