Improved reliability of HfO2/SiON gate stack by fluorine incorporation

240 IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 4, APRIL 2006

Improved Reliability of HfO

₂

/

SiON Gate

Stack by Fluorine Incorporation

Wen-Tai Lu, Chao-Hsin Chiein, Wen-Ting Lan, Tsung-Chieh Lee, Peer Lehnen, and

Tiao-Yuan Huang, Fellow, IEEE

Abstract—Effects of fluorine (F) incorporation on the

relia-bilities of pMOSFETs with HfO2/SiON gate stacks have been

studied. In this letter, fluorine was incorporated during the source/drain implant step and was diffused into the gate stacks during subsequent dopant activation. The authors found that F introduction only negligibly affects the fundamental electrical properties of the transistors, such as threshold voltage V_th, subthreshold swing, gate leakage current, and equivalent oxide thickness. In contrast, reduced generation rates in interface states and charge trapping under constant voltage stress and bias temperature stress were observed for the fluorine-incorporated split. Moreover, the authors demonstrated for the first time that F incorporation could strengthen the immunity against plasma charging damage.

Index Terms—Bias temperature instability (BTI), fluorine (F),

hafnium oxide, plasma charging damage.

I. INTRODUCTION

R

ECENTLY, HfO₂ has emerged as the leading high-k dielectric to replace the conventional SiO₂. However, a number of pending issues need to be resolved before HfO₂ can be inducted into the mainstream ultra-large-scale integra-tion (ULSI) technology. These issues include solving mobility degradation and threshold voltage instability, as well as re-ducing the number of fixed charges and charge traps [1]–[4]. Although there exist numerous literature reports regarding methods to incorporate nitrogen [5], [6] or Si [7], [8] into Hf-based films or stacks so as to improve the film’s quality, however, to the best of our knowledge, the effect of F incorpora-tion on HfO2gate dielectric was seldom addressed [9], [10]. In this letter, fluorine incorporation through fluorine implantation into the source/drain regions was used to evaluate its impact on the constant voltage stress (CVS) instability and negative bias temperature instability (NBTI) of pMOSFETs with HfO₂ gate stacks. Our results clearly show that these degradations are improved in the F-incorporated samples. Moreover, because few studies [9] have been performed regarding plasma charging Manuscript received December 2, 2005; revised January 24, 2006. This work was supported in part by the National Science Council, Taiwan, R.O.C., under Contract 94A0500001. The review of this letter was arranged by Editor A. Chatterjee.

W.-T. Lu, W.-T. Lan, T.-C. Lee, and T.-Y. Huang are with the Department of Electronics Engineering and Institute of Electronics, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C.

C.-H. Chiein is with the Department of Electronics Engineering and Institute of Electronics, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C., and also with National Nano Device Laboratories, Hsinchu 300, Taiwan, R.O.C. (e-mail: [email protected]; [email protected]).

P. Lehnen is with Aixtron AG, Aachen 52072, Germany. Digital Object Identifier 10.1109/LED.2006.871539

effects of HfO2 gate stacks, we have therefore carried out a systematic study in this regard and found that larger antenna ratio will result in much severe degradation. More importantly, our data also show that the plasma charging damage can be significantly improved by the F incorporation into the HfO₂ gate stacks.

II. EXPERIMENT

pMOSFETs with HfO₂/SiON gate stacks were fabricated in this letter. The thin (0.6 nm) interfacial oxynitride layer (SiON) was first grown by rapid thermal processing (RTP) in an N₂O ambient at 700◦C. Subsequently, a 3-nm HfO₂ layer was de-posited by atomic vapor deposition (AVD) using an AIXTRON Tricent system at a substrate temperature of 500 ◦C. Wafers were then annealed in an N2 ambient at 700 ◦C for 20 s to improve the HfO2film quality. Next, a 200-nm polycrystalline silicon (poly-Si) layer was deposited by low-pressure chemical vapor deposition (LPCVD). Then, the gate electrode was pat-terned through lithographic and etching processes. Some wafers then received a fluorine (F, 2 × 1015 cm−2) ion implantation into the source/drain region without removing the photoresist on the gate electrode. This was deliberately performed to avoid the potential complication caused by fluorine-enhanced boron penetration. After photoresist removal, source/drain regions were formed by regular boron implantation, with the dopants activated at 950 ◦C by rapid thermal annealing for 20 s in an N₂ atmosphere. It should be noted that the thermal bud-get of dopant activation also served to diffuse the F species into the HfO2 gate stacks. After passivation layer deposition, contact holes and aluminum metalization were formed. Finally, a forming gas annealing at 400◦C was performed for 30 min to complete the device fabrication.

The equivalent oxide thickness (EOT) of the gate di-electric was extracted from high-frequency (100 kHz) capacitance–voltage (C–V ) curves at strong inversion (EOT = εSiO2/Cinv) without considering the quantum effect.

Charge pumping current was measured with fixed amplitude method at a frequency of 1 MHz [11].

III. RESULTS ANDDISCUSSION

Fig. 1 depicts the typicalId−Vgcurves of pMOSFETs with

HfO2/SiON gate stacks, both with and without F incorporation.

The inset table shows the corresponding transistor parameters. It can be seen that all key device parameters, including the interface state densityNit, EOT,Vth, and gate leakage current, 0741-3106/$20.00 © 2006 IEEE

LU et al.: IMPROVED RELIABILITY OF HfO2/SiON GATE STACK BY FLUORINE INCORPORATION 241

Fig. 1. Typical transfer characteristics of pMOSFETs with HfO2gate stack, both with and without fluorine incorporation.

Fig. 2. (a) Threshold voltage shift(∆V_th) and (b) generation of interface states(∆N_it) and trapping charge (∆Not), both plotted in log scale, as

a function of injection charge density(Vg= −4 V). The degradation was

dominated by∆Not, rather than∆N_it.

are essentially indistinguishable between the samples with and without F incorporation. The inset at the upper right corner shows that the distribution of Vth is not affected by the ad-dition of F. All these data suggest that little or no adverse impact on the fundamental electrical properties is achieved with F introduction.

For the reliability evaluation, negative CVS test was per-formed at 25 ◦C, with the transfer curves measured for monitoring ∆V_th at various stressing times. The results are shown in Fig. 2(a). To reduce the unstable fast charge de-trapping effects [1]–[4], a small positive voltage (0.5 V) with a duration of several seconds was applied to detrap these charges before Id−Vg and charge pumping measurements

without inducing extra damage to the gate stacks. This step thus allows much accurate estimation of the slow trap density without the complication due to the interval variation between voltage stressing and parameter measurement. In other words, the precaution allows us to focus on the slow traps in the gate stacks in this letter. It is clear that the F-incorporated sample always shows smaller∆V_th than the control counter-part. To further gain insights into the degradation mechanism

Fig. 3. Threshold voltage shift (∆V_th) as a function of channel length. Devices were stressed at 25◦C andVg= −4 V.

Fig. 4. (a) ∆V_th and (b)∆N_it and ∆Not, for splits with and without F incorporation, as a function of injection charge density atT = 125◦C under stress voltage of−3.5 V.

during voltage stressing, the interface state generation ∆Nit

and the increase of effective bulk trap density∆Notare plotted as a function of the injection charge density in Fig. 2(b). It should be noted that ∆Not was calculated from ∆Vth by assuming that the charge was trapped at the interface between the dielectric and the substrate. Apparently, ∆N_ot was sig-nificantly larger than ∆N_it, suggesting that the degradation under CVS was dominated by the charge trapping in the bulk of HfO₂ films, rather than the generation of interface states, whether fluorine was incorporated or not. Moreover, F incorporation was found being able to suppress the charge trapping in the bulk of HfO₂ films. Although reduced charge injection during stressing was a plausible cause for the observed improvement in the F-incorporated split, it contradicted with the observation that the improvement became more visible with decreasing channel length, as show n in Fig. 3. If the improvement seen in F-incorporated split was indeed due to reduced injection charges, no dependence of the improve-ment on the channel length should be expected. Therefore, we concluded that the improvement was indeed the result of the F incorporation.

242 IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 4, APRIL 2006

Fig. 5. Time dependence of (a) ∆V_th and (b) ∆N_it under CVS for pMOSFETs with different AARs, both with and without F incorporation. Higher AAR results in much severe degradation, whereas the F-incorporated split exhibits lower∆V_thand∆N_it.

Fig. 4(a) and (b) compares the dependence of threshold volt-age shift and the interface generation, respectively, on injection charge density for splits with and without F incorporation. The BT stress condition was Vg= −3.5 V under 125 ◦C. It can

be seen that F-incorporated films exhibit NBTI improvement similar to fluorine-induced NBTI improvement in SiOF case [12], [13]. The major degradation of NBTI is caused by the positive charge trapping in the films rather than the interface generation, suggesting that the positive charge trapping is not entirely caused by the H+ capturing. Therefore, in addition to positive charge caused by H species, a significant amount of extra trapping centers must be present in the HfO2/SiON

gate stack. Fluorine atoms seem to effectively decorate these trapping centers, leading to reduced degradation.

In our process, the photoresist layer that remained after metal patterning was stripped with O₂plasma in a downstream plasma asher, whose configuration and plasma potential distri-bution could be found in [14]. Using CHARM-2 wafer sensor, it has been previously shown [14] that the potential distribution was highly negative and positive at the wafer center and edge, respectively. Fig. 5 shows the time evolution of the threshold voltage shift and interface state generation for the devices with area antenna ratios (AARs) of either1 × 103or6 × 104, both with and without F incorporation. All measurements were performed on devices located at the same die location (i.e., wafer center). Fig. 4 shows that the hole trapping in the bulk, rather than the interface generation, is the preponderant mecha-nism responsible for the degradation. From the Weibull plot of Vthfor the fresh devices located at the wafer center, it is found that the control devices with AAR of6 × 104depict larger|V_th| values than their counterparts with F incorporation (data not shown). This is consistent with previous results in CVS and NBTI. Moreover, all these results are in-line with the hypothesis that plasma antenna charging effect creates more hole traps in the HfO₂/SiON gate stacks and that F-incorporated devices are more robust to plasma charging effect.

IV. CONCLUSION

In this letter, we found that the reliabilities of pMOSFETs with HfO₂/SiON gate stacks under both CVS and NBTI stresses are significantly improved by the F incorporation. In addition, we demonstrated for the first time that plasma charging effect induces hole trapping in the HfO₂/SiON gate stacks. Finally, we found that the plasma charging effect can be effectively suppressed with F incorporation.

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