應用高介電常數絕緣層與矽奈米微晶粒於超大型積體電路元件之研究

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(1)國立交通大學電子工程學系電子研究所. 博士論文. 應用高介電常數絕緣層與矽奈米微晶粒於超大型積體電路元件之研究 A Study of High-κ Dielectrics and Si Nano-crystals for ULSI Devices 研究生：陳建豪指導教授：雷添福博士趙天生博士. 中華民國九十六年十月.

(2) 應用高介電常數絕緣層與矽奈米微晶粒於超大型積體電路元件之研究 A Study of High-κ Dielectrics and Si Nano-crystals for ULSI Devices 研究生：陳建豪. Student: Jian-Hao Chen. 指導教授：雷添福博士趙天生博士. Advisor: Dr. Tan-Fu Lei Dr. Tien-Sheng Chao. 國立交通大學電子工程學系. 電子研究所. 博士論文 A Dissertation Submitted to Department of Electronics Engineering and Institute of Electronics College of Electrical Engineering and Computer Science National Chiao Tung University in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy in Electronics Engineering October 2007 Hsinchu, Taiwan, Republic of China. 中華民國九十六年十月.

(3) 應用高介電常數絕緣層與矽奈米微晶粒於超大型積體電路元件之研究研究生：陳建豪. 指導教授：雷添福博士趙天生博士. 國立交通大學電子工程學系電子研究所. 摘要 Abstract (in Chinese) 本論文首先對於高介電常數鈷鈦酸(CoTiO3)絕緣層穩定性的改善，提出三種摻雜氮的方法。利用氮氣分子(N2+)或原子(N+)離子，以低能量植入鈷鈦金屬堆疊之中，接著進行氧化，利用電子顯微鏡與 X 光繞射(X-Ray Diffraction)方法均觀察到結晶狀態被氮摻雜抑制，電性量測亦證明了可以降低漏電，提高崩潰電壓，並在電壓加壓下有較佳穩定性。或利用一氧化二氮(N2O)之電漿進行氮摻雜，先以較低的氧化溫度形成鈷鈦酸氧化物，接著進行一氧化二氮電漿處理，之後再經一道高溫熱退火步驟。我們發現以此方法可以有效改善鈷鈦酸絕緣層的熱穩定性，同時提升絕緣層的電性可靠度，絕緣層漏電可以降低大約 4 個數量級，而其崩潰電壓也可提高約 2 V。本論文接著利用兩種新穎的矽前驅物(precursor)以金屬有機氣相沉積法製備高介電常數鉿的矽酸鹽。兩種矽前驅物分別是叔丁基二甲基矽醇(tert-butyldimethyl silanol)，與三叔戊氧基矽醇(tris(tert-pentoxy) silanol)。此論文研究的兩種矽前驅物在常溫常壓下為液態，因此可以提供足夠的蒸氣壓。兩種前驅物中，實驗發現三叔戊氧基矽醇此前驅物不需要氧氣介入反應即可生成矽酸鉿薄膜，而且可以在 250 °C 的低溫下生成平坦的矽酸鉿絕緣層。在此研究中，我們使用一組具備臨場(in situ)製程能力的高真空系統，沉積過程中利用臨場橢圓儀(Ellipsometer)觀察絕緣層成長，探討其成長機制，並利用臨場熱退火與電子能譜儀(XPS)研究薄膜材料特性。其後製作電容元件探討絕緣層之電特性，將薄膜結構變化與電特性比較。此絕緣層被製作成電容探討其電特性，在氫氮混和氣體 i.

(4) 下(4 % H2 + 96 % N2)經過 450 °C 退火，絕緣層介面特性獲得良好的改善。利用臨場製程系統，本論文接著研究矽奈米微晶粒的製備。使用電子束蒸鍍法可在薄氧化層上沉積均勻且平坦的超薄(0.9−3.5 nm)非晶矽層。隨後在未破壞真空的條件下進行臨場快速熱退火(850 °C, 5min)，可以形成自組裝半球狀矽奈米微晶粒。原子力顯微鏡，電子顯微鏡與電子能譜儀被使用於觀察晶粒結構。在較低溫度下(750 °C)可以觀察到未完成的奈米點聚合現象。奈米晶粒先在非晶矽表面成核，接著聚合成較大的晶粒並消耗周圍的非晶矽層，直到其底部與二氧化矽基底層接觸。較薄的非晶矽層可形成較小且較密的晶粒。此研究中得到最小的晶粒半徑約是 5.1 nm，同時亦得到最高的晶粒密度 3.9×1011 cm-2。本論文亦利用臨場電子能譜觀測方法建立一套模型，以信號的強度估計矽奈米微晶粒的尺寸與密度，與實驗結果比較下，驗證出此方法十分具有實用性。最後我們將此種新穎的半球狀矽奈米微晶粒製作成記憶體元件。製作矽奈米微晶粒於 4nm 之穿隧氧化層上，再覆蓋以 17 nm 之阻擋氧化層，製作完成之電容元件觀察到高的電荷儲存密度 4.1×1012 cm-2 (電子+電洞)。將此矽奈米晶粒製作成非揮發性記憶體元件可得到良好的記憶體特性。在±10 V，0.02/0.1 s 的閘極操作電壓下，可以得到約 0.9 V 之臨限電壓變化，在讀寫操作 10000 次之後亦保持住同樣的電壓記憶窗(memory window)。在±15 V 的操作下則可以得到約 2.8 V 的臨限電壓變化量，驗證此矽奈米微晶粒在記憶元件上之實用性。實驗證明這種真空聚合法形成之矽奈米晶粒可應用於非揮發記憶體的製作。. ii.

(5) A Study of High-κ Dielectrics and Si Nano-crystals for ULSI Devices Student: Jian-Hao Chen. Advisors: Dr. Tan-Fu Lei Dr. Tien-Sheng Chao. Department of Electronics Engineering and Institute of Electronics National Chiao-Tung University. Abstract. In this dissertation, three approaches to incorporating nitrogen in CoTiO3 high-κ dielectric films, including the ion implantation of N2+, ion implantation of N+, and N2O plasma treatment, have been investigated. Nitrogen incorporation by ion implantation of N2+ can improve the electrical properties in terms of gate leakage, breakdown voltage and time-to-breakdown (TBD). To reduce the impinging mass of implanted ion species, N+ ion implantation has been used. The same trends can be found as those produced using N2+. A N2O plasma treatment is also an excellent method to improve the electrical properties, exhibiting better-behaved C-V curves, lower gate leakage currents and higher breakdown voltages. Two silanol precursors, tert-butyldimethyl silanol (BDMS) and tris(tert-pentoxy) silanol (TPOS), are evaluated as silicon precursors for hafnium silicate deposition with tetrakis-(diethylamido) hafnium (TDEAH). BDMS has one OH group, which should react with chemisorbed TDEAH. However, the other t-butyl and methyl groups can passivate the substrate surface, and stop the further absorption of TDEAH. Carbon-free hafnium silicate thin-films are deposited by MOCVD using alternative pulses of TDEAH and TPOS precursors. Hafnium silicates with high silicon contents (Hf1-xSixO2, x >0.5) are deposited at 250 °C without additional oxidants. MOS capacitors are fabricated for electrical iii.

(6) characterizations. A forming gas anneal can improve the hafnium silicate interface quality. This low-temperature process could be promising for TFT or optoelectronic applications. Hemispherical Si nanocrystals are self-assembled using an in-situ thermal agglomeration technique. Ultrathin (0.9–3.5 nm) a-Si films are deposited on a 4-nm tunnel-oxide layer using electron-beam evaporation. An in-situ annealing can then activate the thermal agglomeration of Si and transform the ultrathin a-Si films into Si nanocrystals. The Si agglomeration process is evaluated with various processing parameters such as annealing temperatures, surface oxide conditions, and initial Si film thickness. Also, it is demonstrated that XPS measurements can effectively provide the information of the nanocrystal agglomeration. Calculations are made based on the photoelectron attenuation theories, and a simple model is proposed. Comparisons between the calculated results and the experimental data have shown a fairly good match. The fabrication of a Si nanocrystal-embedded nonvolatile memory has been demonstrated using a thermal agglomeration technique. MOS capacitors and MOSFETs embedded with hemispherical Si nanocrystals are fabricated and characterized. A stored charge density of 4.1×1012 cm-2 (electron + hole) is obtained with a highest nanocrystal density of 3.9×1011 cm-2. Uniform FN tunneling is used to program and erase the Si nanocrystal floating-gate n-MOSFETs. A Vt window of 0.9 V is achieved under P/E voltages of ±10 V for 0.02/0.1 s. The memory device also shows good endurance and charge retention behaviors after 10000 P/E cycles. Increasing P/E voltages to ±15 V creates a large memory window (>2.7 V) with the proposed memory device. After a retention test for 100 hours, a memory window of 1 V is maintained. The retention characteristics have shown little temperature dependence with the Si nanocrystal memories, indicating that the charge-loss process is determined by the direct tunneling from nanocrystals into the oxide/Si-substrate interface states.. iv.

(7) 誌謝 Acknowledgement (in Chinese). 在博士班的研究生涯中，我很幸運地可以在雷添福教授與趙天生教授的指導下，學習做研究與解決問題的方法。本論文的完成，首先要感謝兩位指導教授多年來的指導與教誨。老師們在實驗與論文的方向上，提供了很多寶貴的意見與協助，使論文得以順利的完成。在遇到瓶頸的時候，也因為老師們的鼓勵與建議，才得以持續下去，老師們的體恤與包容，學生衷心感激。更感謝兩位老師讓我有機會到加拿大國家研究院(NRC)進行研究，讓我不只在專業的知識上多有收穫，在人生歷練上也獲得許多成長。在加拿大的研究日子裡，要特別感謝 NRC 微結構研究所(IMS)的合作計畫主持人 Dr. Dolf Landheer，對我在生活上、實驗上、知識上的提攜與照顧。從他做實驗的熱忱與嚴謹的研究態度，我學到分析問題的方法與面對困難不放棄的精神。因為他盡心盡力的指導與支持，我才能在實驗與研究上獲得進展。感謝 Surfaces and Interfaces group 的 Dr. Xiaohua Wu, Dr. John Hulse, Irwin Sproule, Simona Moisa, Jeff Fraser, Terry Quance, Dave Prince, Guy Parent，還有 IMS 的 Eric Estwick, Martha Tomlinson, Mark Malloy 等人在實驗上的協助。感謝一起實驗的 Dr. Minsoo Lee 與 Jian Liu，讓做實驗的日子更添動力。感謝國科會在學習經費上的支助，與台灣代表處科學組的長官在生活上的關心。感謝李名鎮學長指導我量測技術，讓我獲益良多。感謝潘同明、李介文、張子云、王哲麒、俞正明、李宗霖、謝明山、李耀仁諸位學長的關心與照顧。還有柏儀、碩廷、信強、紹銘、獻德、育賢、德慶、久盟、美錡、國誠、余俊、志仰、文政、偉成、家豪、鳴汶、雅欣、浩偉、宗諭、國興，與其他在學習過程中共事過的同學與學弟妹，讓生活增色不少。感謝一同作研究的學弟，松齡與宗彬，在相互討論之中於專業知識上共同成長。還要特別向交大半導體中心與國家奈米實驗室裡所有辛苦的工作人員說聲謝謝。感謝我的家人，尤其感謝父母親對我的養育與栽培。這麼多年來，因為有父親與母親毫不保留的愛與支持，我才得以擁有成長與學習的機會。謝謝我的女友，從相識以來生活中的各種喜怒哀樂，其實都是人生的幸福。 v.

(8) Contents Abstract (Chinese)………………………………………………………i Abstract (English)……………………………………………………...iii Acknowledgement (Chinese)…………………………………………...v Contents…………………………………………………………………vi Table Captions………………………………………………………….ix Figure Captions………………………………………………………….x Chapter 1 Introduction ..........................................................................1 1.1 General Background..........................................................................................1 1.2 Motivation...........................................................................................................4 1.3 Organization of the Thesis ................................................................................7. Chapter 2 Experimental Techniques ..................................................12 2.1 Ultrahigh Vacuum in-situ Processing (ISP) System......................................12 2.2 Metal Organic Chemical Vapor Deposition (MOCVD) ...............................12 2.3 Material Characterization Techniques ..........................................................13 2.3.1 X-ray Photoelectron Spectroscopy (XPS)...............................................13 2.3.2 High Resolution Transmission Electron Microscopy (HRTEM) .........14. Chapter 3 Performance Improvement of CoTiO3 High-κ Dielectrics with Nitrogen Incorporation ................................................19 3.1 Introduction......................................................................................................19 3.2 Experimental ....................................................................................................21 3.3 Results and Discussion.....................................................................................22 3.4 Summary...........................................................................................................26. vi 171.

(9) Chapter 4 Characterization of Hafnium Silicates by Pulse-Mode MOCVD using [(C2H5)2N]4Hf and (C4H9)(CH3)2SiOH or [(C5H11)O]3SiOH for Advanced High-κ Gate Dielectrics ..41 4.1 Introduction......................................................................................................41 4.2 Experimental ....................................................................................................45 4.2.1 MOCVD Hf Silicates using TDEAH and BDMS with O2 .....................45 4.2.2 Low-Temperature MOCVD Hf Silicates using TDEAH and TPOS ....47 4.3 Results and Discussion.....................................................................................48 4.3.1 MOCVD Hf Silicates using TDEAH and BDMS with O2 .....................48 4.3.2 Low-Temperature MOCVD Hf Silicates using TDEAH and TPOS ....51 4.4 Summary...........................................................................................................53. Chapter 5 Physical Characterization of Si Nanocrystals Self-assembled by in-situ Rapid Thermal Annealing of Ultrathin a-Si on SiO2 ...........................................................66 5.1 Introduction......................................................................................................66 5.2 Experimental ....................................................................................................68 5.3 Results and Discussion.....................................................................................71 5.3.1 in-situ XPS Investigation of the Si-Nanocrystal Self-Assembly............72 5.3.2 Effects of the Annealing Temperature on the Silicon Agglomeration and Nanocrystal Formation ..................................................................75 5.3.3 Effects of the Native Oxide Growth on the Silicon Agglomeration and Nanocrystal Formation..........................................................................79 5.3.4 Dependence of Nanocrystal Sizes and Densities on the Initial a-Si Thickness ................................................................................................83 5.3.5 Estimation of the Si-Nanocrystal Size and Density by in-situ XPS vii 172.

(10) Analysis ...................................................................................................85 5.4 Summary...........................................................................................................90. Chapter 6 Electrical Characteristics of Nonvolatile Memory Devices with Embedded Hemispherical Si Nanocrystals ..............122 6.1 Introduction....................................................................................................122 6.2 Experimental ..................................................................................................124 6.2.1 Si-Nanocrystal Embedded MOS Capacitors ........................................124 6.2.2 Si-Nanocrystal Embedded MOSFETs...................................................125 6.3 Results and Discussion...................................................................................126 6.3.1 Si-Nanocrystal Embedded MOS Capacitors ........................................126 6.3.2 Si-Nanocrystal Embedded MOSFETs...................................................129 6.4 Summary.........................................................................................................133. Chapter 7 Conclusions and Recommendations for Future Work....147 7.1 Conclusions.....................................................................................................147 7.2 Recommendations for Future Work.............................................................151. References List ......................................................................................155 Curriculum Vitae ..................................................................................168 Publication List .....................................................................................169. viii 173.

(11) Table Captions Chapter 3 Table 3.1 The resultant equivalent-oxide-thickness (EOT), interface layer, CoTiO3 dielectric thickness, total thickness, effective κ-value, and flatband voltage for all samples.........................................................................................................................28 Chapter 4 Table 4.1 Flat-band voltages (VFB), positive fixed charge densities (Nf), the equivalent oxide thickness (EOT) and effective dielectric constant (κeff) extracted from C-V characteristics in Fig. 4.11. The Hf0.18Si0.82O2 film was deposited by pulse-mode MOCVD using TDEAH and TPOS alternative pulses. The forming gas annealing (FGA) was performed after the deposition. Aluminum-gate electrodes were used.....55 Chapter 5 Table 5.1 Split conditions for the Si agglomeration experiments. This table has been re-arranged for the ease of viewing. The samples are actually numbered in sequence. ......................................................................................................................................94 Table 5.2 Ex-situ and/or in-situ post-deposition treatments. The process steps are in sequence from top to bottom. For example, the sample 1328 was removed from the UHV system after the a-Si deposition, immersed into freshly prepared SPM for 10 min, treated with a dilute-HF dip, and then reloaded into UHV for the in-situ RTA. .95 Table 5.3 Surface roughness (root-mean-squared) measured by AFM. The roughness data were obtained from 1-μm2 AFM measurements. The experimental conditions for each sample are also listed...........................................................................................96 Chapter 6 Table 6.1 Flat-band voltage shifts and stored charge densities extracted from C-V results in Fig. 6.5; the densities and base radii of Si nanocrystals are also listed......135. ix 174.

(12) Figure Captions Chapter 1 Fig. 1.1 Moore’s law for microprocessors. Exponential increase of transistor counts as a function of time for generations of microprocessors has been substantiated [2]. .....10 Fig. 1.2 Estimated voltage (Vdd : input voltage / Vth : threshold voltage) and power consumption ( PLEAK : power induced by leakage current / PDYNAMIC : dynamic power consumption) trends. All parameters are taken from ITRS 2001 [4]. .........................10 Fig. 1.3 Gate leakage current density (Jg) versus equivalent oxide thickness (EOT) of the SiOxNy and SiO2 gate dielectrics [8]. Corresponding gate channel lengths of the data points (Lg) are marked. ......................................................................................... 11 Chapter 2 Fig. 2.1 UHV processing facility for 4 inch wafer. .....................................................16 Fig. 2.2 Chemical bonding structure of the tetrakis diethyl-amido hafnium (TDEAH) ......................................................................................................................................16 Fig. 2.3 Schematic view of MOCVD system. .............................................................17 Fig. 2.4 Schematic of the relevant energy levels for XPS binding energy measurements. Ekin is kinetic energy of the photoelectron, h is Plank’s constant, ν is the photon frequency, Eb is the binding energy, Øs is the work-function of the sample, and Øspec is the work-function of the spectrometer. Note that a conducting specimen and spectrometer are in electrical contact and thus have common Fermi levels. Kinetic energies of photo-ejected electrons are given by Equation (2.1) [50]. ........................17 Fig. 2.5 Schematic view of the STEM system equipped with EDS and EELS. ..........18 Chapter 3 Fig. 3.1 TEM pictures for samples of CoTiO3 oxidized at 800 °C for 10 min (a) without and (b) with nitrogen ion implantation. ..........................................................29 Fig. 3.2 High frequency C-V curves measured at 100 kHz for all samples oxidized at 800, 850 and 900 °C with or without nitrogen implantation. ......................................30 Fig. 3.3 Current-voltage characteristics of samples oxidized at 900 °C for 10 min with and without nitrogen implantation. (a) Gate leakage current density vs. gate voltage. (b) Weibull distribution of gate leakage current density at Vg = 1V. (c) Weibull distribution of breakdown voltage ...............................................................................31 x 175.

(13) Fig. 3.4 Current-voltage characteristics for samples oxidized at 850 °C for 10 min (a) without and (b) with nitrogen implantation after constant voltage stress at Vg = 2V for 100 s. ............................................................................................................................33 Fig. 3.5 XRD spectra for a CoTiO3 films oxidized at 850 °C without (line a) and with (line b) nitrogen implantation. .....................................................................................34 Fig. 3.6 Electrical measurements for samples oxidized at 850 °C for 5 min with and without N+ ion implantation. (a) Gate current density vs. gate voltage. (b) Weibull distribution of gate leakage current-density at Vg = 1V. (c) Weibull distribution of breakdown voltage. ......................................................................................................35 Fig. 3.7 SIMS profiles for a sample with 20 W N2O plasma treatment.......................37 Fig. 3.8 Oxygen SIMS profiles for samples without N2O plasma or with N2O plasma treatments using powers of 10, 15, and 20 W. .............................................................38 Fig. 3.9 Electrical characteristics for samples with and without N2O plasma treatment: (a) C-V characteristics, (b) Gate current density vs. gate voltage, (c) the Weibull distribution of gate leakage current-densities at Vg = 1V, and (d) the Weibull distribution of breakdown voltages..............................................................................39 Chapter 4 Fig. 4.1 Illustration of the MOCVD chamber equipped with a liquid injection system (for Hf precursor) and a bubbler (for Si precursor); the sample wafer is sitting face-down on a quartz-ring holder and heated by a set of halogen lamps...................56 Fig. 4.2 Illustration of the sample stage in MOCVD chamber; an in-situ Ellipsometer system is also mounted to the chamber for real time thickness measurements. ..........56 Fig. 4.3 The BDMS mass spectrum. A molecular nitrogen flow of 100 sccm was purged through the BDMS bubbler. A silicon wafer was loaded onto the stage and heated to 500 °C during the measurement. The bubbler and the CVD chamber walls were held at 40 °C and ~120 °C, respectively. ............................................................57 Fig. 4.4 Trace of in-situ Ellipsometric measurements for a pulse-mode deposition. There are 7 steps in a deposition cycle. After the molecular oxygen pulse, a long pump-down step was added. The substrate temperature was 550 °C for this deposition. ......................................................................................................................................58 Fig. 4.5 Traces of in-situ Ellipsometric measurements and mass spectra readings for depositions at (a) 450 and (b) 550 °C: (dash line) O2, () octane, () species from BDMS, () film thickness. ............................................................59 xi 176.

(14) Fig. 4.6 Illustration showing the possible reaction routes for chemisorbed TDEAH and BDMS precursors. The oxidation step can replace the Si-C bonds with Si-O bonds which are more reactive with TDEAH precursors. ...........................................60 Fig. 4.7 AFM image of a 4-nm Hf silicate film deposited at 550 °C using TDEAH and BDMS with O2. The rms roughness is 1.42 nm measured in the scan area. The image size is 1 μm × 1 μm. The color scale indicates the contrast range for a 20 nm height. ......................................................................................................................................61 Fig. 4.8 TEM micrographs of Hf silicate films deposited at 550 °C using TDEAH and BDMS with O2: (a) spike annealed at 800 °C in vacuum and then capsulated in situ with an amorphous silicon layer; (b) the same sample with an additional ex-situ N2 anneal at 1000 °C for 30 seconds.................................................................................61 Fig. 4.9 (a) C 1s, (b) O 1s, (c) Si 2p, and (d) Hf 4f XPS spectra for an Hf0.18Si0.82O2 film deposited by pulse-mode MOCVD using TDEAH and TPOS alternative pulses. After a surface sputtering, the carbon signals became lower than the detection limits. ......................................................................................................................................63 Fig. 4.10 HRTEM picture of the as-deposit Hf0.18Si0.82O2 film deposited by pulse-mode MOCVD using TDEAH and TPOS alternative pulses. ...........................64 Fig. 4.11 (a) C-V curves of the Hf0.18Si0.82O2 films with and without a forming gas annealing. The gate bias was swept from negative to positive during the measurement. (b) Bi-directional C-V curves of the Hf0.18Si0.82O2 film annealed in forming gas at 450 °C for 20 min. Noticeable frequency dispersion is observed below midgap...............64 Fig. 4.12 Gate current density vs. oxide bias for the Hf0.18Si0.82O2 samples; post deposition annealing was performed in forming gas. ..................................................65 Chapter 5 Fig. 5.1 Illustration of the thermally-induced Si agglomeration; an ultrathin a-Si layer was deposited by electron-beam evaporation under vacuum and then annealed in situ to form silicon nanocrystals. The duration of the in-situ rapid thermal annealing was 1–10 min. With the annealing temperature at 750 °C or higher, evidence of Si-dot agglomeration could be observed. ...............................................................................97 Fig. 5.2 (a) O 1s and (b) Si 2p XPS core-level spectra acquired before (1) and after (2) the 3.5-nm a-Si deposition and during the subsequent in-situ annealing (3–5)...........98 Fig. 5.3 (a) Evolution of the XPS O 1s spectra recorded in situ during the a-Si deposition. All peaks were referenced to the Si4+ 2p (Si-O) peak at binding energy of xii 177.

(15) EB = 103.3 eV. (b) O 1s peak intensity attenuation versus the deposited a-Si thickness. The intensities (peak areas) were taken from Fig. 5.2a, and normalized to the initial O 1s spectrum recorded before the a-Si deposition. (c) Cross-sectional TEM micrograph of the a-Si/tunnel-oxide/Si(100) structure. ..................................................................99 Fig. 5.4 SEM micrographs of Si-dots agglomerated from a 3.5-nm-thick a-Si layer after in-situ annealing at 850 °C for (a) 1 and (b) 10 min. The scale bar is 200 nm. 102 Fig. 5.5 (a) Densities and (b) base radii of Si-dots agglomerated from a 3.5-nm-thick a-Si layer after in-situ annealing at 850 °C for different periods. The data are obtained by analyzing SEM images using a digitalized program. The error bars in (b) indicate one standard deviation. The lines are drawn to guide the eyes..................................102 Fig. 5.6 SEM images of Si-dot agglomeration in a 3.5-nm a-Si layer after in-situ RTA at (a) 750 °C, (b) 800 °C, and (c) 850 °C for 5 min. The scale bars indicate 200 nm. ....................................................................................................................................103 Fig. 5.7 (a) Densities and (b) base radii of Si-dots agglomerated in a 3.5-nm a-Si layer after in-situ RTA at 750, 800, and 850 °C for 5 min. The data are obtained by analyzing SEM images using a digitalized program. The error bars in (b) indicate one standard deviation. The lines are drawn to guide the eyes.........................................103 Fig. 5.8 AFM images of samples annealed at (a) 700, (b) 750, (c) 800, and (d) 850 °C for 5 min. A 3.5-nm-thick a-Si layer was deposited prior to the in-situ RTA. The sizes of all AFM images are 1 μm by 1 μm. The color scale indicates a full range of 5 nm for (a) and a full range of 40 nm for others. The rms roughness results for the annealed samples are (a) 0.181, (b) 5.286, (c) 4.759, and (d) 5.038 nm. ..................104 Fig. 5.9 (a) An magnified portion of Fig. 5.8b and (b) the AFM profile along the Y–Y’ cross-section. Recessed areas are observed near the agglomerated Si-dots. .............105 Fig. 5.10 (a) An magnified portion of Fig. 5.8b and (b) the AFM profile along the X–X’ cross-section. The silicon coalescence and the beginning of agglomeration caused the dot formation on a flat silicon surface......................................................106 Fig. 5.11 (a) Cross-sectional TEM micrograph of the sample in Fig. 5.8b. (b) Magnified image shows a twin boundary (indicated by a dash line) in the Si nanocrystal. ................................................................................................................107 Fig. 5.12 Cross-sectional TEM micrograph of the sample in Fig. 5.8b; a nanocrystal partially-agglomerated on the remaining a-Si layer is clearly revealed. ...................107 Fig. 5.13 (a) O 1s and (b) Si 2p core-level spectra measured by ex-situ XPS with the xiii 178.

(16) as-deposited () and nitrogen annealed () a-Si samples. An ultrathin a-Si (3.5 nm) film was deposited on the tunnel-oxide/Si(100) substrate and then annealed ex situ at 850 °C for 5 min in N2 ambient. All peaks are referenced to the Si0 2p (Si substrate) peak at binding energy of EB = 99.3 eV. ....................................................................108 Fig. 5.14 (a) O 1s and (b) Si 2p core-level spectra measured by in-situ XPS with the as-deposited (), in-situ oxidized (), and then in-situ annealed () sample. A 3.5-nm a-Si layer was deposited on the tunnel-oxide/Si(100) substrate followed with a low-pressure (12 milli-Torr) oxidation step at 650 °C for 20 min, and then annealed under UHV at 850 °C for 5 min. All peaks are referenced to the Si0 2p (Si substrate) peak at binding energy of EB = 99.3 eV. ....................................................................109 Fig. 5.15 XPS Si 2p spectrum for the oxidized sample in Fig. 5.14b: (solid circle) measured, (dash lines) fitted peaks, (solid line) sum of fitted peaks. A 3.5-nm a-Si layer was deposited on tunnel-oxide/Si(100) and then oxidized in situ at 650 °C for 20 min under a low-pressure (12 milli-Torr) O2 ambient prior to the in-situ XPS measurement. ............................................................................................................. 110 Fig. 5.16 (a) O 1s and (b) Si 2p spectra measured by in-situ XPS after a 5-nm a-Si layer was deposited () and then treated with SPM and a dilute-HF dip (). The a-Si film was deposited on a tunnel-oxide/Si(100) substrate and then immersed into a sulfuric acid hydrogen peroxide mixture (SPM: 3 parts H2SO4 + 1 part H2O2) for 10 min prior to a 2-min dilute-HF dip. All peaks are referenced to the Si0 2p (Si substrate) peak at binding energy of EB = 99.3 eV. .................................................................... 111 Fig. 5.17 O 1s spectrum for the SPM and HF treated sample shown in Fig. 5.16a: (blank circle) measured, (dash lines) fitted peaks, (solid line) sum of fitted peaks, (dot line) residual errors between measured and fitted data. A 5-nm a-Si film was deposited on a tunnel-oxide/Si(100) substrate and then treated in a sulfuric acid hydrogen peroxide mixture (SPM: 3 parts H2SO4 + 1 part H2O2) for 10 min. A 2-min dilute-HF dip was performed to remove the surface oxide prior to XPS measurement. ....................................................................................................................................112 Fig. 5.18 SEM micrograph of Si agglomeration after an amorphous Si layer (initially 5-nm-thick) was treated with an SPM immersion step, a dilute-HF dip, and then an in-situ annealing at 850 °C for 5 min......................................................................... 113 Fig. 5.19 AFM image of Si agglomeration after an amorphous Si layer (initially 5-nm-thick) was treated with an SPM immersion step, a dilute-HF dip, and then an in-situ annealing at 850 °C for 5 min......................................................................... 113 Fig. 5.20 (a) SEM image and (b) dot-size distribution of Si nanocrystals agglomerated xiv 179.

(17) after in-situ rapid thermal annealing of a 3.5-nm-thick a-Si layer at 850 °C for 5 min. The scale bar in the SEM image indicates 500 nm in length..................................... 114 Fig. 5.21 (a) SEM image and (b) dot-size distribution of Si nanocrystals agglomerated after in-situ rapid thermal annealing of a 2.5-nm-thick a-Si layer at 850 °C for 5 min. The scale bar in the SEM image indicates 500 nm in length..................................... 115 Fig. 5.22 (a) SEM image and (b) dot-size distribution of Si nanocrystals agglomerated after in-situ rapid thermal annealing of a 1.8-nm-thick a-Si layer at 850 °C for 5 min. The scale bar in the SEM image indicates 500 nm in length..................................... 116 Fig. 5.23 (a) ADF-STEM image of hemispherical Si nanocrystals on a thin oxide layer; (b), (c), and (d) HRTEM micrographs. The Si-nanocrystals were obtained by in-situ annealing of a 1.8-nm a-Si thin layer at 850 °C for 5 min. .......................................117 Fig. 5.24 AFM image of the Si-dot agglomeration after in-situ annealing of an ultrathin (0.9 nm) a-Si layer at 850 °C for 5 min. The AFM scan area is 500 nm by 500 nm, and the root-mean-square roughness is measured 0.549 nm. The color scale indicates a full range of 10 nm................................................................................... 118 Fig. 5.25 (a) Densities and (b) base radii of Si dots as a function of the initial a-Si thickness; the nanocrystal dots were thermally agglomerated after in-situ annealing of ultrathin a-Si layers at 850 °C for 5 min. The data were obtained by analyzing SEM or AFM images using a digitalized program. The error bars in (b) indicate one standard deviation. The lines are drawn to guide the eyes. ...................................................... 119 Fig. 5.26 Schematic showing a square unit area of the a-Si film; the length and width of the unit area are both L. The initial thickness of the a-Si layer is TSi....................120 Fig. 5.27 (a) Top-view and (b) cross-sectional schematics of a hemispherical Si-dot on the tunnel-oxide surface; the dot radius is R, and the dot formation occurs in a square unit area sized L2........................................................................................................120 Fig. 5.28 Normalized XPS peak intensity () and dot density (), both calculated based on a simple attenuation model, as a function of the k ratio; the k ratio is defined as the dot radius divided by the initial Si thickness. The normalized intensity measured by in-situ XPS () is also indicated. Experimental XPS data were obtained during the deposition of a 1.8-nm a-Si thin film and the subsequent in-situ annealing at 850 °C for 5 min. ...................................................................................................121 Chapter 6 Fig. 6.1 Schematic of a MOS capacitor with embedded Si nanocrystals. .................136 xv 180.

(18) Fig. 6.2 Schematic of a MOSFET device with embedded Si nanocrystals. ..............136 Fig. 6.3 C-V traces of a MOS capacitor embedded with Si nanocrystals; the gate-bias sweeps are ±10 V (), ±8 V (), ±5 V (), and ±3 V (&). The nanocrystal dots are formed by the in-situ RTA of a 3.5-nm a-Si film at 850 °C for 5 min.......................137 Fig. 6.4 C-V traces of MOS capacitors embedded with Si nanocrystals; the bias sweeps are of (a) ±10 V, (b) ±8 V, and (c) ±5 V. The nanocrystal dots are formed by in-situ RTA of a 3.5-nm a-Si film at 850 °C for 5 min and followed with ex-situ rapid thermal oxidation at 700 °C (), 800 °C (), and 900 °C () for 60 s. .................139 Fig. 6.5 C-V traces of MOS capacitors with (line+symbol) and without (dashed line) Si nanocrystals agglomerated from () 2.5 nm, () 1.8 nm, and () 0.9 nm thin a-Si layers. The gate bias is swept from 10 V to -10 V and back to 10 V. ........................140 Fig. 6.6 Threshold voltage shifts as a function of (a) program and (b) erase time for a Si-nanocrystal floating-gate memory; different program/erase gate voltages (±8, ±10, ±12, and ±15 V) are used. The memory device is erased (programmed) at the corresponding negative (positive) gate bias for 1 s before the programming (erasure) starts. ..........................................................................................................................141 Fig. 6.7 (a) Endurance characteristics of nanocrystal-embedded MOSFETs; program and erase voltages of ±10 V were pulsed for 0.02 and 0.1 s, respectively. (b) Data retention characteristics after 10000 program/erase cycles. The programming and erasing conditions are the same as those in (a). .........................................................142 Fig. 6.8 Data retention characteristics for () programmed and () erased nonvolatile memory devices; (inset) corresponding drain current-gate voltage (Id-Vg) curves. The gate pulse voltages are ±15 V for 1 s. ........................................................................143 Fig. 6.9 Retention characteristics tested at room temperature and at 85 °C; the devices are programmed/erased at a gate bias of ±15 V for a pulse width of 1 s. ..................144 Fig. 6.10 Retention characteristics tested at room temperature and at 85 °C; the devices are programmed/erased at +15 and -12 V with a pulse width of 1 and 0.1 s, respectively. ...............................................................................................................145 Fig. 6.11 Retention characteristics tested at room temperature; the devices are programmed/erased for 1 s at a gate bias of +15 and -12 V, respectively..................146. xvi 181.

(19) Chapter 1 Introduction. 1.1 General Background. Significant progress in complementary metal oxide semiconductor (CMOS) integrated circuit (IC) technology has been made since the late 1980’s. This was promoted by microelectronic revolution in which people’s life style turned from a dream world into reality. However, in order to maintain this revolution, the industry has to solve several technological requirements that are related to performance and production cost. To satisfy the need of growing complexity of systems such as computer and multimedia devices, functionality in microprocessors and capacity in memory chips must be continuously expanded. According to Moore’s law [1], an exponential growth in the number of transistors per very large scaled integration (VLSI) chip was predicted and has been proven true as shown at Figure 1.1 [2]. To maintain a competitive edge in the microelectronic business, a tremendous effort in reducing production costs is also required. These challenges have been overcome by scaling down the unit components in VLSI chips, the metal oxide semiconductor field effect transistor (MOSFET). Device scaling prompted consumer’s increased demand to maximize performance and minimize production cost of VLSI chips, resulting in the acceleration of miniaturization in microelectronic devices. The International Technology Roadmap for Semiconductors (ITRS) predicts the scaling technology over the next 15 years and identifies technical challenges for the global semiconductor industry. According to ITRS 2005, several limitations to device scaling are being encountered in the sub-0.1 μm technology regime [3]. Gate 1.

(20) dielectric thickness (d) for MOSFET is one of the most critical dimensions to be surmounted, and it is expected to reduce to less than 1 nm of EOT (Equivalent Oxide Thickness; equivalent SiO2 gate thickness with corresponding dielectric performance) very soon. One reason that Si-based devices have been dominant in microelectronic fabrication is that Si has a stable multi-functional oxide, SiO2, easily produced by furnace oxidation or deposition. In spite of the excellent properties of SiO2 as a gate dielectric material, such as high band gap energy, low interface defect density and stable oxide formation on Si, it exhibits a significant amount of tunneling leakage current when its thickness is scaled to below 2 nm [3-5]. This tunneling current produce noticeable power consumption at the standby condition of the device. Dynamic and passive power density (leakage power) trends shown in Figure 1.2 suggest that passive power consumption per unit gate area induced by gate tunneling current and sub-threshold current will continuously increase with device scaling and surpass active power density in several years [4]. Therefore, the replacement of SiO2 with a high dielectric constant (k) material has been motivated for the deep sub-micron regime [6, 7]. High-k gate dielectric material can generate the equivalent charge in the channel region while allowing a sufficiently thick layer to be used. This will lead to a substantial reduction in tunneling leakage current. Nitrogen incorporated SiO2 has already replaced SiO2 for more than 3 years in advanced devices with EOT of sub-3 nm. Silicon oxy-nitride is, however, regarded as a temporary solution until the reliability of high-k gate dielectric material is completely verified at the 1 nm-EOT device, because of the limitation in scalability as shown in Figure 1.3 [8]. The implementation of high-k gate dielectrics is expected to be a must for the after the silicon oxy-nitride reaches its limit. 2.

(21) Because of the fast development of IC technology, the consumer electronic products have become more affordable and been widely adopted. People have been more and more relying on digitalized mobile devices, for example the cell phones, digital cameras, and PDAs. In the needs of running digitalized electronic devices and data storage, semiconductor memory devices have become important components [9]. While the portable devices quickly summon a huge popularity, low-cost large-volume nonvolatile memories are eagerly needed by the users for their office documents, research data, high-resolution photos and newest music, among all the other digitalized information to be kept. Nonvolatile memory devices can keep their final electrical states without continuous power supply. Therefore they reduce the power consumption of portable devices, which leads to a longer operation time between recharging. Just like the CMOS logic IC, the nonvolatile memory devices also need to be down-scaled to increase the storage volume per chip and reduce the cost of ownership. Conventional polycrystalline-silicon-based floating-gate (FG) nonvolatile memory devices use a single FG layer to store charges [9]. However, the data reliability is strongly limited by the isolation oxide quality. One charge leakage path created in the isolation oxide can discharge the entire FG and cause a fatal data loss. Therefore it is critical to maintain the oxide robustness, which casts difficulties in scaling the oxide thickness. In recent years, nanocrystal-based memory devices have drawn great attention due to their scaling advantages over the conventional nonvolatile memories [10]. The nanocrystal memory device has many discrete nanocrystal dots as distributed storage nodes. A local leaky path can only affect a few storage nodes (dots) near it, which prevents a serious charge loss. Therefore, nanocrystal floating-gate memories can alleviate the tunnel-oxide scaling issues and as a result, enhance the device operating speeds with thin tunnel-oxide layers [10]. 3.

(22) 1.2 Motivation. Nitrogen incorporation in CoTiO3 gate dielectrics According to recent reports [11-25], optimized treatments which incorporate nitrogen have resulted in a significant improvement in the high-κ dielectric properties. Nitridation of the silicon surface can reduce the growth of an interfacial layer. Plasma nitridation after deposition of the high-κ dielectric can recover the degraded mobility. The advantages of nitrogen incorporation are the increase of the κ-value, the increase of the temperature of crystallization, the reduction of the leakage, reasonable VFB, and reduced boron penetration [11-24]. The material and electrical properties of CoTiO3 high-κ dielectrics have been investigated in earlier reports [26, 27]. In present work, nitrogen incorporation using N2+/N+ ion implantation or N2O plasma treatment to improve this CoTiO3 films are investigated. It is found that the nitrogen incorporation using either ion implantation or plasma treatment can significantly improve the electrical performance of CoTiO3 high-κ dielectrics.. Hf-silicate gate dielectrics deposited by MOCVD HfO2 crystallizes at low temperatures and it is desirable to find a gate dielectric which remains amorphous during device processing where temperatures can reach as high as 1050 °C [28]. Increasing the Si concentration in hafnium silicate increases the crystallization temperature and the silicon/dielectric barrier height but reduces the dielectric constant. It has been estimated that SiO2 mole fractions, ([SiO2]/([SiO2]+[HfO2]) will be required to be > 75 mol% to avoid phase separation and crystallization [29] and films with 81 mol% SiO2 were shown to be amorphous 4.

(23) and thermally stable in a silicon-capped structure upon heating to 1050 °C [30]. The incorporation of nitrogen reduces significantly the required mole fraction of SiO2 [31] but it remains to be demonstrated that such high N concentrations can be incorporated without introducing other electrical defects [32]. Gordon et al. [33] have shown that tetrakis-(diethylamido) hafnium (TDEAH) can be used with tris(t-butoxy)silanol (TBOS) to produce Hf silicate by atomic layer deposition (ALD) and surmised that similar reactions would occur between other alkylamides and tris(t-alkoxy) silanols. Deposition rates, higher than expected from a bulky precursor like TBOS, were reported along with SiO2 mole fractions as high as 75 mol%. This was explained by a mechanism that involves the absorption of two TBOS molecules for each molecule of the alkylamide [34]. However, TBOS is difficult to use because it is a solid at room temperature with a vapor pressure of ~15 Torr at 115 °C [35]. In this work, we report the use of two novel silanol precursors for metal-organic chemical vapor deposition (MOCVD) and ALD with TDEAH. Both silanol precursors are liquids at room temperature and were vaporized using a simple bubbler. The first, t-butyldimethyl silanol (BDMS), has been used to produce low silica content hafnium silicate films by MOCVD [36]. The second, tris(t-pentoxy) silanol (TPOS), is an analogue of TBOS but with a higher vapor pressure. In fact, TBOS is a solid at room temperature which melts at 63-65 °C and boils at 205-210 °C while TPOS is a liquid which boils at 96-99 °C (at 2.5 Torr).. Self-assembled Si nanocrystals The surface coalescence of a-Si during an ultra-high vacuum (UHV) annealing was first observed by Sakai et al [23]. The growth of hemispherical grained (HSG) Si islands on the a-Si surface was explained by the segregation of diffusive Si atoms 5.

(24) around surface nucleation centers [23]. Since then the resulted HSG structure has been widely adopted in the dynamic random-access-memory (DRAM) devices [37] to enhance their capacitive charge-storage densities [38]. Recent studies by Akazawa have suggested that, after a long annealing time (3 hours), the growth of HSG Si would saturate, and a self-limiting, highly-uniform size distribution could be obtained regardless of the annealing temperature [39, 40]. In this study, Si nanocrystals fabricated by the thermal agglomeration technique are investigated. Ultrathin a-Si layers are deposited on a thin tunnel-oxide layer and then annealed in situ using a rapid thermal annealing (RTA) setup under UHV. The a-Si deposition and the thermal agglomeration behaviors are monitored by an in-situ x-ray photoelectron spectroscopy (XPS) machine. The surface morphology and the nanocrystal structures are analyzed by atomic force microscopy (AFM), scanning electron microscope (SEM), and transmission electron microscope (TEM). A theoretical model is then established to fit the in-situ XPS results and estimate the agglomerated dot size and density.. Nonvolatile memories with hemispherical Si-nanocrystal floating gates In this chapter, Si-nc nonvolatile memory devices are fabricated using a thermal agglomeration technique. Si islands have been produced by annealing ultrathin a-Si [41-43] or silicon-on-insulator (SOI) [23, 37, 44-47] films under UHV conditions. It is suggested that the surface energy instabilities play an important role in the thermal agglomeration, or de-wetting, of the ultrathin films. A thermodynamic model based on the calculation of surface energy has been developed by Danielson et al. [48], in which the agglomeration instabilities observed in ultrathin SOI films were discussed. The general implications of their surface-energy-driven de-wetting theory are also suitable to explain the agglomeration behavior of a-Si thin films and the 6.

(25) nanocrystal formation. Although theoretical studies have provided insights of the agglomeration mechanism [42, 48], the electrical characterizations of such agglomerated Si dots are still lacking. In this study, ultrathin a-Si films are deposited using electron-beam evaporation and then annealed in situ under UHV. Hemispherical Si nanocrystals are obtained through the thermal agglomeration process. The nanocrystals are formed on a thin tunnel-oxide layer and then covered by a control-oxide layer. Memory devices including metal-oxide-semiconductor (MOS) capacitors and field effect transistors (MOSFETs) are fabricated with the embedded Si-nanocrystal floating gates. Their electrical characteristics are investigated. This thermal agglomeration method is considered compatible with the conventional top-down process because the ultrathin a-Si film can be patterned prior to the vacuum annealing. In between the ex-situ processing and the vacuum annealing, however, the a-Si surfaces need to be cleaned and kept free of native oxide in order to ensure the Si agglomeration.. 1.3 Organization of the Thesis. In chapter 1, the general background and the research motivation of the dissertation are reviewed and elucidated. In chapter 2, the experimental apparatuses are introduced. The MOCVD system used to deposit high-κ gate dielectrics is described. Meanwhile, XPS, TEM, and MEIS employed for physical analysis are discussed. The setting of electrical analysis is also included. In chapter 3, three approaches to incorporating nitrogen in CoTiO3 high-κ dielectric films, including the ion implantation of N2+, ion implantation of N+, and N2O plasma treatment, have been investigated. Nitrogen incorporation by ion 7.

(26) implantation of N2+ can improve the electrical properties in terms of gate leakage, breakdown voltage and time-to-breakdown (TBD). To reduce the impinging mass of implanted ion species, N+ ion implantation has been used. The same trends can be found as those produced using N2+. A N2O plasma treatment is also an excellent method to improve the electrical properties, exhibiting better-behaved C-V curves, lower gate leakage currents and higher breakdown voltages. In chapter 4, two silanol precursors, BDMS and TPOS, are evaluated as silicon precursors for hafnium silicate deposition with TDEAH. BDMS has one OH group, which should react with chemisorbed TDEAH. However, the other t-butyl and methyl groups can passivate the substrate surface, and stop the further absorption of TDEAH. Carbon-free hafnium silicate thin-films are deposited by MOCVD using alternative pulses of TDEAH and TPOS precursors. Hafnium silicates with high silicon contents (Hf1-xSixO2, x >0.5) are deposited at 250 °C without additional oxidants. MOS capacitors are fabricated for electrical characterizations. A forming gas anneal can improve the hafnium silicate interface quality. This low-temperature process could be promising for TFT or optoelectronic applications. In chapter 5, hemispherical Si nanocrystals are self-assembled using a thermal agglomeration technique. Ultrathin (0.9–3.5 nm) a-Si films are deposited on a 4-nm tunnel-oxide layer using electron-beam evaporation. XPS analysis has verified a layer-by-layer deposition mode for the a-Si film. After the deposition, an in-situ annealing can activate the thermal agglomeration of Si and transform the ultrathin a-Si films into Si nanocrystals. The Si agglomeration process is evaluated with variables such as annealing temperatures, surface oxide conditions, and initial Si film thickness. Also, it is demonstrated that XPS measurements can effectively provide the information of the nanocrystal agglomeration. Calculations are made based on the photoelectron attenuation theories [49], and a simple model is proposed. Comparisons 8.

(27) between the calculated results and the experimental data have shown a fairly good match. Therefore the nanocrystal features can be reasonably estimated by this model using in-situ XPS measurements. In chapter 6, the fabrication of a Si nanocrystal-embedded nonvolatile memory has been demonstrated using a thermal agglomeration technique. MOS capacitors and MOSFETs embedded with hemispherical Si nanocrystals are fabricated and characterized. A stored charge density of 4.1×1012 cm-2 (electron + hole) is obtained with a highest nanocrystal density of 3.9×1011 cm-2. Uniform FN tunneling is used to program and erase the Si nanocrystal floating-gate n-MOSFETs. A Vt window of 0.9 V is achieved under P/E voltages of ±10 V for 0.02/0.1 s. The memory device also shows good endurance and charge retention behaviors after 10000 P/E cycles. Increasing P/E voltages to ±15 V creates a large memory window (>2.7 V) with the proposed memory device. After a retention test for 100 hours, a memory window of 1 V is maintained. The retention characteristics have shown little temperature dependence with the Si nanocrystal memories, indicating that the charge-loss process is determined by the direct tunneling from nanocrystals into the oxide/Si-substrate interface states. Finally, the important experimental results of each chapter are summarized in chapter 7. Some thoughts and suggestions for future research work are also provided.. 9.

(28) Fig. 1.1 Moore’s law for microprocessors. Exponential increase of transistor counts as a function of time for generations of microprocessors has been substantiated [2].. Fig. 1.2 Estimated voltage (Vdd : input voltage / Vth : threshold voltage) and power consumption ( PLEAK : power induced by leakage current / PDYNAMIC : dynamic power consumption) trends. All parameters are taken from ITRS 2001 [4].. 10.

(29) Fig. 1.3 Gate leakage current density (Jg) versus equivalent oxide thickness (EOT) of the SiOxNy and SiO2 gate dielectrics [8]. Corresponding gate channel lengths of the data points (Lg) are marked.. 11.

(30) Chapter 2 Experimental Techniques. 2.1 Ultrahigh Vacuum in-situ Processing (ISP) System. An ultra-high vacuum (UHV) system is essential for the surface study on ultra-thin films, because surface reaction is mostly affected by gas exposure. 100 mm Si(100) wafers were used as substrates for the Hf silicate depositions and for the Si nanocrystal agglomeration experiments. Normally samples were prepared by a standard HF-last RCA clean prior to insertion into an UHV multi-chamber in-situ processing (ISP) system depicted in Figure 2.1. The UHV system consists of an entrance load-lock, an MOCVD chamber, an in-situ XPS chamber, a chamber for in-situ high vacuum rapid thermal annealing and Si e-beam evaporation, and a metal evaporator chamber. All working chambers are separated by three high vacuum tunnels and the CVD and e-beam evaporation chambers have ion-pumped buffer chambers. The vacuum of the UHV system is maintained at the level of 10-10 Torr by ion pumps. Deposition processing, post-deposition treatments, and XPS analysis can be done without any vacuum break.. 2.2 Metal Organic Chemical Vapor Deposition (MOCVD). The hafnium precursor used for this work is tetrakis (diethylamido) hafnium (TDEAH, [(C2H5)2N]4Hf ) with a chemical structure illustrated in Figure 2.2. Hf metal is bonded with four nitrogen atoms that have two ethyl radicals. No oxygen is contained in this precursor, but nitrogen in it. This nitrogen is expected to incorporate. 12.

(31) into the high-k film during CVD growth. Figure 2.3 shows the schematic structure of the MOCVD system. The TDEAH precursor dissolved in octane with the concentration of 0.1 M was introduced into the reactor with a liquid injection system (LDS-300B produced by ATMI). The liquid injection system pumped the liquid solution through a nickel frit into the vaporizer of which temperature was held at 140 °C. The precursor was pumped at a rate of 0.2 ml/min (the lowest stable flow rate in our system) and carried by 50 sccm of Ar through the vaporizer. The other gases (N2 and O2) or precursors (BDMS or TPOS) were introduced into a separate gas distribution ring. The hafnium silicates were grown by pulse-mode deposition in which each deposition cycle consists of several steps controlled by solenoid valves. Gas flows were controlled by mass flow controllers present just before the gas inlet into the CVD chamber. The Si precursors were introduced by delivering the carrier gas (N2) through a heated bubbler containing the precursor. The total deposition pressure was in the range 3-11 mTorr where gas-phase collisions were rare. The sample stage temperature was controlled with a quartz-halogen heater-thermocouple combination. The base pressure of the MOCVD chamber was around 10-9 Torr.. 2.3 Material Characterization Techniques. 2.3.1 X-ray Photoelectron Spectroscopy (XPS). X-ray photoelectron spectroscopy (XPS) was used to characterize the chemical bonding and film composition. Since the photon energy range of interest for material analysis corresponds to the x-ray energy (1-10 keV), photoelectron spectra with specific binding energies produced by x-ray radiation of a sample present. 13.

(32) chemical bonding information about given elements. Figure 2.4 shows relevant energy levels for XPS measurements [50]. Binding energies of photoelectrons can be obtained from Equation (2.1), based on Figure 2.4. Ekin = hν − Eb − Øspec,. (2.1). where Ekin is kinetic energy of the photoelectron, h is Plank’s constant, ν is the frequency of the photon, Eb is the binding energy, and Øspec is the work-function of the spectrometer. The in-situ XPS system is a PHI 5000 instrument with a non-monochromatic Mg Kα X-ray (hν = 1253.6 eV) source in the standard 54 ° geometry (X-ray source 9 ° off-normal and the electron spectrometer 45 ° off normal). The pass energy for XPS survey spectra is 117.4 eV, and that for multiplex is 46.95 eV. Films were also analyzed ex-situ by XPS depth profiling using a PHI 5500 system with a mono chromatic Al Kα X-ray (hν = 1486.6 eV) source in standard 90 ° geometry (X-ray source and electron spectrometer 45 ° off normal). Depth profiling was performed with intermittent Ar+ sputtering at 4 keV or 1 keV, 50 nA and 45 ° incidence. The peak positions were referenced to the substrate Si 2p3/2 peak at 99.3 eV or C 1s from atmospheric contamination at 284.8 eV [51, 52]. In-situ XPS was used to determine chemical bonding and compositions of the films using standard sensitivity factors of O, N, Hf for the O 1s, N 1s, and Hf 4f peaks, respectively, which were obtained from the empirical data of the spectrometer equipped with an Omni Focus III lens supplied by Perkin-Elmer.. 2.3.2 High Resolution Transmission Electron Microscopy (HRTEM). HRTEM was utilized for structural analysis. Cross-sectional bar shaped samples were taken from the wafer and glued together surface-to-surface. The sample 14.

(33) is cut and placed into a 3 mm – diameter titanium disk, and then dimpled from both sides with 3 μm diamond paste until the center of the disc is ~20 μm thick. Polishing with 1 μm diamond paste follows to get a smooth surface. The final step in sample preparation is a low-angle ion milling with a beam-energy of 6 keV for perforation. A Philips EM-430T microscope was used. The maximum electron beam energy and magnification is 300 keV, and ×650000 respectively and the corresponding point resolution is 0.228 nm. A JEOL 2100F TEM/STEM with a Schottky field emission gun was also used. This microscope is operated at 200 keV and equipped with a Gatan Tridiem energy filter for electron energy loss spectroscopy (EELS) analysis and an Oxford Instrument energy dispersive spectrometer (EDS). An annular dark-field (ADF) imaging and spatially resolved spectroscopy were performed with a scanning transmission electron microscope (STEM) probe size of approximately 0.2-0.3 nm. Figure 2.5 shows a schematic view of a STEM system equipped with EDS and EELS.. 15.

(34) Fig. 2.1 UHV processing facility for 4 inch wafer.. Fig. 2.2 Chemical bonding structure of the tetrakis diethyl-amido hafnium (TDEAH) precursor.. 16.

(35) Fig. 2.3 Schematic view of MOCVD system.. Fig. 2.4 Schematic of the relevant energy levels for XPS binding energy measurements. Ekin is kinetic energy of the photoelectron, h is Plank’s constant, ν is the photon frequency, Eb is the binding energy, Øs is the work-function of the sample, and Øspec is the work-function of the spectrometer. Note that a conducting specimen and spectrometer are in electrical contact and thus have common Fermi levels. Kinetic energies of photo-ejected electrons are given by Equation (2.1) [50]. 17.

(36) Fig. 2.5 Schematic view of the STEM system equipped with EDS and EELS.. 18.

(37) Chapter 3 Performance Improvement of CoTiO3 High-κ Dielectrics with Nitrogen Incorporation. 3.1 Introduction. The thickness of the conventional silicon dioxide (SiO2) gate dielectrics has been scaled down to around 1.5 nm to meet the high drive requirements of high-performance (CMOS) [53]. The most serious problem we face today for this ultrathin gate dielectric is the huge gate leakage due to the direct tunneling of carriers from the channel of metal oxide semiconductor field-effect transistors (MOSFET)s [54], which reduces the transconductance of devices, and increases the standby power. This is not adequate for low-power applications in portable equipment. For a long time, high dielectric constant (high-κ) gate materials such as Si3N4 [55, 56], Al2O3 [57-59], HfO2 [60-62], and ZrO2 [63-65] have been proposed to replace the conventional. ultrathin. SiO2. to. solve. this. problem.. For. the. same. equivalent-oxide-thickness (EOT), the thickness of high-κ gate dielectrics can be increased many times. Hence, the direct tunneling current can be significantly reduced. The choice of high-κ material is based on the following requirements: 1.. The κ-value should be in the range 20–50, as high as possible but low enough to avoid the fringing-induced barrier lowering effect in sub-100-nm n-MOSFETs [66].. 2.. The bandgap energy should be larger than 4.5 eV and barrier height larger than 1 eV to avoid increased leakage current at elevated temperature [67, 68]. 19.

(38) 3.. The interface state density should be less than 1011 cm−2 eV−1 to maintain a well-behaved sub-threshold characteristic.. 4.. Low trap densities are required in the film to avoid Frankel-Poole tunneling.. 5.. The dielectric should have good thermal stability during the high-temperature processing.. 6.. It should have high breakdown voltage, low-leakage, and small hysteresis.. In previous work, a new high-κ dielectric CoTiO3 has been proposed for application in MOSFETs and dynamic random access memories (DRAMs) [38]. The dielectric constant for this CoTiO3 with the bottom oxide layer can be as high as 50, which makes this high-κ dielectric become very promising after the current medium κ value (15–25) materials, such as HfO2 and ZrO2, have reached their useful limit. However, some issues still remain when high-κ materials are used. The most important issues are: 1.. The interfacial layer of SiO2 or silicate remaining after deposition of high-κ materials.. 2.. The high fixed charge in the bulk of high-κ dielectrics which results in flat-band voltage (VFB) shifts.. 3.. The degradation of mobility.. 4.. A low crystallization temperature.. 5.. Boron penetration for p-MOSFETs.. According to recent reports [11-25], optimized treatments which incorporate nitrogen have resulted in a significant improvement in the high-κ dielectric properties. Nitridation of the silicon surface can reduce the growth of an interfacial layer. Plasma nitridation after deposition of the high-κ dielectric can recover the degraded mobility. 20.

(39) The advantages of nitrogen incorporation are the increase of the κ-value, the increase of the temperature of crystallization, the reduction of the leakage, reasonable VFB, and reduced boron penetration [11-24]. The material and electrical properties of CoTiO3 high-κ dielectrics have been investigated in earlier reports [26, 27]. In present work, nitrogen incorporation using N2+/N+ ion implantation or N2O plasma treatment to improve this CoTiO3 films are investigated. It is found that the nitrogen incorporation using either ion implantation or plasma treatment can significantly improve the electrical performance of CoTiO3 high-κ dielectrics.. 3.2 Experimental. Capacitors were fabricated on n-type 150 mm Si(100) wafers with a resistivity of 2-7 Ω-cm. After the growth of a 550 nm thick field oxide, the active region of capacitors were defined and etched by buffered oxide etch (BOE, NH4F: HF = 6:1). Wafers underwent a standard RCA cleaning process and were put into the low-pressure chemical vapor deposition (LPCVD) tube in a pure NH3 ambient to grow an ultra-thin nitride ~1.0 nm thick on the Si-surface. The thickness of the nitride was measured by Ellipsometry. The purpose of this NH3-grown ultrathin nitride film is to prevent the reaction of the following sputtered Ti and then Co (Co/Ti) metal films, and also to retard the oxidation of silicon during the oxidation of Co/Ti layer. The Co (5 nm) and Ti (5 nm) films were deposited by sputtering at a power of 500 W and a sputtering rate of 0.9 nm/sec. Then wafers underwent the N2+ or N+ ion implantation. To avoid the nitrogen penetration through the metal films and to reduce damage of the metal films, low ion energy of 10 keV was used with nitrogen doses of 2×1014 and 2×1015 atom/cm2. Wafers were then oxidized in a furnace using flows of 5000 sccm each of O2 and N2. Splits were done for oxidation temperatures of 800, 21.

(40) 850 and 900 °C, and the oxidation time was 10 min. Some wafers without nitrogen implantation underwent N2O plasma treatment in a plasma enhanced chemical vapor deposition (PECVD) system. The flow rate of N2O was 60 sccm, the temperature was 350 °C, the power was set at 10, 15, or 20 W, and the processing time was 5 minutes. The purpose of this N2O plasma treatment is to passivate the oxygen vacancies in the bulk film, and also to incorporate nitrogen in the dielectrics. Then the plasma-treated samples (and the untreated control sample as well) went through an additional rapid thermal annealing (RTA) at 880 °C for 40 seconds in N2 ambient. This RTA step was aimed to repair any plasma-induced damages in the CoTiO3 dielectrics. The top electrode for electrical measurements was a 500 nm Al film which was deposited by physical vapor deposition (PVD). The capacitance-voltage (C-V) curves of the capacitors were measured with an HP 4284A impedance meter at 100 kHz. The areas of the capacitors were 2.5×10-5 cm2 (50 × 50 μm) and 1×10-4 cm2 (100 × 100 μm). The current-voltage (I-V) curves were measured using an HP 4156A semiconductor parameter analyzer. The physical properties of CoTiO3 high-κ dielectrics with and without nitrogen incorporation were analyzed by transmission electron microscopy (TEM), secondary-ion mass spectrometry (SIMS), and x-ray diffraction (XRD).. 3.3 Results and Discussion. A. N2+ Ion Implantation The thickness of all CoTiO3 samples was first measured by TEM. Figures 3.1(a) and (b) show one set of the TEM pictures for samples of CoTiO3 oxidized at 800 °C for 10 min without and with nitrogen ion implantation, respectively. The physical thickness of both samples was in the range 24–25 nm. It was observed that 22.

(41) the oxidation of the Co/Ti films increases the thickness of the interfacial layer. This indicates that the ultrathin nitride film was not thick enough to retard the diffusion of oxygen. Compared with the sample without nitrogen implantation, smaller grains and a less diffuse boundary profile between high-κ and interfacial layers were found for the N2+-implanted sample. C-V curves at a high frequency of 100 kHz are shown in Fig. 3.2. The C-V curve of the sample oxidized at 800 °C for 10 min without nitrogen implantation was not obtained due to a large leakage current during measurement. This may be due to the non-fully oxidized Co/Ti in the bulk of dielectrics at lower temperature for a short oxidation time of 10 min. It is found that the capacitance Cox in the accumulation region decreases with the increasing oxidation temperature, which is due to the abundant oxygen incorporation during the oxidation step. The extracted equivalent-oxide-thickness (EOT), interfacial silicate thickness, high-κ dielectric thickness, total thickness, effective κ-value and flat-band voltage are summarized in Table 3.1. The existence of interfacial layers degrades the effective κ-value. However, the intrinsic bulk dielectric constant for CoTiO3 has been estimated using the same processes [38]. The intrinsic bulk dielectric constant was estimated as high as 50 [38], excluding the interfacial layer. It is found that the EOT increases as the oxidation temperature increased. As a result, the effective κ-value deduced from the C-V results and TEM measurements decreases as the temperature is increased. The flat-band voltage shifts to a negative value for the sample oxidized at 900 °C with nitrogen implantation. This may be due to nitrogen diffusion into the interfacial layer which creates positive charges in the film. Figure 3.3 shows the electrical properties of samples oxidized at 900 °C for 10 min. Figure 3.3(a) shows that capacitors with nitrogen ion implantation exhibit a lower leakage current and a higher breakdown voltage. This phenomenon is the same for samples oxidized at 800 and 850 °C. Figure 3.3(b) shows the Weibull distribution 23.

(42) of gate leakage currents at Vg = 1 V. Capacitors with nitrogen implantation have a tighter distribution and smaller leakage currents than those without. Figure 3.3(c) shows the Weibull distribution of breakdown voltages. Once again, the capacitors with nitrogen implantation have higher breakdown voltages. The samples with and without nitrogen implantation are also subjected to a constant-voltage (Vg = 2V) stress, and the results are shown in Figures 3.4(a) and (b). For the capacitors without nitrogen implantation, a significant increase of gate leakage was found after stressed for 100 s, as shown in Fig. 3.4(a). On the other hand, the samples with nitrogen implantation exhibited no significant increase in gate leakage currents, as shown in Fig. 3.4(b), when compared to those without nitrogen implantation. Figure 3.5 shows the x-ray diffraction spectra for a CoTiO3 film oxidized at 850 °C with and without nitrogen implantation. For the sample without nitrogen implantation, a clear peak intensity was found around 34° for the CoTiO3 (311) phase. However, the peak is not so clear for the sample with nitrogen implantation. This implies that the nitrogen implantation of the Co/Ti films can retard the crystallization of CoTiO3.. B. N+ Ion Implantation To reduce the possible damages caused by the nitrogen ion implantation, two approaches can be adopted. The first approach is to reduce the mass of implanted species by using N+ ions instead of N2+. Figure 3.6(a) shows the result. The oxidation temperature was 850 °C with a reduced oxidation time of 5 min. This can reduce the oxygen encroachment during the high temperature oxidation. The leakage current decreased as the nitrogen dose increased. The Weibull distributions of gate leakage currents and breakdown voltages are shown in Figures 3.6(b) and (c), respectively. It 24.

(43) can be seen that high nitrogen doses improve the electrical properties of the capacitors.. C. N2O Plasma Treatment The second approach to avoid the damage from ion implantation is generally to use the N2O plasma treatments [69, 70] or post-deposition annealing (PDA) in nitrogen-related ambient, such as N2, NO, N2O , or NH3 [71, 72]. In present study, the N2O plasma treatment (at powers of 10, 15, and 20 W) was applied after the oxidation step. Some samples without nitrogen ion implantation underwent the N2O plasma treatment before the gate-metal deposition. This treatment can passivate the oxygen vacancies (by oxygen radicals in N2O plasma) in the dielectric bulk and also introduce nitrogen (radicals of nitrogen in the N2O plasma) into the bulk. Figures 3.7 shows SIMS profiles for a sample treated with N2O plasma (20 W). It is found that nitrogen atoms pile up at the high-κ/Si interface after the N2O plasma treatment. This profile is different from the report using N2 plasma in which the nitrogen has diffused uniformly into the bulk after annealing at 700 °C [70]. However, this result is similar to the resultant nitrogen profile in ultrathin gate oxide (or oxy-nitride) formed by N2O oxidation or annealing [73]. Another advantage using N2O plasma instead of N2 plasma is the oxygen radicals introduced into the bulk of the high-κ film. The oxygen profiles for all samples are measured and shown in Fig. 3.8. It is clear that samples with N2O plasma treatments exhibit higher oxygen concentrations compared to the one without. From the previous report [22], leakage currents of nitrogen-incorporated high-κ dielectrics can be significantly reduced by 3–4 orders of magnitude. Recently, it has been widely accepted that the reason for leakage current reduction by nitrogen incorporation is that nitrogen anneals oxygen vacancies [71, 72]. 25.