856 IEEE ELECTRON DEVICE LETTERS, VOL. 28, NO. 10, OCTOBER 2007
Investigation of Impact Ionization in InAs-Channel
HEMT for High-Speed and Low-Power Applications
Chia-Yuan Chang, Heng-Tung Hsu, Senior Member, IEEE, Edward Yi Chang, Senior Member, IEEE,
Chien-I Kuo, Suman Datta, Senior Member, IEEE, Marko Radosavljevic,
Yasuyuki Miyamoto, Member, IEEE, and Guo-Wei Huang, Member, IEEE
Abstract—An 80-nm InP high electron mobility transistor
(HEMT) with InAs channel and InGaAs subchannels has been fabricated. The high current gain cutoff frequency (ft) of
310 GHz and the maximum oscillation frequency (fmax) of
330 GHz were obtained at VDS = 0.7 V due to the high
elec-tron mobility in the InAs channel. Performance degradation was observed on the cutoff frequency (ft) and the corresponding
gate delay time caused by impact ionization due to a low energy bandgap in the InAs channel. DC and RF characterizations on the device have been performed to determine the proper bias conditions in avoidance of performance degradations due to the impact ionization. With the design of InGaAs/InAs/InGaAs com-posite channel, the impact ionization was not observed until the drain bias reached 0.7 V, and at this bias, the device demonstrated very low gate delay time of 0.63 ps. The high performance of the InAs/InGaAs HEMTs demonstrated in this letter shows great potential for high-speed and very low-power logic applications.
Index Terms—Gate delay time, high electron mobility
transis-tors (HEMTs), impact ionization, InAs-channel.
I. INTRODUCTION
W
ITH THE ultimate limit for the scaling of Si devices for device-performance improvement being approached, planar III–V compound semiconductor field effect transistors (FETs) have been identified as one of the most attractive devices for nanoelectronic applications. The excellent RF performance has been demonstrated by InAlAs/InGaAs high electron mobil-ity transistors (HEMTs) on InP substrate [1]. Generally, higher electron mobility and velocity can be realized by the increase of the indium content in the InGaAs channel, which makes InAs-channel heterostructure FETs (HFETs) well suitable for low-power and high-speed logic applications due to the extremely high electron mobility of more than 30 000 cm2/V· s [2], [3].Manuscript received June 19, 2007. This work was supported in part by the National Science Council under Contract NSC 96-2752-E-009-001-PAE, by the Ministry of Economic Affairs, Taiwan, R.O.C., under Contract 95-EC-17-A-05-S1-020, and by the “Nanotechnology Support Project” of the Ministry of Education, Culture, Sports, Science, and Technology (MEXT), Japan. The review of this letter was arranged by Editor G. Meneghesso.
C.-Y. Chang, E. Y. Chang, and C.-I Kuo are with the Department of Materials Science and Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C. (e-mail: edc@mail.nctu.edu.tw).
H.-T. Hsu is with the Department of Communications Engineering, Yuan Ze University, Chung Li 320, Taiwan, R.O.C.
S. Datta and M. Radosavljevic are with the Components Research, Technol-ogy and Manufacturing Group, Intel Corporation, Hillsboro, OR 97124 USA.
Y. Miyamoto is with the Department of Physical Electronics, Tokyo Institute of Technology, O-okayama, Meguro-ku, Tokyo 152-8552, Japan.
G.-W. Huang is with the National Nano Device Laboratories, Hsinchu 30078, Taiwan, R.O.C.
Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LED.2007.906083
However, high indium-content devices usually suffer from serious kink effect, low breakdown voltage, and high output transconductance caused by the electron–hole pair generation created by impact ionization. This phenomenon is even more remarkable for InAs/AlSb structures because of the lack of hole confinement due to type II alignment [2]. In general, the output conductance limits the achievable gain and the breakdown voltage and has a direct impact on the power performance of such devices [4], [5].
In this letter, the impact-ionization behavior in the RF and digital performances of the InAs HEMT with In0.53Ga0.47As/
InAs/In0.53Ga0.47As composite channel structure was
investi-gated. Owing to the In0.53Ga0.47As subchannels with a higher
energy bandgap, the InAs/In0.53Ga0.47As heterostructure
ob-tains a lower gate leakage current and a higher breakdown voltage. The effect of impact ionization on the device perfor-mance will also be discussed, with the optimum bias conditions determined through complete dc and RF characterizations.
II. DEVICEFABRICATION
The HEMT structure was grown on 2” semi-insulating InP substrate by molecular beam epitaxy. The structure from bottom to top consisted of a 600-nm-thick In0.52Al0.48As
buffer layer, a 3-nm-thick In0.53Ga0.47As lower subchannel,
a 5-nm-thick InAs channel layer, a 3-nm-thick In0.53Ga0.47As
upper subchannel, a 3-nm-thick In0.52Al0.48As spacer layer, a
Si δ-doped (sheet density of 4× 1012cm−2) layer, a 5-nm-thick In0.52Al0.48As barrier, a 5-nm-thick InP etching stop layer, and
a 40-nm-thick Si-doped In0.53Ga0.47As cap (2× 1019cm−3).
The InP etching stop layer was used to improve the selectivity of wet chemical recess etch and provide semiconductor surface passivation on each side of the gate to reduce the trapping effect on the InAlAs surface [6]. With the use of the InP etching stop layer, the lateral recess length was easy to control, and the RF performance was improved [7].
The mesa isolation was done by wet chemical etch. Source and drain ohmic metals were formed with 240-nm-thick Au/Ge/ Ni/Au and alloyed by rapid thermal annealing at 250 ◦C for 30 s. As a result of the highly Si-doped cap, a low ohmic contact resistance (Rc) of 0.025 Ω· mm and a sheet resistance
(Rsh) of 35.3 Ω/ were obtained by using the transmission line
model method. The T-shaped gate lithography was carried out in 50-keV JEOL electron beam lithography system (E-beam). The gate recess was performed by wet chemical etching us-ing succinic acid-based solution. The Ti/Pt/Au gate metal was formed by evaporation and lift off. The gate length of 80 nm was estimated by scanning electron microscopy. De-vices were passivated using a 100-nm-thick plasma-enhanced
CHANG et al.: INVESTIGATION OF IMPACT IONIZATION IN InAs-CHANNEL HEMT 857
Fig. 1. Output characteristics of a 0.08 µm× 100 µm InAs/InGaAs HEMT. (a) Drain current IDas a function of drain bias VDwith different gate voltage VG from 0 to−0.8 V. (b) Normalized output conductance goas a function of VD.
Fig. 2. (a) DC transconductance gmof a 0.08 µm× 100 µm device as a function of VGwith different drain voltage VD. (b) Plot of|S21| measured at 10, 30,
and 60 GHz and gmversus drain–source voltage of 0.08 µm× 100 µm.
chemical-vapor-deposition silicon nitride film. Finally, the air-bridges were formed with 2 µm of plated Au.
III. RESULTS ANDDISCUSSION
Fig. 1(a) shows the current–voltage (I–V ) characteristics of the 80-nm gate HEMT device with a 2× 50 µm gate width. As observed from the figure, this device can be well pinched off with a threshold voltage of−0.7 V and demonstrates a high breakdown voltage with a low gate leakage current. Addition-ally, a relatively high drain–current density of 700 mA/mm was observed at a low VDS of 0.5 V, primarily due to the superior
electron transport properties in the InAs channel. It is noted from the I–V curve that the drain current tends to increase at a constant slope for VDS> 0.7 V. This is mainly due to
the existence of impact ionization as evidenced by the hump occurred in the vicinity of VDS= 0.7 V that was observed in
the output conductance measurement, as shown in Fig. 1(b). Fig. 2(a) shows the dc transconductance (gm) as a function
of gate voltage (VG) at different VDS from 0.3 to 1.1 V. The
device exhibits high gm values, with a peak of 1600 mS/mm
at VDS= 0.5 V and 2630 mS/mm at VDS= 1.1 V. The drastic
increase in peak gmvalues for VDS> 0.7 V is mainly due to the
additional electron–hole pairs generated by impact ionization in the channel. Electrons merely flow in the channel, which adds to the channel current, and increase the transconductance. However, if the resulting holes are unconfined by band lineup, the holes will leave the channel and flow into the negatively bias Schottky gate either to cause an increase in the gate
leakage current or to accumulate below the gate (or channel) area, contributing to a higher gate-to-source capacitance. A record-high ON-state breakdown voltage (BVDS, defined at
1-mA/mm gate current) of 1.75 V was measured at VG= −0.8 V, indicating a good hole confinement achieved by such a
channel structure [4], [5], [8].
To investigate the effect of impact ionization on the RF performance, the S-parameter of the 2× 50 µm device was measured using Cascade Microtech on-wafer probing system with a vector network analyzer from 1 to 110 GHz. A standard load–reflection–reflection–match calibration method was used to calibrate the measurement system. Fig. 2(b) shows the mea-sured|S21| (in decibels) at various frequencies as functions of
drain voltage. DC transconductance gm, as a function of drain
voltage, is also included in the figure. It is clear that, despite the monotonic increasing trend of gm with the drain voltage, |S21| tends to saturate at a constant level for drain biases
higher than 0.7 V. The primary reason was that the impact ionization occurred at drain biases higher than 0.7 V and the generated electrons cannot catch up with the field modulation at RF frequencies. The gate current plotted as a function of gate voltage, as shown in Fig. 3(a), further manifests the impact-ionization phenomenon occurred when VDS was higher than
0.7 V. It also shows better gate leakage performance as com-pared to the Sb-based InAs-HFETs [8], [9]. To further investi-gate such phenomenon, the pad parasitic effects were carefully deembedded through the S-parameter measurements, and the intrinsic device parameters were extracted and listed in Table I. The extracted RF gm values at different bias levels are also
858 IEEE ELECTRON DEVICE LETTERS, VOL. 28, NO. 10, OCTOBER 2007
Fig. 3. (a) Gate current IGplotted as a function of VGat different VDfrom 0 to 1 V, 0.1 V per step. (b) Typical current gain|h21|, MAG/MSG, and Ugas a
function of frequency of a 0.08 µm× 100 µm InAs/InGaAs HEMT. The VDSis 0.7 V, and the VGis−0.4 V. TABLE I
EXTRACTEDINTRINSICPARAMETERS OF A0.08 µm× 100 µm InAs/InGaAs HEMT WITHDIFFERENTDRAIN–SOURCE
VOLTAGEVDSFROM0.5TO0.9 V
listed in the table. It can be observed that the drastic increase in CGS at higher drain bias levels, together with the decrease
in RF gm caused by impact ionization, severely degrades the
cutoff frequency ft, resulting in the peaked ftvalue of 310 GHz
at VDS= 0.7 V.
Complete dc and RF analysis for the investigation of the effect of impact ionization on the device reveal that the de-vice should be biased at VDS= 0.7 V for optimum
perfor-mance. Current gain (|h21|2), Mason’s unilateral gain (Ug),
and MAG/MSG as a function of frequency are plotted in Fig. 3(b). The intrinsic fT and fmaxobtained for the 2× 50 µm
device are 310 and 330 GHz at VDS= 0.7 V, exhibiting better
performance than other InAs-channel devices with InAlAs or Sb-based barrier [8], [10] and comparable to the performance of InGaAs-channel HEMTs with high In concentration [1], [11], [12]. To characterize such device for high-speed logic applica-tions, the gate delay time (CV /I), according to the definition in [13], was calculated to be 0.63 ps at the optimum bias VDS=
0.5 V. This excellent intrinsic device speed of the InAs/InGaAs HEMT shows great potential for logic applications com-pared to the state-of-the-art planar and nonplanar Si logic transistors.
IV. CONCLUSION
In this letter, a high-performance InAs/InGaAs HEMT was demonstrated. High ON-state breakdown voltage BVDS of
1.75 V and very low gate leakage current were obtained by using In0.52Al0.48As barrier layer and In0.53Ga0.47As/InAs/
In0.53Ga0.47As composite channel structure. The effect of
im-pact ionization on the device performance has been investigated through complete dc and RF characterizations which determine the optimum drain bias voltage of 0.7 V. High current gain cutoff frequency (ft) of 310 GHz and maximum oscillation
frequency (fmax) of 330 GHz with a very low gate delay time
of 0.63 ps were achieved at the optimum drain voltage of 0.7 V. With the high gain and high speed at low drain voltage, such devices show tremendous potential in future high-speed and low-power logic applications.
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