Abstract—The impact of MOSFET layout-dependent stress on high-frequency performance and flicker noise has been investi-gated. The proposed donut MOSFETs demonstrate the advan-tages over the standard multifinger MOSFETs, such as the lower flicker noise SID/I2
DSin the low-frequency domain and the higher cutoff frequency fT in the very high-frequency region. The elim-ination of the transverse stress σ⊥from shallow trench isolation (STI) and the suppression of interface traps along the STI edge are proposed as the primary factors responsible for the enhancement of the effective mobility μeff, as well as fT, and the reduction of flicker noise. The significantly lower flicker noise realized by donut devices suggests the reduction of STI-generated traps and the suppression of mobility fluctuation due to eliminated transverse stress. The former is applied to n-channel MOS in which the flicker noise is determined by the number-fluctuation model. The latter is responsible for p-channel MOS whose flicker noise is dominated by the mobility-fluctuation model.
Index Terms—Cutoff frequency, donut, flicker noise, longitu-dinal stress, mobility, shallow trench isolation (STI), transverse stress.
I. INTRODUCTION
W
ITH THE advancement of CMOS technology to the nanoscale regime, the stress introduced from the materi-als and the process becomes more sensitive to the device layout and topography. The shallow trench isolation (STI) process will induce compressive stress and traps, which may have impact on flicker noise (i.e., 1/f noise) in both nMOS and pMOS devices [1]–[4]. Fantini and Ferrari investigated the influence of com-pressive stress from STI on low field mobility and the impact on 1/f noise for nMOS and pMOS [3]. This paper is restricted to wide-channel devices in which the longitudinal stress σ//can bemodulated by varying the distance of the STI edge to the poly-gate edge, i.e., SA, but the effect of transverse stress σ⊥remains unknown. Their experimental results indicate that the electron mobility is degraded, whereas the hole mobility is enhanced
Manuscript received April 19, 2011; revised May 22, 2011; accepted June 2, 2011. Date of publication July 12, 2011; date of current version August 24, 2011. This work was supported in part by the National Science Council under Grant NSC98-2221-E009-166-MY3. The review of this paper was arranged by Editor Z. Celik-Butler.
K.-L. Yeh is with the Institute of Electronics Engineering, National Chiao-Tung University, Hsinchu 300, Taiwan, and also with Silicon Motion Technology Corporation, Hsinchu 300, Taiwan.
J.-C. Guo is with the Institute of Electronics Engineering, National Chiao-Tung University, Hsinchu 300, Taiwan (e-mail: jcguo@mail.nctu. edu.tw).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2011.2159223
under increasing compressive σ// by shrinking SA [3]. The
increase in compressive σ// can benefit pMOS with higher
hole mobility but leads to the penalty of increasing 1/f noise. Wang et al. reported the STI-edge effect on the random-telegraph-signal noise and proposed ring transistors as the structure, trying to eliminate the STI-edge effect [4]. Their study is limited to nMOS, and the ring transistors demonstrate a lower noise factor than the standard one when scaling the channel width below 1.5 μm. In contrast with the work by Fantini et al., this paper limits the focus on the effect of σ⊥, which is varied by channel widths, and assumes a σ//constant
under fixed SA. Both of them adopted a single-finger MOSFET with fixed SA as the standard device and left the impact of STI stress on high-frequency performance as an open question.
Recently, layout-dependent STI stress and its impact on high-frequency characteristics, as well as flicker noise, have been investigated but limited to the nMOS [5], [6]. A minor layout modification, i.e., edge extension, was implemented to reduce the stress and traps introduced by STI [5]. However, the edge-extended layout cannot prevent from the gate-to-STI-edge overlap region and leaves the STI stress an impact factor. Again, a ring transistor was proposed, trying to solve the mentioned problem and identify the influence of the transverse stress σ⊥ on flicker noise [4], [6]. However, the impact on high-frequency performance is not understood. Furthermore, both studies of edge-extended and ring-transistor layouts did not cover pMOS, which is even more important than nMOS for low-phase-noise design in RF and analog applications.
In this paper, a new MOSFET layout, i.e., the donut layout, is proposed to create the devices free from the STI transverse stress σ⊥ along the width direction to explore the impact on transconductance Gm, the effective mobility μeff, the cutoff
frequency fT, and flicker noise. Meanwhile, an extensive
in-vestigation is performed on both nMOS and pMOS to explore the STI-stress effect on the channel current IDS, fT, and flicker
noise. For each device structure under a specified bias, the flicker noise is averaged from multiple dies to represent the statistics of die-to-die variation. This paper is aimed to identify the impact from STI stress on high-frequency characteristics as well as flicker noise, and the results can guide MOSFET layout optimization for RF and analog circuit design.
II. DEVICEFABRICATION ANDCHARACTERIZATION
In this paper, the devices were fabricated in a 90-nm low-leakage CMOS process, with the drawn gate length Ldrawnof
Fig. 1. Brief layout of donut MOSFET (a) D1S1, SA = 0.3 μm and (b) D10S10, SA = 3 μm with two major layers, such as active region (OD) and poly gate (PO).
80 nm and the gate-oxide thickness Toxof 2.2 nm. Note that the
electrical equivalent thickness under strong inversion Tox(inv)is
3 nm, corresponding to a 2.2-nm Toxand CoSi2/poly-Si gate.
In order to investigate the stress and interface traps generated near the STI edge, two types of MOSFET layouts, i.e., stan-dard and donut, are designed and implemented. The total gate width Wtot is fixed at 64 μm: 2 μm× 32 for the multifinger
MOSFET and 16 μm× 4 for the donut MOSFET. Note that the multifinger MOSFET denoted as W2N32 represents the standard device. As shown in Fig. 1, the donut MOSFETs are constructed as four-side polygons in which the corners contribute very little to the channel current [4], [7]. Two layout dimensions, which are denoted as D1S1 and D10S10, were implemented. In Fig. 1(a), D1S1 represents a donut MOSFET in which the space from the poly-gate edge to the STI edge, which is defined as SA, follows the minimum rule, i.e., SA = 0.3 μm, to maximize the compressive stress from STI and along the channel (i.e., the longitudinal stress σ//). Meanwhile,
D10S10 shown in Fig. 1(b) denotes the donut MOSFET with ten times larger space between the poly-gate edge and the STI edge, i.e., SA = 3 μm, intentionally to relax σ//from STI.
Scattering parameters were measured by an Agilent E8364B network analyzer for high-frequency characterization and the extraction of gate capacitances and cut-off frequency. Open-and-short deembedding was performed to remove the parasitic capacitances from the pads, as well as interconnection lines, and the resistances from all of the metal interconnects. The power spectral density of drain-current noise SIDwas measured
by low-frequency-noise (LFN) measurement system, consisting of Agilent dynamic signal analyzer (DSA 35670) and low-noise amplifier (LNA SR570). The LFN measurement generally cov-ers a wide frequency range from 4 Hz to 10 kHz. The LFN was measured under various gate overdrive |VGT| = 0.1 ∼ 0.7 V
and fixed|VDS| = 50 mV for both nMOS and pMOS.
III. RESULTS ANDDISCUSSION
At first, STI stress introduced in MOSFETs with three dif-ferent layouts as mentioned (standard W2N32, donut D1S1, and D10S10) is illustrated in Fig. 2 to assist an analysis and an understanding of the layout effect on STI stress and, then, the electrical characteristics. Note that STI stress is classified as longitudinal stress, which is denoted as σ//, which is in
parallel with the channel, and transverse stress, i.e., σ⊥, which is transverse to the channel. We can see that standard MOSFETs [see Fig. 2(a)] are subject to σ// along the channel length and
Fig. 2. Schematics of STI stress in MOSFETs with three different layouts (a) standard multi-finger device W2N32 (b) donut device D1S1 (c) donut device D10S10. Longitudinal stress : σ//in parallel with the channel, transverse stress: σ⊥transverse to the channel.
TABLE I
STRESSFAVORABLE FORMOBILITYENHANCEMENT INNMOSAND PMOS ALONGLONGITUDINAL ANDTRANSVERSEDIRECTIONS[8]
Fig. 3. Threshold voltage VTmeasured for standard and donut devices under linear and saturation bias conditions (a) NMOS (b) PMOS. Standard : multi-finger W2N32. Donut : D1S1 and D10S10.
σ⊥along the gate width. On the other hand, donut MOSFETs are free from σ⊥. Regarding the stress favorable for mobility enhancement, it has critical dependence on the device types and orientations, as shown in Table I [8]. For nMOS, tensile stress, i.e., either σ// or σ⊥, can improve μeff. As for pMOS,
compressive stress in σ//or tensile stress in σ⊥is the right one
for μeffenhancement.
A. Layout Effects on Threshold VoltageVT: Standard and
Donut MOSFETs
Fig. 3(a) and (b) presents the threshold voltage VT measured
in linear and saturation regions for nMOS and pMOS with standard multifinger and donut layouts (D1S1 and D10S10), re-spectively. As shown in Fig. 3(a), the standard nMOS (W2N32) indicates a smaller VT value, which is 10–15 mV lower than
that of D1S1 and nearly the same as that of D10S10. A similar layout effect on VT is demonstrated for pMOS, as shown in
Fig. 3(b), where the VT lowering from D1S1 to W2N32 is
around 18–20 mV for both linear and saturation regions. The results suggest that VT rolls off due to the narrow-width effect,
i.e., the inverse narrow-width effect, which is a minor effect for W2N32 compared with donut devices. In this paper, the gate
Fig. 4. Drain current IDS and transconductance Gm in linear region for
standard NMOS W2N32 and donut NMOS D1S1, D10S10 (a) IDSversus VGT
(b) Gmversus VGT. VGT= VGS− VT, VDS= 0.05 V.
Fig. 5. Maximum transconductance Gm_maxmeasured from standard and
donut NMOS in (a) linear region VDS= 0.05 V and (b) saturation regions
VDS= 1.2 V. Standard : multi-finger W2N32. Donut : D1S1 and D10S10.
overdrive VGT= VGS− VT is used to replace the gate bias
VGSto offset the VT variation from different layouts.
B. Layout Dependence ofIDS,Gm, andμeff: Standard and
Donut nMOS
Fig. 4(a) and (b) presents the channel current IDS and
transconductance Gm measured from nMOS under various
VGTin the linear region (VDS= 50 mV). As shown in Fig. 4(a),
the donut nMOS D10S10 can offer the highest IDS, but D1S1
suffers the lowest one, as compared with the standard nMOS (W2N32). Gmshown in Fig. 4(b) just follows the same trend
of layout dependence as that of IDS, i.e., D10S10 gains the
highest Gmbut D1S1 suffers the worst one. Fig. 5(a) and (b)
makes a comparison of maximum Gm(Gm,max) between three
different layouts, i.e., standard (W2N32), D1S1, and D10S10 for nMOS in linear and saturation regions (VDS= 50 mV
and 1.2 V). The results indicate that Gm, max of D10S10 is
enhanced by 7.5% but that of D1S1 is degraded by around 9.7%, as compared with the standard nMOS (W2N32). The experimental result suggests that compressive σ// from STI,
which is maximized in D1S1 due to the minimum SA, is the primary factor responsible for Gm,max degradation. As for
D10S10, the much lower σ// due to ten times larger SA and
eliminated σ⊥from the donut layout contributes to the Gm,max
improvement.
The influence on μeff shown in Fig. 6 reveals exactly the
same trend as that of Gm,max. The donut nMOS D10S10
gains an enhancement of 7.45%, whereas D1S1 suffers 9.2% degradation in μeff, i.e., compared with the standard nMOS.
The results justify the mechanism that the layout dependence of Gm,max is originated from the effect of STI stress σ// and
σ⊥on electron mobility summarized in Table I.
Fig. 6. Effective mobility μeff extracted from linear I–V for standard and
donut NMOS. Standard : multi-finger W2N32. Donut : D1S1 and D10S10.
Fig. 7. Drain current IDS and transconductance Gm in linear region for
standard PMOS W2N32 and donut PMOS D1S1, D10S10 (a) IDS versus
|VGT| (b) Gmversus|VGT|. VGT= VGS− VT, VDS=−0.05 V.
Fig. 8. Maximum transconductance Gm_maxmeasured from standard and
donut PMOS in (a) linear region VDS=−0.05 V and (b) saturation regions
VDS=−1.2 V. Standard : multi-finger W2N32. Donut : D1S1 and D10S10.
C. Layout Dependence ofIDS,Gm, andμeff: Standard and
Donut pMOS
As for pMOS with the mentioned three layouts (W2N32, D1S1, and D10S10), the measured IDS and Gm shown in
Fig. 7(a) and (b) indicate the best performance in donut pMOS D1S1, whereas the worst one in standard pMOS (W2N32). The results from pMOS are very different from those demonstrated for nMOS. Again, Fig. 8 presents a comparison of Gm,max
between three different layouts for pMOS. We can see that the donut pMOS D1S1 and D10S10 demonstrate 12.2% and 7.6% higher Gm,max in the linear region than that of standard
pMOS (W2N32). The effective mobility μeff extracted from
linear I−V , as shown in Fig. 9, just reveal the same trend of layout dependence as that of Gm,max. The donut pMOS D1S1
and D10S10 present a μeff enhancement of 12.5% and 6.3%,
respectively, compared with the standard pMOS. According to Table I, it can be explained that D1S1 with the minimum SA, resulting the highest compressive σ// and minimized σ⊥, can
benefit the most in hole mobility. The standard pMOS (W2N32) with relieved σ//in the multifinger structure and the largest σ⊥
Fig. 9. Effective mobility μeff extracted from linear I–V for standard and
donut PMOS. Standard : multi-finger W2N32. Donut : D1S1 and D10S10.
The significant difference of μeff revealed in the donut
MOSFETs with various SA, such as SA = 3 μm for D10S10 and SA = 0.3 μm for D1S1, can be used to extract the av-erage σ//. Regarding the extraction of average σ⊥,
single-finger MOSFETs with various channel widths and different gate orientations such as x and y are required to make a one-to-one comparison with the donut MOSFETs, which can eliminate σ⊥ and act as the reference device. In this paper, single-finger MOSFETs are not available, and the extraction of
σ⊥ is considered as an interesting topic for future work. The method of stress extraction can be referred to our previous work [9] and applied to the donut MOSFETs as follows:
Δμ
μ0
=−(k⊥σ⊥± k//σ//) (1)
where
μ0 mobility of the reference device, free from σ//and σ⊥;
Δμ mobility variation due to STI stress, σ//and σ⊥;
k// first order of coefficient for mobility variation from σ//+
for nMOS and−for pMOS;
k⊥ first order of coefficient for mobility variation from σ⊥. For donut MOSFETs, σ⊥is negligibly small, and (1) can be reduced to
Δμ
μ0
∼
=−(±k//σ//). (2)
Assume that both σ// and σ⊥ are negligibly small in donut
D10S10 and the μeff extracted from D10S10 is defined as μ0.
Then, component k//σ// can be extracted from the mobility
variation Δμ compared with the μ0of the reference (D10S10),
which is given by (2), and σ//is determined by (3) as a function
of the ratio between SAref of the reference and the SA of the
specified device as follows:
σ//= k· log SAref SA . (3) From (2) and (3) Δμ μ0 ∼ =− ±k//k· log SAref SA (4) Δμ = μeff(SA)− μ0 (5)
μ0= μeff(SAref). (6)
Fig. 10. Measured and calculated fT versus VGS (|VDS| = 1.2 V) for
standard and donut MOSFETs (a) NMOS (b) PMOS. Standard : multi-finger W2N32. Donut : D1S1 and D10S10.
Factor k//k can be extracted from (4)–(6), with SAref=
3 μm for D10S10 and SA = 0.3 μm for D1S1. Hereafter, the mobility variation from σ// for donut MOSFETs with various
SA ( SAref) values can be predicted by (4).
D. High-Frequency Performance of Donut and Standard MOSFETs
The impact of layout-dependent STI stress on high-frequency performance is of special concern, and the cutoff frequency
fT is recognized as the key performance parameter for RF
devices and circuits design. Fig. 10(a) and (b) illustrates the measured and calculated fT for nMOS and pMOS with donut
and standard layouts. Note that fT is extracted from the
extrap-olation of|H21| to unity gain and defined as fT = f (|H21| =
1). For nMOS shown in Fig. 10(a), the donut D10S10 gains an improvement of 5% in the maximum fT compared with the
standard and D1S1. The benefit from the donut layout becomes particularly larger for pMOS. As shown in Fig. 10(b), the donut pMOS D1S1 presents the best performance with the highest
fT and realizes a 28% increase in the maximum fT than the
standard pMOS.
The improvement of fTmeasured from donut MOSFETs can
be explained consistently by the enhancement of μeff and Gm,
according to the fT calculated by the analytical model as a
function of Gm and gate capacitances Cgg and Cgd, which is
given by (7) [10] in the following:
fT = Gm 2π C2 gg− Cgd2 (7) Cgg= Im(Y11) ω (8) Cgd= − Im(Y12) ω . (9)
A good match between the measured and calculated fT, as
shown in Fig. 10(a) and (b), for both nMOS and pMOS with different layouts (W2N32, D1S1, and D10S10) justifies the accuracy of the proposed analytical model. According to (7), it is predicted that fT is proportional to Gmand the enhancement
of Gmcan boost fT under fixed gate capacitances (i.e., Cggand
Cgd). The gate capacitances Cggand Cgdcan be extracted from
two-port Y-parameters according to (8) and (9). The results shown in Fig. 11(a) and (b) for nMOS and pMOS indicate negligibly small difference in Cggand Cgd between the donut
Fig. 11. Gate capacitances Cggand Cgdversus VGSextracted from Im(Y11)
and Im(Y12) for standard and donut MOSFETs (a) NMOS (b) PMOS.
Stan-dard : multi-finger W2N32. Donut : D1S1 and D10S10.
Fig. 12. Low frequency noise SID/IDS2 versus frequency (|VDS| =
0.05 V,|VGT| = 0.7 V) measured from the standard and donut MOSFET
(a) NMOS (b) PMOS. Standard : multi-finger W2N32. Donut : D1S1 and D10S10.
and standard layouts, as compared with that of Gm(see Figs. 5
and 8). Therefore, the layout dependence of fT just follows
that of Gm, i.e., the higher fT corresponding to the larger Gm.
Regarding other RF performance parameters such as the max-imum oscillation frequency fmax and the noise figure NFmin
(not shown), the donut MOSFETs may suffer certain degree of degradation due to inherently larger gate resistances than the standard multifinger MOSFETs. The experimental results suggest that an innovative donut device layout is required to cover all of the RF and analog performance.
E. LFN of Standard and Donut MOSFETs
Fig. 12(a) and (b) makes a comparison of LFN in terms of
SID/ID2 between the standard and donut layouts for nMOS
and pMOS, respectively. The noise spectrum follows the 1/f function over a wide frequency range from 4 to 10 kHz. It means that the measured LFN is typical flicker noise. The standard device (W2N32) reveals nearly twice larger SID/ID2
compared with the donut devices (D1S1 and D10S10) for both nMOS and pMOS, under the specified gate overdrive voltage
|VGT| = 0.7 V. In contrast, the donut device D10S10 with the
most extended gate-to-STI-edge distance indicates the lowest
SID/ID2. The results can be explained consistently by the fact
that D10S10 can keep free from σ⊥, as well as interface traps near the STI edge, and the smallest σ//due to ten times larger
space away from the STI edge compared with D1S1.
To explore the mechanism responsible for the LFN, SID/IDS2
measured at 50 Hz and various |VGT| (0.1–0.7 V) are
plot-ted versus (Gm/IDS)2 for three different layouts (W2N32,
D1S1, and D10S10), as shown in Fig. 13. For nMOS shown in Fig. 13(a), measured SID/IDS2 reveals a linear increasing
function of (Gm/IDS)2 for all three devices. As for pMOS
Fig. 13. Low frequency noise SID/IDS2 versus (Gm/IDS)2 under various
|VGT| (0.1 ∼ 0.7 V) for standard and donut devices (a) NMOS (b) PMOS.
Standard : multi-finger W2N32. Donut : D1S1 and D10S10.
Fig. 14. Low frequency noise SID/IDS2 versus IDSunder varying|VGT|
(0.1∼ 0.7V) for standard and donut devices (a) NMOS (b) PMOS. Standard : multi-finger W2N32. Donut : D1S1 and D10S10.
shown in Fig. 13(b), measured SID/IDS2 indicates weak
depen-dence on (Gm/IDS)2in the strong inversion region (|VGT| =
0.3−0.7 V) and a minor increase under weak inversion at the lowest|VGT| = 0.1 V. Referring to the drain-current
fluctua-tion model proposed in [11], as given by (10), the first term represents the carriers number fluctuation, and the second term denotes the correlated mobility fluctuation. SID/IDS2 measured
from nMOS [see Fig. 13(a)], revealing a good linear function of (Gm/IDS)2, is dominated by the first term in (10), i.e.,
the carriers number fluctuation. As for the pMOS, measured
SID/IDS2 [see Fig. 13(b)], showing nearly a constant
indepen-dent of (Gm/IDS)2, suggests the dominance of the second term
in (10), i.e., the correlated mobility fluctuation.
To verify further the mechanism, measured SID/IDS2 is
plot-ted versus IDS, as shown in Fig. 14. For nMOS, SID/IDS2
shown in Fig. 14(a) indicates a good match with the number-fluctuation model given by (11) in which SID/IDS2 under
various VGT is proportional to Nt/IDS2 , and that predicts the
increase in flicker noise with increasing the traps’ density Nt
[12]. It is believed that the gate-to-STI-edge overlap region will suffer the most severe compressive strain, as well as the interface traps Nt, and the donut devices can eliminate these
effects along the gate width, i.e., in the transverse direction. According to a previous study, the stress-generated traps may aggravate the scattering effect and increase the flicker noise [13]. The mentioned mechanism can explain why the donut MOSFETs, which are free from the gate-to-STI-edge overlap region can achieve the lowest flicker noise.
SID IDS =q 2k BT λNt fγW LC2 ox W LCox2 1+αμeffCox IDS Gm 2 Gm IDS 2 (10) SID I2 DS =q 2k BT λNt fγ W μ2 effVDS2 L3 1 I2 DS (11)
Fig. 15. Statistical distribution of SID/IDS2 (|VDS| = 0.05 V, |VGT| =
0.7 V) measured from standard (W2N32) and donut (D1S1, D10S10) devices (a) NMOS and (b) PMOS.
As for the pMOS shown in Fig. 14(b), measured SID/IDS2
follows a simple power law of 1/IDS and manifests itself
governed by the mobility-fluctuation model, according to the Hooge empirical formula expressed in (12) [14]. In addition, the model for SID/IDS2 can be expressed as a function of
VGT, which is given by (13). Note that the Hooge parameter
αH is dimensionless and may vary with biases and process
technologies. The reduction of flicker noise measured from the donut pMOS suggests the suppression of mobility fluctuation due to the eliminated compressive σ⊥. Furthermore, the in-crease in|VGT| can help suppress the flicker noise in terms of
SID/IDS2 . SID I2 DS =1 f αHμeff L2 qVDS IDS (12) SID I2 DS =q f 1 W LCox × αH VGT , VGT= (VGS− VT) (13)
αH: the Hooge parameter.
Fig. 15 makes a comparison of the flicker noise in terms of SID/IDS2 between three different device layouts,
incorporat-ing die-to-die variations. For nMOS shown in Fig. 15(a), the standard device (STD: W2N32) reveals 85% higher SID/IDS2
in the mean value than donut devices (D1S1 and D10S10), and D10S10 manifests itself the best one with the minimum
SID/IDS2 . All of the three layouts present similar standard
variation in the statistical distribution. The results justify that the donut layout can keep the MOSFETs free from σ⊥, as well as interface traps near the STI edge, and then achieve lower
SID/IDS2 . For D10S10 compared with D1S1, ten times larger
space away from the STI edge can effectively suppress σ//and
push the flicker noise SID/IDS2 to a lower value. Similar results
are demonstrated for pMOS in Fig. 15(b), but the standard pMOS (W2N32) reveals significantly higher SID/IDS2 in mean
and standard variation, and the difference between two donut pMOS devices (D1S1 and D10S10) is very minor. As a result, the proposed STI stress and excess traps can explain the layout dependence of the flicker noise for both nMOS and pMOS.
To explore the mechanism responsible for the lower flicker noise in donut nMOS, the interface-trap density Nt
appear-ing in the number-fluctuation model (11) was extracted from measured SID/IDS2 for nMOS with various layouts. Note that
the tunneling attenuation length λ is specified as 1 Å and the frequency exponent γ is 1.7 for the Si/SiO2 system [15]. The
extracted trap density, as shown in Fig. 16, affirms that Nt
can be reduced significantly by around twice for donut nMOS,
Fig. 16. Statistical distribution of interface trap density Ntextracted from number fluctuation model of LFN for standard (W2N32) and donut (D1S1, D10S10) NMOS. VDS= 0.05 V, VGT= 0.7 V.
Fig. 17. (a) SID/IDS2 versus VGT(b) Hooge parameter αHversus VGTfor
standard (WN32) and donut (D1S1, D10S10) PMOS. αH is extracted from mobility fluctuation model.
as compared with standard nMOS. Furthermore, D10S10 has lower Nt, as compared with D1S1, due to the suppression of
STI stress in both longitudinal and transverse directions, i.e.,
σ//and σ⊥.
As for pMOS, the flicker noise is dominated by the mobility-fluctuation model described by (12) and (13) in which the Hooge parameter αHappears as the key parameter to be
deter-mined. Fig. 17(a) presents SID/IDS2 under various VGTvalues,
which are measured from pMOS with specified three layouts (STD: W2N32, D1S1, and D10S10). The higher|VGT| can help
reduce SID/IDS2 , which is attributed to an increase in inversion
carriers and, then, higher IDS, as shown in (12) and (13). Note
that the standard pMOS (W2N32) suffers the largest SID/IDS2 ,
whereas the donut pMOS D1S1 indicates the lowest SID/IDS2 ,
which may be attributed to the Gm and μeff enhancement.
According to measured SID/IDS2 and extracted μeff(see Fig. 9),
αH can be determined from (12) or (13) under varying IDSor
VGT. The result shown in Fig. 17(b) indicates that αHis weakly
dependent on VGTand its layout dependence just follows that
of SID/IDS2 . The standard pMOS reveals the largest αH, and the
donut pMOS D1S1 indicates the smallest αH. The reduction of
αH and the resulted suppression of SID/IDS2 in donut pMOS
suggest that the elimination of STI transverse stress σ⊥ can reduce carrier scattering as well as mobility fluctuation and then lead to smaller αH, which is determined by mobility fluctuation
from multiple-scattering mechanisms [16]. IV. CONCLUSION
The proposed donut MOSFETs demonstrate the advantages over the standard multifinger MOSFETs, such as the lowest
SID/IDS2 in the low-frequency domain (1–10 kHz) and higher
trap density can explain consistently the advantages from the donut devices. An innovative donut MOSFET layout for solv-ing the potential degradation of fmaxand NFminemerges as an
interesting and important topic in the future work for RF and analog applications.
ACKNOWLEDGMENT
The authors would like to thank the Chip Implementation Center for the device fabrication and Nano Devices Laboratory for the noise measurement.
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Kuo-Liang Yeh (M’09) received the B.S.E.E.
de-gree from National Chiao Tung University (NCTU), Hsinchu, Taiwan, in 1995 and the M.S.E.E. degree from National Taiwan University, Taipei, Taiwan, in 1997. He is currently working toward the Ph.D. degree in electronics engineering with NCTU.
In 1999, he joined the Taiwan Semiconductor Manufactory Company Inc., Hsinchu, where he has worked on process integration and yield improve-ment. From 2004 to 2007, he was a Senior Engineer with MediaTek Inc., Hsinchu. He is currently a Se-nior Manager with the Silicon Motion Technology Corporation, Hsinchu. He is the author of more than ten technical publications in international journals and conference proceedings. His research interests include the characterization and the parameter extraction of complementary metal–oxide–semiconductor devices for modeling and circuit simulation, as well as the protection of intellectual property rights.
Jyh-Chyurn Guo (M’06–SM’07) received the
B.S.E.E. and M.S.E.E. degrees from National Tsing Hua University, Hsinchu, Taiwan, in 1982 and 1984, respectively, and the Ph.D. degree in electronics en-gineering from the National Chiao Tung University (NCTU), Hsinchu, in 1994.
For more than 19 years, she was with the semi-conductor industry, where her major focus was on device design and very-large-scale-integration tech-nology development. In 1984, she joined the Elec-tronics Research and Service Organization/Industrial Technology Research Institute (ERSO/ITRI), where she had been engaged in semiconductor integrated circuit technologies with a broad scope that covers high-voltage high-power submicrometer projects, high-speed static random access memory technologies, etc. From 1994 to 1998, she was with the Macronix International Corporation and engaged in high-density as well as low-power Flash-memory technology development. In 1998, she joined the Vanguard International Semiconductor Corporation, where she assumed the responsibility of the Device Department Manager for advanced dynamic ran-dom access memory device technology development. In 2000, she joined the Taiwan Semiconductor Manufacturing Company (TSMC), where she served as a Program Manager in charge of 100-nm logic CMOS front-end-of-line technology development, high-performance-analog technology development, and RF CMOS technology development. In 2003, she joined the Department of Electronics Engineering, NCTU, as an Associate Professor, and since 2008, she has been a Full Professor. She is the author or coauthor of more than 60 technical papers and is the holder of 19 U.S. patents in her professional field. Her current research interests include RF/mixed signal CMOS device design and modeling for low power and low noise, nanoscale CMOS noise modeling and strain engineering effects, broadband and scalable inductors modeling, novel nonvolatile memory technologies, and device integration technologies for system on a chip.
