Germanium N and P Multifin Field-Effect
Transistors With High-Performance Germanium
(Ge) p
+
/n and n
+
/p Heterojunctions
Formed on Si Substrate
Che-Wei Chen, Cheng-Ting Chung, Ju-Yuan Tzeng, Pin-Hui Li, Pang-Sheng Chang,
Chao-Hsin Chien, and Guang-Li Luo
Abstract— We demonstrate the characteristics of p+-Ge/n-Si and n+-Ge/p-Si heterojunction diodes formed by heteroepitaxial Ge grown on Si leading to high performance and very low leakage current. The ON/OFF current ratio of the p+-Ge/n-Si and n+-Ge/p-Si heterojunction was>107and>106, respectively. The OFF current density was extremely low at <10 μA/cm2 for the p+-Ge/n-Si formed with different implantation energies of 10 ∼ 40 KeV and ∼20 μA/cm2 for the n+-Ge/p-Si with different implantation energies of 20 ∼ 50 KeV at a reverse bias of |VR| = ±1 V, respectively. Both p and n-Ge channel multifin field-effect transistors (FinFETs) were formed by a mesa structure using these p+-Ge/n-Si and n+-Ge/p-Si heterojunctions. A high-κ/metal gate stack was employed. The body-tied Ge multifin FinFET with a fin width (WFin) of ∼40 nm, and the channel length (LChannel) was 150 nm for p-FinFET and of 110 nm for n-FinFET, exhibiting a driving current of 174μA/μm at VG= −2 V and 102 μA/μm at VG= 2 V, respectively. This is the first experimental demonstration of a body-tied high mobility Ge channel multifin FinFET using a top-down approach.
Index Terms— Body-tied, germanium, multifin field-effect tran-sistors (FinFETs), silicon p+-Ge/n-Si heterojunction, n+-Ge/p-Si heterojunction
I. INTRODUCTION
I
N THE past decade, Germanium (Ge) has been investigated as a high-mobility channel material as a substitute for silicon channels in order to continuously boost the ONcurrent (Ion) of MOSFETs. One of the concerns, however, is a smallband gap (Eg= 0.67 eV) owing to the presence of band-to-band tunneling (BTBT) leakage current at the drain junction
Manuscript received December 15, 2012; revised February 10, 2013; accepted February 12, 2013. Date of current version March 20, 2013. This work was supported in part by the National Science Council of Taiwan under Grant NSC 98-2221-E-009-173-MY3 and Grant NSC 101-2628-E-009-011-MY3. The review of this paper was arranged by Editor W. Tsai.
C.-W. Chen, C.-T. Chung, J.-Y. Tzeng, P.-H. Li, and P.-S. Chang are with the Department of Electronics Engineering and the Institute of Electronics, National Chiao Tung University, Hsinchu 30010, Taiwan (e-mail: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]).
C.-H. Chien is with the Department of Electronics Engineering and the Institute of Electronics, National Chiao Tung University, Hsinchu 30010, Taiwan, and also with the National Nano Device Laboratories, Hsinchu 30078, Taiwan (e-mail: [email protected]).
G.-L. Luo is with the National Nano Device Laboratories, Hsinchu 30078, Taiwan (e-mail: [email protected]).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2013.2247766
when a high electric field exists [1], [2]. However, when the device is scaled down to a short-channel region, especially at the level of nanometer dimensions, the junction leakage becomes more severe because a stronger electric field exists, caused by the higher substrate-doping concentration [3]. More-over, the source/drain (S/D) junctions of Ge MOSFETs need to be designed carefully for the purpose of parasitic resistance reduction and short-channel effect control [4] in advanced devices such as multifin field-effect transistors (FinFETs). However, n-type dopants in Ge diffuse extraordinarily fast [5], and possess relatively low dopant solubility [6]. These two features make the formation of shallow junctions with suffi-ciently low resistance very challenging. Moreover, the pres-ence of Fermi level pinning in the metal/n-Ge contact has been reported, which leads to large contact resistance [7]. This effect will also contribute to the magnitude of parasitic resistance and in turn deteriorate the ON current of the channel transistor. Therefore, making a high-performance Ge-n-FET is rather challenging. On the other hand, integrating Ge devices onto a Si wafer is very attractive from the viewpoint of cost control and the range of platforms already built on Si, despite the ∼4.2% lattice mismatch existing between Ge and Si. Thus, depositing high-quality epitaxial Ge film with minimum defect density is also very hard. This is why in the previous studies, the heterojunction diodes always showed low ION/IOFF ratios and high-leakage current densities [8], [9].
In our previous works [10], [11], we reported that the Ge p-channel FinFET (p-FinFET) was successfully fabricated directly on the Si and Si-on-insulator (SOI) substrate. The low leakage current of p+/n and n+/p heterojunctions were also investigated [12]. We suppose that most of the junction depletion region was built inside the Si side, which can restrain the BTBT-leakage current in Ge and then can lead extremely low junction-leakage current. However, fabrication of nonplanar CMOS FinFETs has not yet been demonstrated in the published literature. The nonplanar FET is very attractive for future applications since it has better channel potential control ability to cope with the short-channel effects (SCEs) [13], [14]. Certainly, there are still a lot of challenges that need to be overcome in integrating Ge FinFET on top of the Si wafer before mass production. In this paper, we illustrate p+-Ge/n-Si and n+-Ge/p-Si heterojunction diodes with a very high ION/IOFF ratio and very low leakage current using 0018-9383/$31.00 © 2013 IEEE
II. EXPERIMENTS
Undoped Ge films with thicknesses of 120 and 160 nm were grown on the n- (2 ∼ 7 ohm-cm) and p-type (15∼ 25 ohm-cm) 6-in Si(100) substrates, respectively, using ultrahigh vacuum chemical vapor deposition after a standard cleaning. The films were baked at 900 °C for 10 min in a high-vacuum ambient to desorb Si surface native oxide before Ge was deposited. After Ge deposition, the postdeposition annealing (PDA) was performed at 900 °C for 10 min without a vacuum break in order to reduce dislocation, owing to lattice mismatch between Si and Ge. According to a previous study, 900 °C annealing is capable of effectively reducing the threading dislocation density and improving single crystalline Ge-film quality [15].
In order to avoid the channeling effect, an oxide of 10-nm thickness was deposited by plasma-enhanced chemical vapor deposition (PECVD) on the Ge surface before an implanted region was defined. Various dopant energy of boron ions (10, 20, 30, 40 keV, 1× 1015 cm−2) and phosphorus ions (20,
35, 50 keV, 1× 1015 cm−2) were respectively implanted in the active area with 120- and 160-nm Ge, and subsequently a 100-nm PECVD oxide was deposited for restraining dopant outdiffusion during a rapid thermal annealing (RTA) process. The implantation energy was 20 keV for p-FinFETs and 35 keV for n-FinFETs, respectively. Activation was performed in nitrogen ambient for 10 s at 500 °C (p+-Ge/n-Si) and for 10 s at 600 °C (n+-Ge/p-Si) to form the Ge/Si heterojunction diode as an S/D of CMOS devices. A heterojunction area (625μm2) and multifin channel structure was formed by using reactive ion etch (RIE) anisotropic etching in Cl2/HBr ambient
using oxide as a hard mask after patterns were performed by lithography. At the same time, a Si substrate was also etched slightly by chlorine until the etching was stopped at the Si substrate. The spin on glass (SOG) was coated (∼650 nm) and etched back for device isolation after removing oxide and dilute hydrofluoric cyclic surface cleaning. The GeO2was used
as a surface passivation layer using rapid thermal oxidation (RTO) at 520 °C for 30 s and then an Al2O3high-κ dielectric
deposition was performed by atomic layer deposition. In particular, the utility of thermally grown GeO2as a good
elec-trical passivation layer for high-κ dielectrics was investigated [16]–[20]. The metal gate Ti (5 nm)/Pt (100 nm) was deposited by sputtering, and a lift-off process was performed. Metal-lization Ti (5 nm)/Pt (50 nm) contact for p+-Ge/n-Si and Ti (5 nm)/Au (50 nm) contact for n+-Ge/p-Si heterojunction were deposited by sputtering and a lift-off process as well. Finally, a back-metal contact Al was carried out by thermal evapora-tion. Both p+-Ge/n-Si and n+-Ge/p-Si heterojunction diodes and the body-tied Ge FinFET CMOS devices were created. All
(c) (a)
Fig. 1. (a) Schematic illustration of Ge-channel multifin FinFET. (b) TEM image of a Ge/Si interface showing the existence of a misfit dislocation density. (c) XRD of 160-nm Ge on Si with postdeposition annealing.
patterns were defined by electron-beam system and a Keithley 4200 was used to measure electrical characterization.
III. HETEROJUNCTIONDIODES
Fig. 1(b) shows the transmission electron microscopy (TEM) image of crystalline Ge film on Si. The existence of misfit dislocations at the Ge/Si interface can be observed owing to the lattice mismatch. A uniform interface between Ge and Si was also seen, implying PDA does not result in the diffusion of Ge into Si. In the x-ray diffraction (XRD) rocking curve, as shown in Fig. 1(c), we saw that the intensity of the Ge peak was slightly higher and the full width half maximum was also narrower than those in the previous report [21], indicative of better Ge-film quality. Both suggest that high quality of single-crystalline Ge film had been grown directly on the Si wafer for the starting material.
Fig. 2(a) shows secondary ion mass spectrometry (SIMS) dopant profiles of the p+-Ge/n-Si heterojunction diode with implantation energies of 10, 20, 30, and 40 KeV before and after RTA. The dashed line indicates the thickness of the epitaxial Ge film. After the RTA process, the depth profile of boron dopants were hardly redistributed, and no deeper diffusion was observed. This result was similar to that in the previous report [22]; the pairing of boron with the defects has a high binding energy so that the atoms are almost immobile at each level of implantation energy. Moreover, we think most of the dopants residing in the Si region remain inactive since the thermal energy of low-temperature RTA used in this work was insufficient to activate the dopants. As a result, a similar leakage current level of the diodes with four implantation energies was obtained. Fig. 2(b) shows the SIMS-dopant profiles of the n+-Ge/p-Si heterojunction diode. A slight diffusion of phosphorous dopants was observed after the annealing due to the relatively higher thermal budget required for the n-type dopant activation in Ge [23]. Upon prolonged annealing, P is more likely to precipitate, and the profile of the junction tends to become more graded [24].
Thermal annealing for reducing the threading dislocation density is known to enhance device performance and lead to an OFF current reduction [25]. Moreover, a good
passi-(a)
(b)
Fig. 2. (a) SIMS depth profile of the p+-Ge/n-Si heterojunction diode with 10∼ 40 KeV implantation energies and RTA (500 °C 10 s in N2 + 520 °C 30 s in O2). (b) SIMS depth profile of the n+-Ge/p-Si heterojunction diode with 20∼ 50 KeV implantation energies and RTA (600 °C 10 s in N2 + 520 °C 30 s in O2). The dashed line indicates the epi-Ge layer thickness.
vation is also required for fabricating Ge diodes with suf-ficiently low OFF current density [26], [27] because the surface leakage current can be eliminated [28]. We fabri-cated the p+-Ge/n-Si and n+-Ge/p-Si heterojunction diodes with the GeO2 surface passivation by RTO at 520 °C
for 30 s and SOG isolation. The different implantation ener-gies varied from 10 to 40 keV for p+-Ge/n-Si and from 20 to 50 keV for n+-Ge/p-Si heterojunctions in order to examine the corresponding variation of the leakage current. Pure Ge p+/n and n+/p junction diodes were also made for comparison; GeO2 was formed by the same condition
of 520 °C for 30 s and removed during the contact-holes formation. As a result, as shown in Fig. 3(a), the p+ -Ge/n-Si heterojunction diode depicts a very high ION/IOFF > 107
and an extremely low OFF current density (<10 μA/cm2 at V = −1 V) no matter what implantation energy was used. The pure Ge p+/n homojunction showed the ION/IOFF of ∼105 and I
OFF of 800 μA/cm2 at V = −1 V. Strikingly,
the leakage current of heterojunction is about two orders of magnitude smaller than that of pure Ge p+/n junction, even though the misfit dislocations have been seen at the Ge/Si interface. On the other hand, the BTBT leakage current in Ge was effectively suppressed due to the fact that most of the depletion region was built inside the n-Si side for every implantation energy. The ideality factor∼1.1 of our p+
-Ge/n-(a)
(b)
Fig. 3. (a) I–V characteristics of p+-Ge/n-Si heterojunction diode with high ION/IOFF> 107with various implantation energies of 10∼ 40 KeV and a pure Ge p+/n homojunction for comparison. (b) I–V characteristics of n+-Ge/p-Si heterojunction diode with high ION/IOFF > 106 with various implantation energies of 20∼ 50 KeV and a pure Ge n+/p homojunction for comparison.
Si heterojunction was extracted. Recently, there are many articles focusing on the Ge-junction diode being published. Yu et al. [29] also reported the selective growth method epi-Ge p+/n junction diode on the Si using the selective multiple hydrogen anneals by heteroepitaxial (MHAH) technique. The diode had an OFF current density of >10−4 A/cm2 at V = −1 V and ION/IOFF< 104. Park et al. [8] reported the Ge
p+/n junction diode on the Si substrate using metal-induced dopant activation (MIDA) technique with ION/IOFF∼2.1×104
in which IOFF was>1 mA/cm2at V = −1 V.
Fig. 3(b) shows the electrical characteristic of n+ -Ge/p-Si heterojunction diodes with high ION/IOFF> 106 and a
low OFF current density ∼20 μA/cm2 at V = 1 V with implantation energies of 20, 35, and 50 KeV. The pure Ge n+/p homojunction showed ION/IOFF of ∼105 and IOFF
of 7 mA/cm2 at V = 1 V. The leakage current level of n+-Ge/p-Si heterojunction is two orders of magnitude lower than that of the pure Ge homojunction due to the fact that Si has a relatively large band gap. However, the ON current of the n+-Ge/p-Si heterojunction was slightly lower than that of the pure Ge homojunction. We speculate that this is due to the fact that the defects in the phosphorus doped epitaxial Ge are very difficult to annihilate compared to those in the single crystalline Ge [4]. In the previous study, Park et al. [30] reported the Ge n+/p junction diode formed on the Si substrate
the viewpoint of power consumption. To demonstrate the uniformity of leakage current in the electrical performance, the cumulative probability versus leakage current density (at V = −1 V) is shown in Fig. 4. We can see that a tight control had been obtained since there was a very narrow distribution of leakage current density of p+-Ge/n-Si heterojunction. No matter what implantation energy was used, the leakage current distributed between 2 and 6 μA/cm2.
In order to explain why our diodes have exhibited such excellent properties, we think it is necessary to resort to the fundamental current conduction mechanisms of the pn diodes. As is well known, there are four possible primary origins of leakage current in a diode: 1) generation current within the space charge region; 2) diffusion current outside the space charge region; 3) generation of minority carriers at the surface in the periphery [31], [32]; and 4) BTBT current. We suppose that the surface generation current was restrained by the GeO2surface passivation because GeO2/Ge system has
much better interface quality. Meanwhile, the BTBT leakage current was effectively eliminated by the heterostructure since Si has a relatively large band gap. Therefore, we suggest that the generation current within the space charge region and the diffusion current outside the space charge region are the dominant factors. If V kT/q, the magnitude of the generation current within the depletion region will be given by Igen = 1 2q ni τ0 W A (1)
where q is the charge on an electron, ni is the intrinsic
carrier concentration, τ0 is the minority carrier lifetime, W
is the width of the depletion region, and A is the area of the heterojunction. We expect the generation current component to have the same temperature dependence as ni, and it is
dependent on the magnitude of the reverse bias. The generation current increases in proportion to W due to the fact that more centers are within the depletion region. From I–V curve, we saw that the OFF current was nearly independent of reverse bias. So, we can rule out the possibility that the leakage current is generated through the threading dislocations. On the other hand, there is no significant electric field present in the neutral regions and the minority carriers move by diffusion. The diffusion currents due to holes and electrons are described by
Idiff,p= q Dp n2i NDLp A (2) and Idiff,n = q Dn n2i NALn A (3)
Fig. 4. Plot of cumulative probability versus leakage current density (at
V = −1 V), showing tight control and narrow distribution of leakage current
density of p+-Ge/n-Si heterojunction.
(a) (b)
Fig. 5. Activation energies (Ea) estimated from the slope of the ln(JR) versus 1/T plot of (a) p+-Ge/n-Si and (b) n+-Ge/p-Si heterojunction, respectively.
respectively, where Dp is the hole diffusivity, ND is the donor
impurity concentration, Lp is the diffusion length of holes in
the n-region, and vice versa. No bias-dependent item is seen in these equations and the temperature dependence arises from the term of n2i.
The temperature dependence of I–V characteristic of the heterojunction diodes was measured in order to identify the carrier conduction mechanism. Fig. 5(a) and (b) shows the activation energies (Ea) of our diodes, which were estimated
from the slope of the ln(JR) at V = ±1 V versus 1/T plot
of p+-Ge/n-Si and n+-Ge/p-Si, respectively. In Fig. 5(a), it was seen that there were two different slopes in the whole temperature range, representing different dominant conduction mechanisms. However, the temperature dependencies of the generation and diffusion current are known to come form ni
and n2i, respectively; at a higher temperature the feature of higher band gap material dominates the characteristic of the heterojunction pn diode [32]. The value of∼0.26 eV suggests that generation-recombination current of Ge is dominant at low temperatures. On the other hand, the value of∼0.78 eV suggests that the generation-recombination current of Si is dominant at high temperatures. From Fig. 5(b), a larger Ea (∼0.38 eV) of n+-Ge/p-Si heterojunction than that of
(a) (b)
Fig. 6. Activation energies (Ea) of (a) p+/n Ge and (b) n+/p Ge
homojunction as a function of temperature, respectively.
p+-Ge/n-Si heterojunction is shown at low temperatures. This value is close to half of the band gap of Ge, implying that generation-recombination current in Ge dominates for the heterojunction due to the fact that the diffusion of phosphorus dopants is further enhanced by the implant damage [33]. A smaller Ea (∼0.62 eV) of n+-Ge/p-Si heterojunction
indi-cates that the implantation-induced-defect-assisted tunneling is a possible conduction mechanism in the high-temperature region. Fig. 6(a) and (b) shows the activation energies of the p+/n Ge and n+/p Ge homojunctions, respectively. The activation energy was of about 0.66 eV, indicating that that the characteristic of the Ge homojunction diode is dominated by the diffusion current. This is the same with the situation found in the p+/n Si homojunction with an activation energy of about 1.1 eV (∼Eg) [34]. From Fig. 6(b), an activation of about
0.36 eV of n+/p Ge homojunction was close to half of the band gap of Ge, implying that the generation-recombination current is a dominant component. Our results are similar to those reported in the previous work [35].
A specific contact resistance RC is important issue for
high-performance devices. The specific contact resistances of our metal/p+ and metal/n+ junctions were evaluated using the TLM structures [36], which are known to depend on both the metal pad area and width (contact spacing). The TLM structure and I–V electrical characteristics are shown in the inset of Fig. 7. In Fig. 7(a), the contact resistance of the metal/p+-Ge is plotted versus contact width, in which the slope of the curve gives the sheet resistance (ρsh) and
the intercept of x axis gives the transfer length (LT). The
specific contact resistance was c.a. 2.8 × 10−5 -cm2and the sheet resistance was c.a. 180/sq. These values are acceptable, and further improving of the specific contact resistance can be through a germanide layer between the contact metal and p+-Ge. The specific contact resistance the metal/n+-Ge was c.a. 1.7 × 10−5 -cm2 and the sheet resistance was 118 /sq, as shown in Fig. 7(b). Furthermore, the specific contact resistance is lower than the values reported in the former literature [37], [38].
IV. MULTIFINFINFETCMOS
Fig. 8(a) shows the tilted plane-view scanning electron microscope (SEM) image of Ge multifin with S/D electrodes
(a) (b)
Fig. 7. (a) I–V plots and TLM structure (inset) of the metal/p+-Ge contact, and contact resistance is plotted versus width (contact spacing). (b) I–V plots and TLM structure (inset) of the metal/n+-Ge contact and contact resistance is plotted versus width (contact spacing).
Fig. 8. (a) Shows the tilted SEM image of Ge multifin with S/D patterns on Si substrate with five fins and fin width was∼40 nm. (b) Shows the cross-sectional TEM image of Ge multifin with 5-nm Al2O3high-κ dielectrics Ti/Pt metal gate stack and SOG as device isolation.
(a) (b)
Fig. 9. (a) IDS–VGtransfer characteristic and IDS–VDSoutput characteristic (inset) of Ge multifin p-FinFET with a LChannelof 150 nm and WFinof 40 nm. (b) IDS–VG transfer characteristic and IDS–VDSoutput characteristic (inset) of Ge multifin n-FinFET with a LChannelof 110 nm and WFinof 40 nm.
on the Si substrate. There were five Ge fins with fin width ∼40 nm. Fig. 8(b) shows the cross-sectional TEM image of Ge multifins with 5-nm Al2O3high-κ dielectrics and Ti/Pt metal
gate stack. Fig. 9(a) shows the IDS-VG transfer characteristic
of Ge multifin p-FinFET with LChannelof 150 nm and WFinof
40 nm in the linear region at VDS = 0.1 V and saturation
region at VDS = 1 V. The total effective channel width
(WEff = 2× HFin+WFin) of p-FinFET was∼285 nm and drain
current (IDS) was normalized by 5× WEff. The subthreshold
swing (S.S.) was 238 mV/dec and the drain-induced barrier lowering (DIBL) was 222 mV/V. The ION/IOFF ratio was ∼2 × 103. These results suggest that the equivalent oxide
subthreshold slope. Our device exhibited a driving current of 174 μA/μm at VG = −2 V, which was higher than seen in
the earlier literature (∼30 μA/μm) [21]. Certainly, the multifin structure is more appropriate for future applications than the single fin one. More importantly, our device structure is a Ge body-tied FinFET, which is much preferred from the viewpoint of cost effectiveness. Fig. 9(b) shows the IDS-VG transfer
characteristic of Ge multifin n-FinFET with LChannelof 110 nm
and WFinof 40 nm. The WEff of n-FinFET was∼365 nm. The
S.S. value was 110 mV/dec and the DIBL value was 89 mV/V. The ION/IOFF ratio was ∼2 × 104. The good sub-threshold
characteristics and a high driving current of 102 μA/μm at VG = 2 V were obtained. We think that the low ON current
level is due to the low solubility and the fast diffusivity of n-type dopants [23]. As seen with the p-FinFET, a shallower junction formation of n-FinFET can mitigate the SCEs. The IDS–VDS output characteristic of Ge multifin p-FinFET with
LChannel of 150 nm and n-FinFET with LChannel of 110 nm
was illustrated (see inset of Fig. 9). The saturation current of p-FinFET and n-FinFET was 81 μA/μm and 56 μA/μm, respectively, at VDSand VGS= ±1 V. Finally, we fabricated
the short-channel Ge multifin n and p FinFETs directly on the Si substrate with relatively high driving current density with a fully Si CMOS compatible scheme.
V. CONCLUSION
We have demonstrated the p+-Ge/n-Si and n+-Ge/p-Si heterojunction diodes achieved by the mesa structure directly on the Si substrate and investigated the origins of leakage current density on the diode’s performance through activation energy extraction and I–V measurements. Afterwards, non-planar body-tied Ge multifin FinFET CMOS devices with Al2O3 high-κ dielectrics Ti/Pt metal gate stack were
fabri-cated. Both p+-Ge/n-Si and n+-Ge/p-Si heterojunction diodes exhibited very high ION/IOFF ratios, which were >107 and
>106, respectively. Significantly lowOFFcurrent density was
observed <10 μA/cm2 for p+-Ge/n-Si and∼20 μA/cm2 for n+-Ge/p-Si at VR= ±1 V with various implantation energies.
The short-channel length 150-nm Ge multifin p-FinFET device had a high driving current of 174 μA/μm at VG = −2 V
with S.S. = 238 mV/dec and DIBL = 222 mV/V. We think the subthreshold performances can be further improved by reducing EOT, interface traps (Dit) improvement, and using
a shallower junction formation. The short-channel length 110-nm Ge multifin n-FinFET device had a high driving cur-rent of 102μA/μm at VG = 2 V with good S.S. = 110 mV/dec
and DIBL = 89 mV/V. Finally, we think that our results for heterojunction diodes are promising for future applications of
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Che-Wei Chen received the M.S. degree in
elec-tronic engineering from National Tsing Hua Univer-sity, Hsinchu, Taiwan, in 2010, where he is currently pursuing the Ph.D. degree in electronic engineering with National Chiao Tung University, Hsinchu.
Cheng-Ting Chung is currently pursuing the Ph.D.
degree with the Department of Electronics Engineer-ing and the Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan.
His current research interests include Ge MOS-FETs, high-k/Ge gate stack, and tri-gate FETs.
Ju-Yuan Tzeng is currently pursuing the M.S.
degree in electronic engineering with National Chiao Tung University, Hsinchu, Taiwan.
His current research interests include Germanide contact.
Pin-Hui Li is currently pursuing the M.S. degree
with the Department of Communications Engineer-ing, National Chiao Tung University.
His current research interests include device physics of Ge MOSFETs.
Pang-Sheng Chang is currently pursuing the M.S.
degree in electronic engineering from National Chiao Tung University, Hsinchu, Taiwan.
His current research interests include the study of post Si devices.
