Analysis and Design of the 0.13-
m CMOS
Shunt–Series Series–Shunt Dual-Feedback Amplifier
Tzung-Han Wu, Member, IEEE, Jin-Siang Syu, Student Member, IEEE, and Chin-Chun Meng, Member, IEEE
Abstract—This paper demonstrates the design methodology of the shunt–series series–shunt dual-feedback Meyer wideband amplifier. The small-signal S-parameters are obtained for the first time using the pole-and-zero analysis, thus giving the RF designers a detailed insight into the Meyer amplifier. A 10-GHz wideband amplifier is demonstrated in this paper, using 0.13- m CMOS technology to verify our design theory. The experimental results of the S-parameters highly agree with our theory.
Index Terms—Dual feedback, Meyer amplifier, series–shunt feedback, shunt–series feedback, wideband amplifier.
I. INTRODUCTION
R
ECENTLY, high-frequency and wideband communica-tion applicacommunica-tions, such as the 60-GHz (WLAN, ultraw-ideband (UWB), and even Direct Broadcast Satellite (DBS)/low noise block (LNB), have arisen. In the past, the DBS or LNB re-ceivers have required a high-frequency LNA to receive the de-sired signal and a wideband buffer amplifier for additional gain amplification [1]–[3] when the gain of the first-stage LNA is insufficient. In addition, the 60-GHz WLAN front-end receiver [4], [5] has become more and more important, and this applica-tion may also require some extra gain block, depending on the system architecture and frequency planning. The UWB system inevitably needs a wideband LNA to increase the sensitivity of the entire receiver chain through 3–10-GHz RFs. There are already tremendous research topics about the wideband LNA [6]–[14] for UWB.The wideband amplifier is a general-purpose gain building block, and the main requirement of a wideband amplifier is its gain and input/output matching bandwidth. It is worthwhile to mention that not only the gain bandwidth but also the matching bandwidth has to meet the system requirement to provide extra gain to any RF system. The gain saturation point, the lin-earity performance, and the noise performance are also impor-tant criteria to judge whether a wideband amplifier is good or Manuscript received May 26, 2008; revised September 23, 2008. First pub-lished February 18, 2009; current version pubpub-lished November 04, 2009. This work was supported by the National Science Council of Taiwan, Republic of China, under Contract NSC 98-2221-E-009-033-MY3 and by the MoE ATU Program under Contract 95W803. This paper was recommended by Associate Editor B. Bakkaloglu.
T.-H. Wu was with the Department of Communication Engineering, National Chiao Tung University, Hsinchu 300, Taiwan. He is now with the RFIC design team, MediaTek Inc., Hsinchu, Taiwan.
J.-S. Syu and C.-C. Meng are with the Department of Electrical Engineering, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: ccmeng@mail. nctu.edu.tw).
Digital Object Identifier 10.1109/TCSI.2009.2015603
not. In the past, the microwave distributed amplifier has dom-inated the wideband application [15]–[17]. However, the dis-tributed amplifier wastes too many valuable chip estates, and thus, the cost cannot be low. Recently, the mainstream tech-nology is the feedback amplifiers [6]–[11], [18], [19].
Most of the feedback wideband amplifiers are single-stage amplifiers with inductive peaking techniques [6]–[10], [20]. Although the lumped feedback amplifiers have already saved a lot of space when compared with the distributed counterparts, the on-chip peaking inductors still consume extra chip space. As a result, the other useful two-stage amplifier topologies consisting of resistive feedback loops are more attractive for a low-cost consideration [21]–[27]. Among so many wideband amplifier topologies, there are basically two most popular two-stage wideband amplifier configurations—the Meyer (shunt–series series–shunt feedbacks) topology [21]–[23] and the Kukielka (shunt–series shunt–shunt feedbacks) topology [11], [24]–[26].
The Kukielka topology is a Cherry–Hopper amplifier [28] with a global shunt–series feedback loop [11], [26]. The Cherry–Hopper amplifier basically consists of a transconduc-tance amplifier in the first stage and a transimpedance amplifier in the second stage. The Kukielka amplifier preserves the broadband characteristic of the Cherry–Hopper amplifier, and the global shunt–series feedback loop can further increase the bandwidth. The input and output matching is achieved simultaneously by the global shunt–series feedback loop and the local shunt–shunt feedback loop. The design methodology of the Kukielka amplifier has already been well established in [11] and [26].
In this paper, those design equations considering the S-parameters of the Meyer wideband amplifier are deter-mined. The Meyer topology is a two-stage amplifier with two global shunt–series and series–shunt feedback loops, and this schematic makes the Meyer configuration totally different from the Kukielka topology. However, the gain bandwidth and the input/output matching bandwidth can be simultaneously achieved by two feedback loops, as shown in Fig. 1. Because there are two global feedback loops in the Meyer topology, the input and output common-mode level, as well as the bias currents, is well defined, as shown in Fig. 1.
In our previous work on the Kukielka amplifier [26], the loop gain is always less than one when the input matching is achieved. Therefore, the bandwidth is limited because the amplifier has an overdamped gain response. The capacitive peaking technique was employed to extend the bandwidth but the peak gain is 2 dB more than the dc gain and the group 1549-8328/$26.00 © 2009 IEEE
Fig. 1. Circuit schematic of the Meyer (shunt–series and series–shunt) amplifier.
delay has a variation of 20 ps within the 3-dB bandwidth. On the contrary, our proposed topology eliminates this fun-damental constraint; thus, the input/output matching can be achieved while the loop gain is still flexible. Without using the capacitive peaking, the 10-GHz bandwidth is achieved with a maximally flat gain response and only a 5-ps group-delay variation within the bandwidth.
Previous works [21], [22] have discussed the design equa-tions of the Meyer amplifier using bipolar junction transistor (BJT) technologies; however, the previously reported approach has limitations for the CMOS technologies caused by an invalid analytical approximation, as described in the following sections of this paper. To realize the insights of the Meyer wideband am-plifier, we use the pole-and-zero analysis [29], [30] to determine all of the design equations of the S-parameter. This paper pro-vides a consistent method to determine the frequency response of the gain and the terminal impedance matching when com-pared with [21] and [22]. Methods to solve the small-signal pa-rameters between this paper and previous counterparts are dis-cussed at the end of Section II. It is worthwhile to mention that the method we have proposed in this paper is more complete and general, particularly for the deep submicrometer CMOS tech-nologies.
To our best knowledge, the small-signal S-parameters of the Meyer topology has been established for the first time in this paper. Section II presents the detailed design parameters of the Meyer amplifier, including the gain, input/output impedances, loop gain, poles, and S-parameters. A Meyer amplifier based on these design principles is discussed in Section III. Measurement results are shown in Section IV, and Section V concludes this paper.
II. ANALYSIS OF THEMEYERWIDEBANDAMPLIFIER
A. DC Voltage Gain, Input Resistance, and Output Resistance of the Meyer Wideband Amplifier
The Meyer configuration consists of two feedback loops, as shown in Fig. 1. One of the feedback loops is the shunt–series global feedback, consisting of and , between the first-and second-stage common-source amplifiers. This feedback loop is a current-sampling shunt-mixing loop; therefore, the feedback loop provides current–current feedback [30]. On the other hand, the global series–shunt feedback is a voltage-sam-pling series-mixing feedback loop, consisting of and ,
Fig. 2. Block diagram of the Meyer wideband amplifier.
and provides voltage–voltage feedback [30]. The shunt–series and series–shunt feedback loops are represented by and , respectively.
Because the Meyer configuration contains two feedback loops, the A- and -circuits are too complicated to find. How-ever, the Meyer wideband amplifier can be decomposed step by step as follows. Fig. 2 shows the block diagram of the Meyer amplifier. As shown in Fig. 2, the Meyer amplifier can be treated as a voltage amplifier with a voltage–voltage feedback loop . Moreover, the A-circuit of the Meyer amplifier is a current feedback amplifier. As long as the open loop current gain and the feedback loop are found, the voltage gain to the load can be determined by
(1)
and are the dc input and output resistances of the cur-rent feedback amplifier. Therefore, the total closed-loop gain of the Meyer amplifier from input node A to output node B is
(2) The analytic forms of and will be defined later in the following section.
Fig. 3 shows the decomposition sequences of the Meyer am-plifier. First, the Meyer topology shown in Fig. 1 can be decom-posed into the circuit shown in Fig. 3(a). Fig. 3(a) contains a voltage amplifier and a voltage feedback loop . It is inter-esting that the A-circuit shown in Fig. 3(a) is actually a current amplifier with a shunt–series feedback loop. Hence, the A-cir-cuit shown in Fig. 3(a) can be further decomposed into a current amplifier with a feedback loop , as shown in Fig. 3(b).
First, the overall open-loop voltage gain of the Meyer topology can be described as (2). can be obtained by solving the closed-loop current gain , the input resistance , and the output resistance , including the loading effect [30] of the wideband amplifier circuit, as shown in Fig. 3(b). Therefore
Fig. 3. (a)A and circuits of the Meyer amplifier after first decomposition. (b)A and circuits after second decomposition.
Next, we calculate the , (the input resistance when the shunt–series feedback is taken into consideration), and (the output resistance when the series–shunt feedback is taken into consideration) of the current amplifier, as shown in Fig. 3(b). The is straightforward
(4)
where the resistance is the output resistance when looking into the drain node of the transistor . The input resistance of the current amplifier is
(5) Thus, the total dc input resistance of the Meyer amplifier can be determined by
(6)
with the feedback factors
(7)
Similarly, the output resistance can be obtained by
(8) where the resistance is the output resistance when looking into the drain node of the transistor . The resistance is greatly increased because the source node of the transistor is in series with a large shunt–series feedback resistance [30]. Therefore, the is very large [30], and the value of can
be neglected when , , and are parallel.
Thus, the dc total output impedance of the Meyer amplifier is equal to
(9) Using the circuit shown in Fig. 3, now can be described as follows:
(10) The total dc voltage gain of the Meyer amplifier is
(11)
Consequently, as shown in Figs. 1 and 2, the dc voltage gain from the voltage source to the load can be described as
(12) The dc values of the voltage gain, the input resistance, and the output resistance of the Meyer wideband amplifier are de-termined by (6), (9), and (12).
B. System Transfer Function
In order to determine the frequency response of the small-signal voltage forward transmission coefficient , we have to determine the system transfer function of the Meyer amplifier. From (11), the system transfer function must be
where is the voltage gain and is a ratio of resistances (14)
Therefore, the loop gain of the Meyer amplifier can be described as
(15)
The denominator in (13) can be expressed as
(16) Next, as long as and are determined, the frequency re-sponse of the system-transfer function can be obtained. The original two poles ( and ) change to two complex poles ( and ), caused by the voltage feedback loop. The feed-back poles and can be calculated as
(17) The characteristic (16) can be changed to the following standard form:
(18)
where is the natural frequency and can be described as (19) and is the quality factor
(20)
There are various pole/zero locations for the frequency re-sponses of a feedback amplifier design. For example, the in-verse Chebyshev and Cauer responses have specific transmis-sion zeros which cannot be applied to our all-pole system in this paper. On the other hand, the Chebyshev response has a wider bandwidth but a worse group-delay flatness in a given gain-ripple condition while the Bessel–Thomson response has an equal-ripple delay response but a narrower gain bandwidth. Compared with the aforementioned choices, the Butterworth (maximally flat) response is a good tradeoff among the gain,
Fig. 4. Final topology of the modified Meyer wideband amplifier.
group-delay flatness, and the bandwidth. Moreover, to maxi-mize the speed of the overall two-stage amplifier system, the two separate poles ( and ) of each single-stage amplifier are set the same. Consequently, in order for the transfer function (18) to have the maximally flat response, the has to be 0.707. Since
equals to , the loop gain should be one
by (20) in this paper. Furthermore, as the value is lower than 0.707, for example, the two-pole Bessel–Thomson response, the bandwidth is sacrificed but the system is more stable since the two complex poles are far from the imaginary axis in the com-plex frequency domain. On the contrary, as the value is higher than 0.707, e.g., the two-pole Chebyshev response, the gain peak exists and is inclined to instability because the poles are close to the imaginary axis. Thus, a of 0.707 is a good choice for stability concerns.
C. Pole Locations of the Meyer Amplifier
Different from the Kukielka amplifier, the Meyer topology does not use the Cherry–Hopper structure for the basic am-plifier. A simple common-source amplifier definitely suffers from a poor frequency response; therefore, the speed of the second stage must be improved. In practical applications, the Darlington configuration can be used for the second stage in the Meyer amplifier. Fig. 4 shows the typical topology of the Meyer wideband amplifier including the source impedance and the loading impedance . As shown in Fig. 4, the Meyer amplifier consists of two source degenerative stages; the first stage is a common-source amplifier, and the second stage is a Darlington frequency doubler.
Assume that the Meyer amplifier is a two-pole system, the first pole is the dominant pole of the first-stage common-source amplifier, and the second pole is the dominant pole of the second-stage Darlington amplifier. The equivalent small-signal model used for solving the first pole of amplifier is shown in Fig. 5(a). Neglecting the biasing resistors and , the first pole can be obtained by the open-circuit time constant method [31]
(21)
where the is approximated
Fig. 5. Small-signal model for solving (a) the first pole and (b) the second pole.
Fig. 6. Small-signal model of the Darlington stage used to solve the frequency response.
while the resistor (the source impedance) is 50 and equals
(23)
where and .
The second pole can be obtained by the small-signal model shown in Fig. 5(b). Although the second stage is a Darlington pair, the dominant pole can be approximated by [30]
(24) The transconductance of the common-drain transistor is normally much smaller than that of the transistor in the Darlington configuration. Consequently, the capacitance of and can be neglected, and only the capacitance of and is taken into consideration. Therefore, the dominant pole of the Darlington stage is approximated by calculating the pole of the transistor . Some parameters must be found before calculating and .
Assuming that the resistor is small enough, which is usu-ally valid for the CMOS amplifiers, since the CMOS transistor is naturally much smaller, the resistors and can be determined using the small-signal model shown in Fig. 6. The resistor is the output resistance of the source node of the transistor , and it is approximated as
(25)
As shown in Fig. 6, the resistances can be calculated by changing the T-network ( , , and ) into the -network ( , , and ) [32]. Thus, the resistances are
(26)
Therefore, the and can be derived as [30]
(27)
where
(28) Because the source impedance and load impedance are both 50 , the of the amplifier is just the same as the voltage gain with a scaling factor of two by definition. Therefore, according to (21) and (24), can be determined once the and are obtained by (4) and (14)
(29)
According to [6], [7], and [9], we intentionally assume that all the S-parameters have the same poles ( and ); therefore, the S-parameters can be obtained by following:
(30)
(31) The zeros and can be obtained by solving the root of the denominator in (17), by changing into [26], [29], [30]. Similarly, the zeros and are the root of the denominator in (17), by changing into .
D. Simplified Design Equations and Design Methodology
Although the design equations of the dc values and pole lo-cations are found in the previous sections, it is still difficult to give the designer an approach to arrange the values of resistors
in order to optimize the gain, the input/output resistances, and the bandwidth. However, the first-order design methodology of the Meyer amplifier is very clear, based on some practical as-sumptions. As shown in (19), if the designer wants the largest
bandwidth, the must equal , and has to equal
one. If the loop gain is equal to one, then (32) is true, as shown at the bottom of the page. Therefore, the input and output resistances can be simplified into (33) and (34), as shown at the bottom of the page. As we can see, these equations are helpful for the designers to determine the values of the re-sistors when the gain-bandwidth product is maximized. In order to obtain the first-order design equation, some extra but reason-able assumptions must be made. Assuming that and are too small to achieve the unity loop gain, the term
and the term therefore has to be large enough. For the output impedance matching, the resistance in (34) can be described as
(35) Therefore, the resistance of the loading resistor must be near 100 for the perfect impedance matching. Under the same assumptions, (33) can be simplified to
(36) Using the results in (14) and (35), the voltage gain of the A-cir-cuit, as shown in Fig. 3(a), is
(37) Consequently, the first-order design flow for the maximum gain-bandwidth product is summarized as follows.
1) Assume , and thus, approximates 100
for the output impedance matching.
2) Design the pole locations by (21) and (24). The first pole must be equal to the second pole.
3) The values determined in design flow 2) have to be checked by (36) to perform the input impedance matching.
Fig. 7. (a) Noise contributions of the first stage. (b) Equivalent input-referred noise voltage/current of the first stage before feedback. (c) After feedback.
4) Recursively repeat processes 1)–3) until the optimized values of the S-parameters are found.
E. Noise Analysis
The demonstrated work is a cascade amplifier with dual feed-back loops. The noise contribution from the second stage can be neglected because the gain of the first stage is high enough dB [11]. Therefore, we can obtain the noise figure by simply calculating the total short-circuit output noise current spectral density from the first stage.
There are several key noise sources in the first stage, as shown in Fig. 7(a). The channel thermal noise current spectral den-sity of a MOSFET in the saturation region is modeled as
, where represents the
noise excess factor while is the zero-bias conductance. The parameter is a bias-dependent factor which equals 2/3 only for a long-channel device but it is much greater than 2/3 for a short-channel device [3], [33]. In addition, the gate resistance and the source degeneration resistance also need to be considered. Fortunately, the gate resistance of the MOSFET
(32)
(33) (34)
has a small effect on the gain performance, owing to the rela-tively high input impedance looking into the gate node.
The equivalent input-referred noise voltage and noise current of the first stage without feedback, as shown in Fig. 7(b), are written as follows [9], [35]:
(38) (39)
where is composed of and a parasitic
capacitance shunted to ground.
As shown in Fig. 7(c), since the shunt-type feedback resis-tance only affects the equivalent input-referred noise current but not the noise voltage [11], [35], still holds, and the equivalent input-referred noise current density can be modified as
(40) Consequently, the overall noise figure is given by
(41) Equation (41) gives a direct insight that the noise figure
increases when the feedback resistor
de-creases (i.e., the amount of feedback
increases) while the ideal noiseless feedback does not change the noise figure performance [35]. However, if is large enough, the noise performance is determined by the size and the bias of the transistor , not the resistor . Moreover, the noise arises at high frequencies due to the capacitance at the gate node.
F. Linearity
Fig. 8 is the block diagram of a nonlinear circuit with a feed-back loop. Equation (41) shows that, without considering the feedback loops, the linearity performance of a cascade ampli-fier usually dominates at the latter stage since the gain of the first stage is high. The mathematical expressions of the input/output relations of the nonlinear amplifier before/after feedback are de-scribed in (43) [36]. Although the linear gain degrades by a factor of after feedback, the third-order distortion can be much more reduced. As a consequence, the third-order
Fig. 8. Block diagram of a nonlinear circuit with a feedback loop.
output-referred intercept point can be predicted to have
an improvement of dB as described in (44).
(42) before f.b.
after f.b. (43)
after f.b. before f.b. (44)
Since the loop gain is set as unity for the But-terworth gain response of the proposed dual-feedback amplifier, the linearity performance does not improve much.
G. Comparisons of the Small-Signal Parameters in This Paper and Previous Works
Compared with the previous works [21], [22], and [26], the derived circuit parameters in this paper, such as the total ter-minal impedances and gain in this paper, are more general, be-cause the transistor need not be very large in our assump-tion. According to the work in [22], there is a major assumption that the current gain of the transistor is large enough (which is true for the bipolar transistors), and thus, both of the current and voltage feedback loops have an equal feedback loop gain with the closed-loop voltage gain. This assumption is employed to obtain the input and output impedance in [22]. Obviously, the higher current gain makes the bandwidth lower, since the gain-bandwidth product is a constant in the feedback amplifier design. However, the of the CMOS transistor is usually much smaller than that of the BJT transistor; hence, the current gain of MOS transistors may not be large enough, and this assumption is not suitable for the CMOS Meyer wideband amplifier.
In addition, as described by [21] and [22], the derived is approximated to
(45) The source degenerative resistor in (45) equals the source degeneration resistor in this paper. As shown in (45), the term is proportional to , which is based on the very huge loop gain of the voltage feedback path, and only the voltage feedback loop (consisting of resistors and ) is taken into consideration in this special case. Under this circumstance, the loop gain is greatly larger than one; therefore, the bandwidth is not optimized. The result of in (45) implies that only the voltage feedback loop dominates the dual feedback system; however, this is not true for analyzing the terminal impedance matching, particularly for CMOS technologies.
Fig. 9. Demonstrated 0.13-m CMOS Meyer wideband amplifier with its component values.
Consequently, the approaches of [21] and [22] for deter-mining the terminal impedances and the gain are based on the conflicting assumptions in a single circuit. This paper has not provided completely unique information but a general formula to determine the gain and input/output impedance.
III. CIRCUITDESIGN
In this section, a shunt–series series–shunt dual feedback wideband amplifier is demonstrated using 0.13- m CMOS tech-nology. The advanced 0.13- m CMOS technology is suitable to implement the high-performance RFICs. The circuit schematic and the designed values of the resistors are shown in Fig. 9. This Meyer amplifier is designed and implemented with CMOS technology to verify our theory because of its excellent cutoff frequency provided by the technology. This Meyer amplifier is designed without the source capacitive peaking technique in order to simplify the prediction of the pole locations.
A successful wideband amplifier must contain the following specifications: wide gain bandwidth and matching bandwidth, acceptable noise performance, and reasonable linearity. In order to achieve the goals, a proper dc biasing point and the device size should be decided first.
The dc biasing current and device size influence the noise and linearity performance. A larger dc with a smaller MOS device increase the , and thus, the gain and noise performance up-grade [6], [7], and [9]. However, a higher gain generally intro-duces a worse linearity performance, and a smaller device size causes more mismatches between devices, although the Meyer amplifier is single ended. A small device also may increase the gate resistance, and thus, the noise degrades [6], [7], and [9].
In this paper, some tradeoffs between noise performance, gain, bandwidth, and linearity are made. In order to extend the bandwidth up to 10 GHz with a dc gain larger than 16 dB, the linearity is traded a little bit. In addition, the first stage of the Meyer amplifier basically dominates the noise performance of the two-stage Meyer amplifier. The of the first-stage common-source amplifier shall be as high as possible. Unfor-tunately, a higher requires a larger dc, and thus, the voltage drop across resistor will be too large. As a result, we optimized the circuit elements, as shown in Fig. 9.
As shown in Fig. 9, a Darlington pair is employed in the second stage of the demonstrated Meyer amplifier. The wideband amplifier is implemented using 0.13- m CMOS
TABLE I
EQUIVALENTSMALL-SIGNALPARAMETERS OF THECMOS.
Fig. 10. Die photograph of the 0.13-m CMOS shunt–series series–shunt dual feedback amplifier.
technology. The minimum gate length of this technology is 0.13- m, and the maximum cutoff frequency is around 80 GHz. As shown in Fig. 9, the first-stage common-source transistor has a gate length of 0.13 m and 12 gate fingers. Similarly, gate length, finger number, and finger width are shown in Fig. 9. Some tradeoffs are made in order to optimize the circuit performance in terms of gain, port matching, noise figure, and linearity. The small-signal parameters of transistors
, , and are summarized in Table I. IV. MEASUREMENTRESULTS
The die photo of the 0.13- m CMOS wideband amplifier is shown in Fig. 10. The input RF ground–signal–ground (GSG) pads are on the left, while the output RF GSG pads are on the right. There are two dc bias pads on the top. As shown in Fig. 10, the chip consumes an area of m . The wideband amplifier only needs a chip area of m , and the probing pads, metal dummies, and poly dummies occupy the remaining 96% chip area. This is because the 0.13- m process requires dummies to perform the chemical–mechanical polishing process. The dc supply is 2.5 V, and the current consumption is 24 mA.
An HP8510 network analyzer, in conjunction with the cas-cade on-wafer probe station, is used to measure the S-param-eter performances. Fig. 11 shows the measured power gain of the fabricated wideband amplifier. In addition, the predicted
, by our theory, and the simulated are shown in the same figure for comparison. The Meyer amplifier has a 17-dB gain with a 10-GHz bandwidth.
Fig. 12 shows the measured, predicted, and simulated values while the measured, predicted, and simulated values are shown in Fig. 13. The measured input and output return losses
Fig. 11. Measured, predicted, and simulatedS values of the 0.13-m CMOS Meyer wideband amplifier.
Fig. 12. Measured, predicted, and simulatedS values of the 0.13-m CMOS Meyer wideband amplifier.
Fig. 13. Measured, predicted, and simulatedS values of the 0.13-m CMOS Meyer wideband amplifier.
are less than dB in the 3-dB gain bandwidth, respectively. Consequently, the predicted results and also the simulated results highly agree with the experimental S-parameter results. Fig. 14 shows the measured and simulated group delay of the Meyer wideband amplifier. Because the maximal flat response is chosen, the group delay is thus smooth, not like Chebyshev or Cauer responses.
The measured noise figure of the Meyer wideband amplifier is shown in Fig. 15. The measured noise figure is lower than 8.2 dB in the 3-dB gain bandwidth. The simulated and predicted noise performances are also shown in Fig. 15. Here, the predicted noise figure is calculated with the modification of . How-ever, the measured noise figure is, on average, 0.5 dB higher than
Fig. 14. Measured and simulated group delay of the 0.13-m CMOS Meyer wideband amplifier.
Fig. 15. Measured and simulated noise figure of the 0.13-m CMOS Meyer wideband amplifier.
Fig. 16. Measured power performance of the 0.13-m CMOS Meyer wideband amplifier.
our simulation results because the BSIM3 model only provides long-channel noise modeling parameters which are not suitable for the advanced CMOS technologies nowadays [33], [37], but the simulation still shows the same trend as the measured data. Compared to the reported CMOS wideband amplifiers [6], [7], and [9], the measured curve trend of the noise figure as a func-tion of the RF frequency is also the same. The noise figure in-creases rapidly as the RF frequency becomes higher.
Fig. 16 shows the measured and of the demon-strated Meyer wideband amplifier. The power performances de-grade as the operating frequency gets higher. The is dBm, and the is dBm when the frequency equals 10 GHz.
V. CONCLUSION
The first-order design methodology of the shunt–series se-ries–shunt double-feedback Meyer wideband amplifier has been developed. A 10-GHz wideband amplifier has been demon-strated using a 0.13- m CMOS technology. Experimental results highly agree with our theory, and the design tradeoffs are discussed. The small-signal S-parameters are obtained by the approach of pole-and-zero analysis; therefore, the insight of the Meyer wideband amplifier is given to the RF designers. The fabricated 0.13- m CMOS wideband amplifier has a 17-dB gain, a -dB input return loss, and a -dB output return loss with a 10-GHz bandwidth. The noise figure of the demonstrated amplifier is lower than 8.2 dB, while the and are better than and dBm, respectively, over the usable bandwidth.
ACKNOWLEDGMENT
The authors would like to thank the National Nano Device Laboratory for the RF measurement support, the National Chip Implementation Center for the chip-fabrication support, and Prof. S.-S. Lu for the idea of noise analysis.
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Tzung-Han Wu (S’06–M’08) was born in Taipei,
Taiwan, in 1979. He received the B.S. and M.S. degrees from the Department of Electrical En-gineering, National Chung-Hsing University, Taichung, Taiwan, in 2001 and 2003, respectively, and the Ph.D. degree from the Department of Communication Engineering, National Chiao Tung University, Hsinchu, Taiwan, in 2007. For his M.S. thesis, he worked on GaInP/GaAs HBTs, SiGe HBTs, and CMOS RFICs .
He is currently with the RFIC design team of Me-diaTek Inc., Hsinchu, Taiwan. His current research interests are in the areas of RFICs and analog ICs.
Dr. Wu is a member of Phi Tau Phi.
Jin-Siang Syu (S’09) was born in Taoyuan, Taiwan,
in 1984. He received the B.S. degree from the De-partment of Communication Engineering, National Chiao Tung University, Hsinchu, Taiwan, in 2006, where he is currently working toward the Ph.D. de-gree in electrical engineering.
His current research interests are in the areas of RFICs.
Mr. Syu is a member of Phi Tau Phi.
Chin-Chun Meng (M’02) received the B.S. degree
in electrical engineering from National Taiwan Uni-versity, Taipei, Taiwan, in 1985 and the Ph.D. de-gree in electrical engineering from University of Cal-ifornia, Los Angeles, in 1992.
He is currently a Full Professor with the Depart-ment of Electrical Engineering, National Chiao Tung University, Hsinchu, Taiwan. His current research in-terests are in the areas of RFIC and microwave and millimeter-wave integrated circuits.
