Design of 24-GHz 0.8-V 1.51-mW Coupling
Current-Mode Injection-Locked Frequency
Divider With Wide Locking Range
Zue-Der Huang, Chung-Yu Wu, Fellow, IEEE, and Bi-Chou Huang
Abstract—A 0.8-V CMOS coupling current-mode injec-tion-locked frequency divider (CCMILFD) with 19.5% locking range and a current-injection current-mode logic (CICML) fre-quency divider have been designed and fabricated using 0.13- m 1p8m CMOS technology. In the proposed CCMILFD, the cur-rent-mode technique to minimize the loss of input signals and the coupling circuit to enlarge the phase response have been designed to increase the locking range. The locking range of the fabricated CCMILFD is 4.1 GHz with a power consumption of 1.51 mW from a power supply of 0.8 V. In the proposed CICML frequency divider, the current-injection interface is applied to the current inputs to make the circuit operated at a higher frequency with low power consumption under a low voltage supply. The operation frequency of the fabricated CICML frequency divider can divide the frequency range from CCMILFD and consume 1.89 mW from a 0.8-V voltage supply. The chip core areas of the CCMILFD and CICML frequency divider without pads are 0.23 and 0.015 mm2, respectively. The proposed circuits can be operated in a low supply voltage with the advantages of a wider locking range, a higher operation frequency, and lower power consumption.
Index Terms—Coupling current-mode injection-locked
fre-quency divider (CCMILFD), current-injection current-mode logic (CICML) frequency divider, current-mode injection-locked frequency divider (CMILFD), current-mode logic (CML), injec-tion-locked frequency divider (ILFD).
I. INTRODUCTION
I
N RF frequency synthesizers, the high-speed frequency di-vider plays a critical role in various broadband and wireless applications. Recently, voltage-mode injection-locked fre-quency dividers (ILFDs) and direct injection-locked frefre-quency dividers (DILFDs) have been proposed in some of the research [1]–[4]. They have the advantages of low power consumption and high-frequency capability. However, both conventional ILFDs and DILFDs have the same problem of a narrow locking range. In order to solve this problem, enlarging the size of input transistors to generate a larger transconductance orManuscript received July 08, 2008; revised March 30, 2009. First published June 30, 2009; current version published August 12, 2009. This work was supported by the National Science Council (NSC), Taiwan, under Grant NSC 96-2221-E-009-179.
Z-D. Huang and C.-Y. Wu are with the Nanoelectronics and Giga-scale Systems Laboratory, Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: zuederhu.ee93g@nctu.edu.tw; cywu@alab.ee.nctu.edu.tw).
B.-C. Huang was with the Nanoelectronics and Gigascale Systems Labora-tory, Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan. He is now with Sunplus Media Inc, Hsinchu 30078, Taiwan (e-mail: cavaliere_stuart@hotmail.com).
Digital Object Identifier 10.1109/TMTT.2009.2025409
decreasing the quality factor of the resonant network in [1]–[7] are the most common solutions. With a larger , the injected voltage signal can be converted to a higher ac current to reach a larger locking range. However, an increase in the size of the tail transistor also increases the undesired parasitic capacitance, which becomes a leakage path for a high-frequency injection signal. It seriously degrades the ratio of the injection current to a dc current . This issue has been raised in pre-vious research [5] and the technique of shunt-peaking locking range enhancement has been proposed. Though there is some improvement in the locking range, the cost of chip area due to the extra inductors in the circuit is high.
Another method to extend the locking range is decreasing the effective quality factor of the resonant network. With the lower quality factor, the bandwidth is broadened and the signals with different frequencies are allowed to be evident at outputs. The CML-type ILFD with resistive loads proposed in [6] can have a lower quality factor and higher locking range when compared to a high- narrowband LC-tank ILFD. However, it needs more power for the circuit to guarantee the oscillation and maintain the output amplitude.
Recently, new techniques of utilizing coupling circuits be-tween dividers [7] and common-node injection [8] have been proposed to extend the locking range with low power consump-tion. However, the circuits presented in [7] are not suitable for low-voltage applications due to the cascode structure. In addi-tion, because the incident signals are voltage mode and injected from the tail transistors of the circuit, cannot be improved to further improve the locking range.
In the lower frequency band, the CML-type frequency divider is a good option because of its optimization of power, speed, and area consumption. However, the conventional CML divider is not suitable in a low-voltage operation when working at a high frequency. It suppresses the voltage headroom of the current source and makes evaluation pairs more difficult to change its logic states. As shown in [9], the operating frequency is propor-tional to the supply voltage. When the voltage supply is down below 1 V, the divider cannot accommodate a signal with a fre-quency over 10 GHz.
In order to solve the problems above, this paper proposes a current-mode divided-by-4 circuit, which is composed of two divider stages. The first stage is the coupling current-mode in-jection-locked frequency divider (CCMILFD) for higher fre-quency signals, and the second stage is the current-injection current-mode logic (CICML) frequency divider for lower fre-quency signals. The CCMILFD is composed of two
mode injection-locked frequency dividers (CMILFDs) and one coupling circuit. A new method of injecting the current signal directly into the divider instead of the voltage signal is adopted in the proposed CMILFD. This reduces the required voltage headroom and solves the problem of poor efficiency associated with voltage-to-current translation in the input stage. The cou-pling circuit is used to generate an extra phase to compensate for the loop phase shift. As a departure from previous work [7], the incident signals are injected into both the CMILFD stage and the coupling circuit stages. As a result, the locking range can be enhanced with low power consumption.
In the second divider, in order to solve the problems of the conventional CML divider, a CICML structure is introduced. The switching mechanism is determined by the current and not the voltage signal. The voltage headroom requirement and the switching response time for the devices can be reduced. It can make the entire circuit feasible to be operated in a high-fre-quency band and under a low supply voltage condition.
The proposed frequency current-mode divider has been de-signed and fabricated using 0.13- m CMOS technology. The fabricated chip has been measured to verify precisely its per-formance. The measurement results show that the CCMILFD has a locking range of 19.5% with a power consumption of 1.51 mW. The fabricated CICML divider can cover the full range of the first stage at a 0.8-V supply with a power consump-tion of 1.89-mW.
In Section II, the design concept and model of the proposed CCMILFD are presented. In Section III, the circuit design is described. The experimental results are presented in Section IV. Finally, a conclusion is given in Section V.
II. THEORETICALMODELANALYSIS
A. Locking Range of CCMILFD
Based on the concept of an LC ILFD [1], [10], [11], a new model for a CCMILFD is proposed, which is composed of two CMILFDs and one coupling circuit. The injection current signal is injected not only into the CMILFD itself, but also into the coupling circuit. The coupling circuit behaves as a mixer and is used to provide an extra phase to compensate for the phase shift caused by the input signal. The block diagram for the proposed CCMILFD model is shown in Fig. 1, where the phase differ-ences between and and between and are , the signals and are differential input signals, and are quadrature output voltages, is generated through the mixer by mixing and , is the output current of the coupling circuit by mixing and , and is the tank current in the LC tank.
When the double frequency current signals are injected into the divider, the input current is given by both the dc current of the mixer and the double frequency current. Since the injec-tion current flows into both the CMILFD and coupling circuit, each of them can be assumed to receive half of the injection current. As shown in Fig. 2, both and are generated through the mixers by modulating the injection current signals and dc currents with quadrature output voltages. After the LC tank, only the fundamental component of the output signal can be filtered out at the output nodes. Moreover, since the output
Fig. 1. Proposed model for CCMILFD.
Fig. 2. Half model of CCMILFD.
amplitude of CCMILFD is large and able to switch on and off the transistors abruptly, the and can be viewed as square waves for the mixer to simplify the analysis. The fundamental component of currents and can be derived as
high-order harmonics (1)
high-order harmonics (2) where the input frequency is twice the output frequency , is the amplitude of and , and and are the Fourier series of the square waves produced by and . The derivations are given in Appendix A.
In the proposed CCMILFD, is further added to in order to generate an extra phase shift for the tank current
. To derive an analytical expression of the locking range for CCMILFD, can be derived as
(3) where
(4)
(5)
In (4) and (5), is the injection current ratio and equal to . The derivations are given in Appendix B.
From (5), the phase response between and can be calculated as
(6)
With the assumption of sufficient close loop gain, the locking range is only determined by the close loop phase condition of the Barkhausen criteria. As derived in Appendix B, the single-sided locking range can be expressed as
(7) As may be seen from (7), the locking range depends on the injec-tion current ratio , tank quality factor , and the phase differ-ence between injection currents and output voltage , respectively. In particular, the locking range can be increased by increasing and reducing at the expense of power consump-tion for a given output amplitude.
From (7), it also shows that the optimal phase response for the locking range occurs when the phase is equal to . Under this condition, the locking range is a function of and and the final result is given by
(8)
In the conventional ILFD, the phase response and locking range are [1]
(9) (10)
Fig. 3. Circuit diagrams of: (a) CMILFD and (b) conventional ILFD.
When comparing (6) with (9), it can be seen that because of , the CCMILFD creates an extra phase shift of . In a conven-tional ILFD, the phase response is determined by . When is very small, the phase response becomes very small and the locking range is limited by the Barkhausen criteria in phase. However, in the proposed CCMILFD, it can provide an extra phase shift to prevent the circuit from the failure of the phase criteria, especially when is small. Furthermore, when com-paring (8) with (10), the locking range of the proposed circuit is much larger than that of a conventional ILFD.
In addition to the extra phase shift resulting from the proposed circuit, the output amplitude can also be improved to increase the loop gain. The tank current amplitude is enhanced by a factor of , as shown in (4). Due to an increase in the amplitude of , both the output level of can be higher and the loop gain of the entire loop can be increased. This can guarantee that the initial assumption of sufficient loop gain is sustained and the possibility of losing lock in the loop due to insufficient loop gain can be reduced.
III. CIRCUITREALIZATION ANDSIMULATIONRESULTS
The divide-by-4 circuit consists of a divide-by-2 CCMILFD and a divide-by-2 CICML frequency divider. The circuit real-ization and simulation results of the CMILFD, CCMILFD, and CICML divider are discussed in Sections III-A–D.
A. CMILFD
The circuit diagrams of the CMILFD and the conventional ILFD are shown in Fig. 3(a) and (b), respectively. In Fig. 3(a), the cross-coupled pair in the CMILFD can be viewed as a mixer to generate the output current by mixing and . To reduce the power loss on the input parasitic capacitance, a new incident interface for is proposed. As shown in Fig. 3(a),
is directly injected into the common source connection instead of through the gate of input transistor in Fig. 3(b). In Fig. 3(b), is generated by converting the voltage signal through the transconductance of . In order to have a larger , a higher is required. A higher is realized by increasing the dc current and transistor size of . However,
Fig. 4. Simulated comparison of the locking ranges between CMILFD and ILFD atQ = 7.
Fig. 5. Circuit diagram of CCMILFD.
it results in higher power consumption and larger signal loss through its parasitic capacitors and .
In the CMILFD, since the injection current is injected directly to , it is not related to the transconductance of . There-fore, the diode-connected transistor that behaves as a resis-tive load is used to provide the dc current and this allows for a reduction in the transistor size. When the size of becomes smaller, the parasitic capacitance and of node can be decreased to reduce the current signal loss. Since the signal loss is minimized, most input current can be injected into to the circuit and the injection current ratio can be improved. As a result, the locking range of the CMILFD can be increased.
In Fig. 4, the sensitivity curves of the CMILFD and the con-ventional ILFD are simulated by using Spectre RF with the same
LC tank and power supply voltage. From Fig. 4, it can be seen
that, at the same level of input power, the locking range of the CMILFD is much larger than that of the conventional ILFD. Therefore, the locking range can be improved using the pro-posed approach involving a current–mode interface.
B. CCMILFD
The circuit diagram of the CCMILFD is shown in Fig. 5, which has two CMILFDs and one coupling circuit. The cou-pling circuit is composed of and , as shown in Fig. 5. The resonant frequency of the circuit is determined by the two center-tapped inductors and and the parasitic ca-pacitances , , , and at the output modes.
Fig. 6. Simulated locking range versus.
Fig. 7. Simulated comparison of the locking range between CCMILFD and CMILFD.
and behave as two hard-limiting mixers to mix the quadrature output voltages and input current signals. The output current of the coupling circuit is combined with from the CMILFD to generate the tank current . The in-jection currents and are differential and each of them is fed into the CMILFD and the coupling circuit.
The simulation results of the locking range versus is simu-lated by using Spectre RF and is shown in Fig. 6. From Fig. 6, under the conditions of quality factor and , the simulated locking range of the CCMILFD is around 4.6 GHz at . The theoretical single-sided locking range is calcu-lated using (8) and then the double-sided locking range is mul-tiplied by a factor of 2. The simulation result correlates well with the theoretical locking range of the CCMILFD and is much larger than that of the conventional ILFD. As also seen from Fig. 6, the higher has a larger locking range. Fig. 7 shows the simulation results of input power plotted against input frequency in order to compare the sensitivities between the CCMILFD and the single CMILFD without the coupling circuit. It can be seen in Fig. 7 that with the same input power, the locking range of
Fig. 8. Circuit diagram of CICML divider.
the CCMILFD is much larger than that of the single CMILFD due to the existence of the coupling circuit.
Through the LC tank in the circuit, the signal of fundamental frequency can be taken from the output node, and its relative harmonics are suppressed by the LC filter. The simulated second and third harmonics can be suppressed to approximately 24 and 40 dB below the fundamental signal, respectively.
C. CICML Divider
The circuit diagram of the proposed CICML frequency divider is depicted in Fig. 8. , , , and are the PMOS loads for the divider. and
form the evaluation pairs, which can switch the logic state. and are the latch pairs to latch the logic. , , , and are the current sources.
When the conventional CML frequency divider [9] is oper-ated in a low voltage supply, the voltage swing in the internal nodes of the circuit is suppressed and makes the circuit diffi-cult to change the logic states of the evaluation pair and latch pair. The low gate voltage swing also makes the current source transistors difficult to be switched on and off. Therefore, the op-eration frequency is limited due to the low voltage supply.
The concept of a current-mode injection interface is applied to this circuit to solve the above problem. The input current sig-nals - and - are injected into the nodes and , re-spectively. The current signals instead of voltage signals are provided to switch on and off the evaluation pairs and latch pairs. When the current flows to the evaluation pair, it starts to determine the logic value. The result is transmitted to the latch pair and it is latched when the current flows to the latch pair. Since the logic is decided by the current switching mech-anism, the limitation on speed due to the response time of the current source transistors in the conventional CML divider [9] is reduced and the operating frequency can be much higher than that for a conventional CML frequency divider when in low-voltage operation. A comparison of high-frequency capa-bility between a conventional CML and the proposed CICML divider in simulation with a low voltage supply is shown in Fig. 9. The frequency of the CICML can be up to 14 GHz at a low supply voltage of 0.8 V, whereas that of CML divider is ap-proximately 10 GHz. In this study, the self-oscillation frequency of the CICML is designed at around 5.5 GHz. The sensitivity curve covers the desired frequency band, as shown in Fig. 10. From Fig. 10, the locking range at the input power of 10 dBm is around 7 GHz.
Fig. 9. Simulated comparison between classical CML and CICML dividers at V = 0:8 V.
Fig. 10. Simulated sensitivity curve of CICML divider.
D. Divide-by-4 Circuit
The overall circuit diagram of the diviby-4 divider is de-picted in Fig. 11. It consists of a CCMILFD divider, a CICML divider, and four open-drain output buffers for measurement.
Four current buffers for the inter stages are used to prop-agate the current signals in Fig. 11. The circuit diagram and its small-signal model of the current buffer are shown in Fig. 12(a) and (b), respectively. In Fig. 12(a), is a large blocking capacitor and can be viewed as a short circuit at high frequency. The gain of the current buffer can be derived from the small-signal model in Fig. 12(b) and simplified as
(11)
where and are the gate–drain and drain–bulk capaci-tance of , and are the gate–source and drain–bulk capacitance of , and is the transconductance of . The first pole of the circuit is at
Fig. 11. Circuit diagram of divide-by-4 divider.
Fig. 12. Current buffer. (a) Circuit diagram. (b) Small-signal model.
From the above equations, it can be seen that when both and are very small, the gain of the current buffer is close to 1 and the location of the first pole approaches to the unity gain frequency of . Therefore, it is a wideband-unity-gain current buffer and is very suitable to propagate the current signals in the current-mode applications.
For measurement purposes, an external signal source and a hybrid coupler were used to generate accurate differential input signals to measure the detailed locking range of the CCMILFD. In Fig. 11, the output signals and are the outputs of and after passing through open-drain buffers with off-chip bias-tee components, respectively. and are the outputs of and , respectively, in the divided-by-4 after the buffers.
IV. EXPERIMENTALRESULTS
The designed 24-GHz current-mode divide-by-4 circuit was fabricated using 0.13- m 1p8m CMOS technology. The chip
Fig. 13. Micrograph of chip.
micrograph of the designed dividers is shown in Fig. 13. The chip includes a CCMILFD, CICML frequency divider, output buffers, and testing pads. On-wafer probing measurement was adopted to verify the performance of the dividers. There are three ground–signal–ground–signal–ground (GSGSG) RF probes with a pitch of 100 m and one six-pin dc probe with a pitch of 150 m used to probe the chip. A hybrid coupler and an external signal source are applied to the generation of accurate differential input signals for the CCMILFD when measuring
Fig. 14. Measured spectrum of CCMILFD.
Fig. 15. Measured and simulated sensitivity curve of CCMILFD atV dd = 0:8 V.
its locking range. The losses from cables, probes, and adaptors were calibrated and compensated in the measurement results.
Owing to the layout parasitic and process variation of the fabricated chip, the measured frequency of circuits is slightly shifted down, as shown in Figs. 14 and 15. In Fig. 14, the measured spectrum of the output signals of the fabricated CCMILFD is shown. The output frequency is exactly divided by two from an input frequency of 21.8 GHz. In Fig. 15, the measured sensitivity curve of the CCMILFD is presented. The locking range at an input power of 10 dBm is from 19.3 to 23.4 GHz. The phase noise of CCMILFD is 123 dBc/Hz at 1-MHz frequency offset and the measurement result is depicted in Fig. 16. The core chip area of the CCMILFD is 0.36 0.64 mm . The power consumption of the CCMILFD is 1.51 mW with a 0.8-V power supply.
For the measurement of the second stage of the divider, be-cause there are no external sources designed to measure the CICML frequency divider, the precise sensitivity curve cannot be presented in this paper. However, the CICML can divide the signals from the CCMILFD completely to achieve our goal of dividing the input frequency by 4. The measured spectrum is
Fig. 16. Measured phase noise of CCMILFD.
Fig. 17. Measured spectrum of CICML divider.
Fig. 18. Measured phase noise of CICML divider.
shown in Fig. 17. The input frequency is 10.98 GHz from the CCMILFD and its output is located at 5.49 GHz. The power con-sumption is 1.89 mW with a 0.8-V power supply voltage. The phase noise of the CICML divider is 104 dBc/Hz at 1-MHz frequency offset and the measurement result is shown in Fig. 18. The measurement results are summarized in Table I for both the CCMILFD and CICML frequency divider. The perfor-mance comparisons among different CMOS ILFDs are given in Table II. As compared to other CMOS ILFDs, the proposed CCMILFD and CICML divider have the advantages of a lower
TABLE I
SUMMARY OFMEASUREMENTRESULTS FORCCMILFDANDCICML
*1 It was measured to cover all frequency ranges from the first stage divider. No external sources were designed to measure its exact performance. *2 The post-layout simulation results are simulated at the input power of 10 dBm.
voltage operation, significantly lower power consumption, and a wide locking range of 19.5% of the center frequency.
V. CONCLUSION
In this study, both a CCMILFD and CICML frequency divider are proposed and applied to the design of a CMOS divide-by-4 divider. In the proposed CCMILFD, a new coupling circuit to improve the phase response and a current-mode technique to minimize the loss of input signals are proposed to increase the locking range and to minimize power consumption. The theo-retical model analysis of the CCMILFD has been developed. In the proposed CICML frequency divider, a current-injection interface has also been proposed to increase the operation fre-quency under a low voltage supply. The divide-by-4 divider has been fabricated by using 0.13- m 1p8m CMOS technology. The measured locking range of the fabricated CCMILFD is about 19.5% of the center frequency and the entire output range of CCMILFD is covered by the CICML frequency divider. The power consumptions of the CCMILFD and CICML frequency divider are 1.51 and 1.89 mW with core chip areas of 0.23 and 0.015 mm , respectively. The measurement results have veri-fied that the proposed circuits can be operated on a low supply voltage of 0.8 V and provide the advantages of a wider locking range, a higher operation frequency, and a lower power con-sumption. Thus, the current-mode technique has great potential in applications of low-voltage RF systems in nanometer CMOS technologies.
APPENDIXA
In the design of CCMILFD, the quadrature outputs of CCMILFD are large signals. When the output amplitude is large compared with the switching voltage of the mixer, the mixer can be switched abruptly. In such case, and can be assumed as square waves for the mixer to simplify the analysis
of locking range. The Fourier series of the square waves can be expressed by the fundamental term and harmonics as [1]
(A.1)
(A.2) where is the phase difference between and , respec-tively. The injection currents and are differential and can be expressed as
(A.3) (A.4) where is the input frequency and is the amplitude of and .
and are generated by mixing the injection current signals in (A.3) and (A.4) and dc currents with the quadrature output voltages in (A.1) and (A.2). The results are given by
high-order harmonics (A.5)
high-order harmonics (A.6) where is the dc current of CMILFD and the coupling circuit, input frequency is equal to two times of output frequency .
APPENDIXB
The tank current is generated by adding the two currents and . From (A.5) and (A.6), we have
high-order harmonics (B.1) The high-order harmonics in (B.1) can be rejected by the LC tank in the circuit. Therefore, only fundamental terms are considered.
TABLE II
PERFORMANCECOMPARISONSAMONGDIFFERENTCMOS ILFDS
To obtain the phase of it, the fundamental terms of (B.1) can be rewritten in complex notation as
(B.2) where is the injection current ratio and equal to . From (B.2), and can be found as
(B.3)
(B.4)
Therefore, the phase response can be expressed as
It is known that, the impedance of an LC tank can be described as
(B.6)
where is the quality factor of the LC network. From (B.6), the phase of is
(B.7) To derive an analytical expression for the locking range, let us suppose that there is a sufficient loop gain for the close loop. In such a case, the locking range is only limited by the phase condition of the Barkhausen criteria. Using (B.5) and (B.7), the loop phase under the Barkhausen criteria can be shown as
(B.8) Substituting (B.5) and (B.7) into (B.8), we have
(B.9) The right-hand side can be rewritten as
(B.10) By solving (B.10), the single-sided locking range can be ex-pressed as
(B.11) When the phase is equal to , the circuit becomes a quadrature output system and the maximum locking range can be derived as
(B.12)
ACKNOWLEDGMENT
The authors would like to thank the National Chip Imple-mentation Center (CIC), National Applied Research Laborato-ries, Taiwan, for the fabrication of the testing chip. The authors would also like to thank Ansoft Taiwan for the support of their
computer-aided design (CAD) tool High Frequency Structure Simulator (HFSS).
REFERENCES
[1] A. Mazzanti, P. Uggetti, and F. Svelto, “Analysis and design of injec-tion-locked LC dividers for quadrature generation,” IEEE J. Solid-State
Circuits, vol. 39, no. 9, pp. 1425–1433, Sep. 2004.
[2] M. Tiebout, “A 50 GHz 0.13-m direct injection locked oscillator topology as low power frequency divider in CMOS,” in Proc. Eur.
Solid-State Circuits Conf., Sep. 2003, pp. 73–76.
[3] K. Yamamoto and M. Fujishima, “55 GHz CMOS frequency divider with 3.2 GHz locking range,” in Proc. Eur. Solid-State Circuits Conf., Sep. 2004, pp. 135–138.
[4] M. Tiebout, “A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider,” IEEE J. Solid-State
Cir-cuits, vol. 39, no. 7, pp. 1170–1174, Jul. 2004.
[5] H. Wu and A. Hajimiri, “A 19 GHz 0.5 mW 0.35m CMOS frequency divider with shunt-peaking locking-range enhancement,” in IEEE Int.
Solid-State Circuits Conf. Tech. Dig., Feb. 2001, pp. 412–413.
[6] U. Singh and M. M. Green, “High-frequency CML clock dividers in 0.13-m CMOS operating up to 38 GHz,” IEEE J. Solid-State Circuits, vol. 40, no. 8, pp. 1658–1661, Aug. 2005.
[7] T. Shibasaki, H. Tamura, K. Kanda, H. Yamaguchi, J. Ogawa, and T. Kuroda, “A 20-GHz injection-locked LC divider with a 25% locking range,” in IEEE VLSI Symp., Jun. 2006, pp. 170–171.
[8] T.-N. Luo, Y.-J. E. Chen, and D. Heo, “AV -band wide locking range CMOS frequency divider,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2008, pp. 563–566.
[9] C. Cao and K. O. Kenneth, “A power efficient 26-GHz 32:1 static frequency divider in 130-nm bulk CMOS,” IEEE Microw. Wireless
Compon. Lett., vol. 15, no. 11, pp. 721–723, Nov. 2006.
[10] R. L. Miller, “Fractional-frequency generators utilizing regenerative modulation,” Proc. IRE, vol. 27, no. 7, pp. 446–457, Jul. 1939. [11] S. Verma, H. R. Rategh, and T. H. Lee, “A unified model for
injection-locked frequency dividers,” IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 1015–1027, Jun. 2003.
[12] A. Mirzaei, M. E. Heidari, R. Bagheri, S. Chehrazi, and A. A. Abidi, “Injection-locked frequency dividers based on ring oscillators with op-timum injection for wide lock range,” in IEEE VLSI Symp., Jun. 2006, pp. 174–175.
[13] J. Lee and B. Razavi, “A 40 GHz frequency divider in 0.18-m CMOS technology,” in IEEE VLSI Symp., Jun. 2003, pp. 259–262.
[14] H. R. Rategh, H. Samavati, and T. H. Lee, “A CMOS frequency syn-thesizer with and injection-locked frequency divider for a 5-GHz wire-less LAN receiver,” IEEE J. Solid-State Circuits, vol. 35, no. 5, pp. 780–787, May 2000.
[15] H. R. Rategh and T. H. Lee, “Superharmonic injection-locked fre-quency dividers,” IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 813–821, Jun. 1999.
[16] A. Bonfanti, A. Tedesco, C. Samori, and A. L. Lacaita, “A 15-GHz broad-band 2 frequency divider in 0.13-m CMOS for quadrature gen-eration,” IEEE Microw. Wireless Compon. Lett., vol. 15, no. 11, pp. 724–726, Nov. 2005.
Zue-Der Huang was born in 1975. He received the
B.S. and degree in electronics engineering from Na-tional Chiao Tung University, Hsinchu, Taiwan, in 1998, the M.S. degree in electrical engineering from the University of Southern California, Los Angeles, in 2002, and is currently working toward the Ph.D degree in electronics engineering at National Chiao Tung University.
From 2002 to 2004, he was with the Atheros Taiwan Research and Development Center, as an Analog/Mixed-Mode Circuit Design Engineer. His research interests include low-voltage current-mode CMOS RF circuits, focusing on RF voltage-controlled oscillators (VCOs), high-frequency dividers, and frequency synthesizer designs.
Chung-Yu Wu (S’76–M’76–SM’96–F’98) was
born in 1950. He received the M.S. and Ph.D. degrees in electronics engineering from National Chiao Tung University, Hsinchu, Taiwan, in 1976 and 1980, respectively.
Since 1980, he has been a Consultant to high-tech industry and research organizations and has built up strong research collaborations with high-tech indus-tries. From 1980 to 1983, he was an Associate Pro-fessor with National Chiao Tung University. From 1984 to 1986, he was a Visiting Associate Professor with the Department of Electrical Engineering, Portland State University, Port-land, OR. Since 1987, he has been a Professor with National Chiao Tung Uni-versity. From 1991 to 1995, he served as the Director of the Division of Engi-neering and Applied Science, National Science Council, Taiwan. From 1996 to 1998, he was bestowed as the Centennial Honorary Chair Professor of National Chiao Tung University. He is currently the President and Chair Professor of National Chiao Tung University. In Summer 2002, he conducted postdoctoral research with the University of California at Berkeley. He has authored or coau-thored over 250 technical papers in international journals and conferences. He holds 19 patents, including nine U.S. patents. His research interests are
nano-electronics, biomedical devices and systems, neural vision sensors, RF circuits, and computer-aided design (CAD) and analysis.
Dr. Wu is a member of Eta Kappa Nu and Phi Tau Phi. He was a recipient of the 1998 IEEE Fellow Award and a 2000 Third Millennium Medal. He was also the recipient of numerous research awards presented by the Ministry of Education, National Science Council (NSC), and professional foundations in Taiwan.
Bi-Chou Huang was born in 1980. He received the
M.S. degree from National Chiao Tung University, Hsinchu, Taiwan, in 2007 (under the Industrial Technology Research and Development (R&D) Master Program on Integrated Circuit (IC) Design).
Since 2007, he has been with Sunplus Media Inc, Hsinchu, Taiwan. His major research interests are fo-cused on the design of CMOS RF integrated circuits and frequency synthesizers.
