Interleaved Current Sensorless Control for
Multiphase Boost-Type Switch-Mode
Rectifier With Phase-Shedding Operation
Hung-Chi Chen, Member, IEEE
Abstract—Multiphase boost-type switch-mode rectifiers (SMRs) are often used to improve the efficiency of ac–dc conver-sion. In particular, the light-load efficiency can be increased by turning off some phases (i.e., phase-shedding operation). To keep the number of feedback signals fixed regardless of the topology phase number N , the interleaved current sensorless control (ICSC) with consideration of the phase-shedding operation is proposed in this paper. In ICSC, no current sensing is needed, and only input and output voltages are sensed. To demonstrate the proposed ICSC, a two-phase boost-type SMR is established for test, and the proposed ICSC is implemented in a field-programmable-gate-array-based system. The provided simulation and experimental results show good performance of the proposed ICSC.
Index Terms—Interleaved control, phase-shedding operation.
I. INTRODUCTION
T
HE QUALIFIED ac/dc conversion must meet the func-tions of input current shaping and output voltage regula-tion. The boost-type switch-mode rectifier (SMR), including a diode rectifier and a boost converter, is often used to perform the qualified ac/dc conversion [1]–[3]. In addition, the multiloop control with the inner current loop and the outer voltage loop is often used to generate a switching signal in boost-type SMR. However, multiloop control needs to sense three signals: current signal and input and output voltage signals.Recently, to reduce the number of feedback signals, many voltage sensorless controls (VSCs) [4]–[7] and current sensor-less controls (CSCs) [8]–[10] for boost-type SMR have been proposed in the literature. The summary of feedback signals for sensorless controls is tabulated in Table I. It is clear that fewer feedback signals were used in sensorless control except the one in [9] due to the additional dc load current sensing.
Compared to the conventional boost-type SMRs, the mul-tiphase SMRs with an interleaved control scheme possess smaller current ripples and higher efficiency.
Manuscript received June 12, 2012; revised September 1, 2012, October 15, 2012, and December 5, 2012; accepted March 12, 2013. Date of publication April 5, 2013; date of current version August 9, 2013. This work was supported by the National Science Council of Taiwan under Contract NSC 101-2623-E-009-004-ET.
The author is with the Department of Electrical and Computer Engineering, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: hcchen@ cn.nctu.edu.tw).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2013.2257137
To meet efficiency requirements, more and more multiphase boost-type SMRs were used in fuel-cell power-generation sys-tems [11], plug-in electric vehicles [12], and photovoltaic ap-plications [13]. Therefore, more and more research has focused on multiphase boost-type SMRs.
The design of multiphase boost-type SMRs can be found in [13]–[15]. The interleaved phase shifter in variable-frequency pulsewidth modulation and the reduction technique of common-mode electromagnetic interference in the multi-phase boost-type SMRs had been proposed in [16] and in [17], respectively. The results in [18]–[21] show that the light-load system efficiency can also be significantly im-proved by shutting down some boost cells (i.e., phase-shedding operation).
The conventional multiloop control for boost-type SMR can be modified and extended to control an N -phase boost-type SMR by sensing all N inductor currents. Thus, the total number of the sensed signals is (N + 2). With the increasing of the topology phase number N , the complexity of the control configuration would also increase. Therefore, sensorless control applied to the N -phase boost-type SMR is important to simplify the controller design. However, no sensorless control was used for N -phase boost-type SMR in the publication.
After studying the sensorless controls for boost-type SMR in [4]–[10], it is found that all sensorless controls can be extended for the N -phase boost-type SMRs. From the number of feedback signals listed in Table I, it is noted that, for the case of extending VSC, the number of total sensed signals is N + 1, and this number also increases with the topology phase number N . However, for the case of extending CSC, the required number of sensing signals is fixed to two, regardless of the phase number N . It means that the case of extending CSC to N -phase boost-type SMR is better than the case of extending VSC.
By observing the three CSC methods in Table I, the voltage follower control in [8] is simple, but it suffers from the large current harmonics. The method in [9] senses an additional load current signal instead of the input current signal. Therefore, the aforementioned two methods are not suitable to be extended for the control of N -phase boost-type SMR.
The CSC in [10] is used to develop the proposed inter-leaved CSC (ICSC) which is the first sensorless control for
N -phase boost-type SMRs. In particular, the proposed ICSC
also considers phase-shedding operation and improves the volt-age transient response during phase-shedding operation.
TABLE I
SUMMARY OFFEEDBACKSIGNALS FORVARIOUSCONTROLS[4]–[10]
Fig. 1. Topology of an N -phase boost-type SMR.
This paper is organized as follows. Initially, the gate signal dispenser (GSD) is studied, and the average model of the
N -phase boost-type SMR with phase-shedding operation is
developed. Based on the developed model, ICSC is proposed. The analysis shows that the sinusoidal current waveform can be automatically generated by the proposed ICSC and the input current amplitude is independent of the active-phase number n. Finally, some simulated and experimental results are provided to show the performances of the proposed ICSC.
II. N -PHASEBOOST-TYPESMR
Fig. 1 shows the topology of an N -phase boost-type SMR, where integer N is the topology phase number (N > 1). It consists of a diode bridge rectifier, N boost converters with the identical inductors L, and the identical diodes D. It is noted that, in the digital control of the power electronic system, the turn-on time ton is given before the beginning of each
switching period Ts. Thus, by the GSD, all the gate signals
GS1, GS2, . . . , GSNcorresponding to the controllable switches
S1, S2, . . . , SN are generated from the same turn-on time
signal ton.
To model the behavior of the N -phase boost-type SMR, some assumptions are initially made: 1) All switches are as-sumed to operate at a fixed period Ts much smaller than the
line period T , and thus, the input voltage vsover one switching
period can be seen as a constant, and 2) a bulk capacitor Cdis
connected to the output dc voltage, and thus, the output voltage is assumed to be equal to its average value Vd. Therefore, the
steady-state output voltage is assumed to be equal to the voltage command Vd= Vd∗.
According to KCL, the total inductor current iLis the sum of
individual inductor currents
iL= N
k=1
iL,k. (1)
When the input voltage vs(t) = Vspsin(2πt/T ) =
Vspsin(ωt) is positive, the total inductor current iL is
equal to the input current is, and the current iL is equal to the
negative input current−is when the input voltage vsturns to
negative. Then, the input current can be represented in terms of the total inductor current iL
is(t) = sign (vs(t)) iL(t) = sign(sin ωt)iL(t) (2)
where sign(•) is the sign operator and sign(X) =
+1, when X ≥ 0
−1, when X < 0. (3)
To let all gate signals have the same turn-on time signal ton
and the duty ratio d, a GSD is proposed. It follows that all the duty ratios d1, d2, . . . , dNof gate signals are equal to each other
d1= d2=· · · = dN =
ton Ts
= d (4)
where dk is the duty ratio of boost converter #k.
A. GSD
At first, every switching period Ts can be divided into
N identical subperiods Ts = Ts/N . When the given turn-on
time ton is within the range (M− 1)Ts< ton≤ MTs (1≤
integer M ≤ N), the given turn-on time toncan be seen as the
sum of two terms tonand (M− 1)Ts
where toncan be seen as a partial turn-on time in the subperiod
Ts. Every gate signal with the same turn-on time ton can be
seen as the combinations of the following:
1) (M− 1) “turning-on” subperiods between sp#1 and
sp#(M− 1);
2) one “partial-on” subperiod sp#M with partial turn-on time ton;
3) (N− M) “turning-off” subperiods between sp#(M + 1) and sp#N subperiods.
The dispensing rules of the aforementioned subperiod series for the gate signal GS1 of boost converter #1 are obtained by
the series
GS1(t) ={sp#1, sp#2, . . . , sp#(N − 1), sp#N} . (6)
Then, the gate signal GS2 of converter #2 is obtained from
the shift-left operation of the gate signal GS1by one subperiod,
and it can be expressed as
GS2(t) ={sp#2, . . . , sp#(N − 1), sp#N, sp#1, } . (7)
Moreover, the gate signal GSk (1≤ integer k ≤ N) of the
boost converter #k is obtained from the shift-left operation of the gate signal GS1by (k− 1) subperiod
GSk(t) ={sp#k, sp#(k + 1), . . . , sp#N,
sp#1, . . . , sp#(k− 1)} . (8)
According to the aforementioned GSD rules, the illustrated gate signals and the resulting inductor currents for Ts< ton≤
2Ts(M = 2) and (N− 2)Ts< ton≤ (N − 1)Ts(M = N−
1) are illustrated in Fig. 2(a) and (b), respectively.
For the case of M = 2 in Fig. 2(a), all the gate signals can be seen as a combination of one “turning-on” subperiod, one “partial-on” subperiod, and (N− 2) “turning-off” subperiods. The signal GS2can be obtained by the shift-left operation of
GS1by one subperiod.
For the case of M = N− 1 in Fig. 2(b), all the gate sig-nals can be seen as a combination of (N− 2) “turning-on” subperiods, one “partial-on” subperiod, and one “turning-off” subperiod. The signal GSN can be obtained by the shift-left
operation of GS1by N subperiods.
The inductor currents and the total current are also plotted in Fig. 2 for comparison. It is clear that the total current ripple
Irip,N is much smaller than the individual inductor current
ripple.
B. Maximum Current Ripple
According to Fig. 2(a), there are always one “turning-on” switch, one “partial-on” switch with partial-on time ton=
ton− Ts, and (N− 2) “turning-off” switches at each subperiod
Tswhen Ts < ton≤ 2Ts.
Similarly, when (N− 2)Ts < ton≤ (N − 1)Ts, there are
always (N− 2) “turning-on” switches, one “partial-on” switch with partial turn-on time ton= ton− (N − 2)Ts, and one
“turning-off” switch at each subperiod, as shown in Fig. 2(b).
Fig. 2. Illustrated gate signals and the resulting inductor currents for (a) Ts< ton≤ 2Ts (M = 2) and (b) (N− 2) Ts< ton≤ (N −
1)Ts(M = N− 1).
Consequently, once the given turn-on time ton is within
the range (M− 1)Ts< ton≤ MTs (integer M ≤ N), there
are always (M− 2) “turning-on” switches, one “partial-on” switch, and (N − M) “turning-off” switches at each subperiod. In each boost converter, the inductor current rising rate is
|vs|/L when the switch is turning on. The inductor current
falling rate is (Vd∗− |vs|)/L when the switch is turning off.
Therefore, the rising rate m+L and the falling rate m−L of the total inductor current iLcan be expressed as
m+L = M|vs| L − (N − M) Vd∗− |vs| L = N|vs| L − (N − M) Vd∗ L (9) m−L= −(M − 1)|vs| L + (N− M + 1) Vd∗− |vs| L = −N|vs| L + (N− M + 1) Vd∗ L . (10)
Fig. 3. Inductor current ripple with various turn-on times ton.
Then, both multiplying the rising rate m+L by current rising time tonand multiplying the falling rate m−Lby current falling time (Ts− ton) can yield the total current ripple Irip,N
Irip,N = m+ton= m−(Ts− ton) . (11)
By substituting (9) and (10) into (11), the absolute value of the input rectified voltage|vs| would be equal to
|vs| =
(N− M + 1)Vd∗
N −
Vd∗ton
N Ts . (12)
From (9) and (12), the total current ripple Irip,N becomes Irip,N = Vd∗Ts N L ton Ts − ton Ts 2 . (13)
The value of tonthat produces the maximum current ripple Irip,N,maxoccurs when dIrip,N/dton= 0 which yields
1− 2 ton Ts = 0. (14)
Solving (14) for ton gives ton= 0.5Ts for the maximum current ripple Irip,N,max. The maximum current ripple becomes
Irip,N,max= Vd∗Ts
4N L. (15)
The maximum current ripple Irip,N,max in (15) decreases
with the increase of the topology phase number N . For com-parison, the maximum current ripple of the conventional boost-type SMR with an inductor L is Irip,1,max= Vd∗Ts/(4L).
The inductor current ripples for one-, two-, three-, and four-phase boost-type SMRs with various turn-on time signals ton
are plotted in Fig. 3. It is clear that the current ripples for phase number N > 1 are smaller than those of the conventional one-phase boost-type SMR (N = 1).
C. Average Current Model With Phase-Shedding Operation
To consider the practical condition, the nonzero inductor resistors rLare assumed. In addition, the effects of the voltage
drops across the diode bridge rectifier, the freewheeling diode, and the semiconductor switch are also considered.
The total voltage drop in the “switch-on” path is the sum of the voltage drops across the bridge rectifier and the semicon-ductor switch. The total voltage drop in the “switch-off” path is the sum of the voltage drops across the bridge rectifier and the freewheeling diode. Both voltage drops in the “switch-on” path
Fig. 4. Equivalent average model with the phase-shedding operation.
and the “switch-off” path are assumed to be equal to VF in this
section.
The KVL equation for boost converter #k (1≤ integer k ≤
N ) in terms of the average inductor current ¯iL,k within the
switching period Tsand the duty ratio d is
Ld¯iL,k
dt =|vs| − rL¯iL,k− VF− V
∗
d(1− dk). (16)
Due to the identical duty ratios d in (8), all boost cells have the same average voltage equation. In the phase-shedding operation, only n boost converters (1≤ integer n ≤ N) are active, and the number n can be changed according to the load condition to obtain higher efficiency.
By considering the phase-shedding operation, there are n KVL equations like (16) for the n active boost converters. Consequently, by summing n KVL equations and arranging the terms, the total average current ¯iLcan be obtained
L n d¯iL dt = Vsp| sin ωt| − rL n¯iL− VF − V ∗ d(1− d). (17)
Therefore, from (17), the behavior of the average total in-ductor current with the active-phase number n in an N -phase boost-type SMR can be equivalently modeled by a boost-type SMR, as shown in Fig. 4. The model includes a reduced in-ductance (L/n), a reduced inductor resistance (rL/n), and the
same conduction voltage VF. If the inductors are not identified,
the inductor current would not be balanced, and (17) can be modified by replacing (L/n) and (rL/n) with the equivalent
inductor Leqand the equivalent resistance req, respectively.
From (17), the behavior of the average total inductor current is obtained in terms of the circuit parameters and the integer n. Because the active-phase number n is not fixed and may change due to the phase-shedding operation, the following proposed ICSC also needs to compensate the effect of the change of the integer number n.
III. ICSC
The proposed ICSC can be seen as a proportional–integral (PI)-type voltage controller illustrated in Fig. 5(a), cascaded with a turning-on time generator shown in Fig. 5(b). It is obvious that only the input voltage vs and the output voltage
Vdare sensed.
After generating the voltage error signal εv, the original
phase shift signal θ is equal to the sum of the proportional term Kpεvand the integral term (KIεv/s) by the well-known
PI-type calculation. The original phase shift signal θ is limited to θmax(n) for the overload protection of the overall system.
Fig. 5. Proposed ICSC: (a) PI-type voltage controller and (b) turn-on time generator.
To provide the overload protection to each active boost cell, the final phase shift signal θis limited to the maximum value
θmaxbased on the capability of the individual boost cell. Thus, the θmaxcan be expressed as
θmax= n
Nθmax(n), 1≤ integer n ≤ N. (18)
To meet the efficiency requirement, the phase-shedding oper-ation is required, and the phase number n of active boost cells may change actively according to the load level. The change of the phase number n would contribute to the change of the equivalent model in Fig. 4. Thus, the consideration of the phase-shedding operation is very important for the control design.
A. With Consideration of Phase-Shedding Operation
In the proposed ICSC, an adjustable gain (N/n) is cascaded to the output of the voltage controller for the phase-shedding operation. From Fig. 5(a), the resulting phase shift signal θ becomes
θ= N
nθ, 1≤ integer n ≤ N. (19)
A unit-absolute sine signal| sin ωt|, in phase with the recti-fied input voltage|vs|, is generated by the zero-crossing
detec-tor (ZCD) and the unit-absolute sine generadetec-tor. After obtaining the original phase shift signal θ, a unit-absolute phase-shifted sine signal| sin(ωt − θ)| with the phase θleading the rectified input voltage|vs| is also generated by the corporation of ZCD
and the unit-absolute phase-shifted sine generator.
To compensate the effect of the equivalent inductor resistance (rL/n) and the conduction voltage VF, two compensated
sig-nals ton,iand ton,vin Fig. 5(b) are given by ton,i = θ Vsp Vd∗ rL ωL| sin ωt|Ts (20) ton,v = VF Vd∗Ts. (21)
The resulting turn-on time signal toncan be expressed as
ton= Ts− Ts
Vsp
Vd∗ |sin(ωt − θ
)| + t
on,i+ ton,v. (22)
Consequently, the duty ratio d = ton/Tscan be simplified to
d = 1−Vsp Vd∗ |sin(ωt − θ )| + θVsp Vd∗ rL ωL|sin(ωt)| + VF Vd∗. (23)
B. Independent Sinusoidal Current Amplitude
By substituting (18) and (23) into (17) and arranging the terms, the first-order differential equation for the average in-ductor current ¯iLcan be obtained
L n d¯iL dt = Vsp | sin ωt| −sin ωt−N θ n + θN ˆVs ωL |sin (ωt)| − ¯iL rL n. (24)
It is noted that the terms regarding VF in (24) are canceled out.
When the term N θ/n is small and near zero, the approximations sin(N θ/n)≈ (Nθ/n) and cos(Nθ/n) ≈ 1 can be used. Then, by using the common trigonometric identity sin (α− Nθ/n) = sin (α) cos (Nθ/n) − sin (Nθ/n) cos (α), sin(α− Nθ/n) can be approximated to (sin α − Nθ cos α/n). Thus, the first term| sin ωt| − | sin(ωt − Nθ/n)| in the right-hand side of (24) may be approximated to
| sin ωt| −sin ωt−N θ n ≈ N θn sign(sin ωt) cos ωt (25) where the sign operator sign(X) had been defined in (3).
By using the approximation in (25), the first-order differen-tial equation in (24) can be rewritten as
d¯iL dt ≈ N Vspθ L sign(sin ωt) cos ωt +rL L N Vspθ ωL | sin ωt| − ¯iL . (26)
It is noted that the active-phase number n is canceled out in (26). Since d| sin ωt|/dt = sign(sin ωt) cos ωt, substituting (27) into the second term of the right-hand side of (26) would make the second term zero. Thus, the following inductor current (27) must be the solution to (26) even when the inductor resistance rLis not neglected
¯iL≈
N Vspθ
ωL | sin ωt| = N Vspθ
ωL sign(sin ωt) sin ωt. (27)
From (2), the average input current ¯isbecomes
¯is(t)≈ θ
N Vsp
Fig. 6. Basic circuit of the power flow in the power system.
where Isp is the peak value of the input sinusoidal current
and it is independent of the active-phase number n. It means that the change of the active-phase number n (i.e., phase-shedding operation) has no effect on the sinusoidal input current amplitude Isp.
Due to the input voltage vs= Vspsin(ωt) and the in-phase
sinusoidal current isin (28), the average input power Pscan be
expressed as ¯ Ps= VspIsp 2 = N V2 sp 2ωL θ = V2 sp 2ω(L/N )θ. (29) It is clear that the change of active-phase number n (i.e., phase-shedding operation) has no effect on the average input power Ps, and thus, the phase-shedding operation has no effect
on the output dc voltage. That is, the proposed ICSC is suitable for the phase-shedding operation.
Additionally, the average input power Ps in (29) is
pro-portional to the controllable signal θ which also shows that the PI-type calculation is able to generate the adequate phase signal θ.
The proposed ICSC is based on [10], and the results in [10] are helpful to the sensitivity study of ICSC. The sensitivity study shows that, with parameter uncertainty, the PI-type con-troller is able to regulate the dc output voltage, but the current harmonics may be yielded.
C. Design of Controller Parameters
The transfer function between the output voltage perturbation ΔVd and the phase perturbation Δθ can be obtained from the
power balance between input power Ps, output power Pd, and
capacitor power PC[10].
From (29), the average input power Pswith the small
pertur-bation ΔPsbecomes ¯ Ps+ Δ ¯Ps= VspIsp 2 = N V2 sp 2ωL (θ + Δθ). (30) The output power Pdwith the small perturbation ΔPdcan be
represented by the output voltage perturbation ΔVd
Pd+ ΔPd= (Vd∗+ ΔVd)2 RL ≈ (Vd∗) 2 RL +2V ∗ dΔVd RL . (31) The small perturbation ΔPC of the capacitor power can be
represented by the output voltage perturbation ΔVd
ΔPC= d C 2 (Vd∗+ ΔVd)2 dt ≈ CV ∗ d dΔVd dt . (32) TABLE II
SIMULATEDCIRCUITPARAMETERS
Fig. 7. Simulated waveforms for (a) the boost-type SMR (N = 1) and (b) two-phase boost-type SMR (N = 2).
Fig. 8. Simulated responses during the change of active-phase number n from 2 to 1: (a) with the adjustable gain (N/n) and (b) without the adjustable gain (N/n).
The balance ΔPs= ΔPC+ ΔPdbetween the power
pertur-bations can yield the following small-signal transfer function
Gs(s) for the sinusoidal input current:
Gs(s) = ΔVd Δθ = N V2 sp 2CVd∗ωL 1 s +CRL2 = ks 1 s +CRL2 . (33)
Fig. 9. Implementation of proposed ICSC and a two-phase boost-type SMR.
Fig. 10. Experimental input voltage and current waveforms. (a) 600 W. (b) 400 W. (c) 200 W.
It is clear that the behavior of output voltage can be seen as a first-order model. Additionally, the change of the active-phase number n has no effect on the transfer function Gs(s). Thus,
the output voltage can be well regulated by including the simple PI-type controller in the proposed ICSC.
By setting the ratio of the proportional gain kP and the
integral gain kIto the pole of Gs(s)
kI
kP
= 2
CRL
TABLE III
INPUTCURRENTHARMONICS ANDTHEIRLIMITATIONS OFIEC 61000-3-2
the closed-loop transfer function of the output voltage Vd and
the output voltage command Vd∗can be obtained
Vd Vd∗ = kP N V2 sp 2CVd∗ωL s + kP N V2 sp 2CVd∗ωL . (35)
Equation (35) is a low-pass filter. To avoid the effect of the double-line-frequency voltage ripple in the output voltage, the cutoff frequency in (35) is chosen to be smaller than the 1/20 of the double line frequency (i.e., 0.1ω). Therefore, the proportional gain kPcan be obtained by
kP ≤
4CVd∗ω2L
5N V2
sp
. (36)
D. Viewpoint of Power Flow
From (25), the approximation| sin ωt| − | sin(ωt − Nθ/n)| can also be written as
| sin ωt| −sin ωt−N θ n ≈ N n (| sin ωt| − |sin(ωt − θ)|) . (37) By substituting the average inductor current ¯iL in (27) into
(24) to cancel the last term in (24), the average inductor voltage ¯
vL/nacross the inductor L/n in Fig. 4 can be expressed as
¯ vL n = L n d¯iL dt ≈ Vsp N n (| sin ωt| − |sin(ωt − θ)|) . (38)
Therefore, the average inductor voltage ¯vL/N can be
ex-pressed in terms of ¯vL/n ¯ vL N = n Nv¯Ln ≈ Vsp(| sin ωt| − |sin(ωt − θ)|) . (39)
Equation (39) can be equivalently plotted in Fig. 6, where a fixed inductance L/N is connected between two rectified sinusoidal voltages under phase-shedding operation. These two
voltages have identified magnitudes, but little phase difference
θ exists between them. It shows that phase-shedding operation
has no effect on the power flow (i.e., voltage regulation).
IV. SIMULATIONRESULTS
In this section, a series of the computer simulations is pro-vided to demonstrate the proposed ICSC. The nominal values and the circuit elements are listed in Table II. The simple PI-type loop with the antiwindup mechanism is used as the voltage controller to automatically adjust the controllable phase shift signal θ. According to (34) and (36), the controller parameters were chosen as kP = 0.0053 rad/V and kI = 0.0379 rad/V/s.
A. Steady-State Performance
The simulated waveforms for the conventional boost-type SMR (n = N = 1), as shown in Fig. 1, and the two-phase boost-type SMR (n = N = 2) were plotted in Fig. 7(a) and (b), respectively. In Fig. 1, a 150-Ω resistor is connected across the output voltage, and the average power is near 600 W. It is noted that, in this simulation, all their boost cells were active, and thus, n = N and θ = θin the proposed ICSC.
From Fig. 7(b), the output voltage Vd is well regulated to
the voltage command Vd∗= 300 V, and all their input currents
is were shaped to a sinusoidal waveform, in phase with the
input voltage vs. With the increase of phase number N , both
the input current ripple and total current harmonic distortion (THDi) decrease, although their individual inductor current
ripples were equal to each other. Therefore, the proposed ICSC is able to yield the desired power factor correction function without sensing any current.
B. Phase-Shedding Operation
When one phase (i.e., one boost converter) of a two-phase boost-type SMR (N = 2) turns down, the active-phase number
n changes from n = 2 to n = 1. It follows that the proposed
ICSC automatically changes the gain (N/n) from 2/2 (= 1) to 2/1 (= 2) and thus yields the final phase shift signal θ= 2θ. The simulated output voltage Vd, input current is, two inductor
currents iL,1 and iL,2, and two phase signals θ and θ of the
proposed ICSC were plotted in Fig. 8(a).
At the instant of the change of active-phase number n, the final phase signal θ suddenly rises to a double level, which contributes to a small voltage fluctuation in Fig. 8(a).
C. Without Adjustable Gain(N/n)
For comparison, the simulated responses without the pro-posed adjustable gain (N/n) in Fig. 5(a) are also plotted in Fig. 8(b). It is clear that the PI-type voltage controller must take some time to regulate the output voltage during the phase-shedding operation. However, the voltage dip in Fig. 8(b) is larger than that in Fig. 8(a). It follows that the proposed ICSC is able to perform well during the phase-shedding operation.
V. EXPERIMENTALRESULTS
The field-programmable gate array (FPGA)-based imple-mentation of the proposed ICSC and the two-phase boost-type SMR (N = 2) has been plotted in Fig. 9, where the circuit parameters have been tabulated in Table II. Since the GSD in Fig. 1 cannot be implemented in the general microcontroller chips, the proposed controller is implemented in an FPGA-based environment.
Because there is no A/D and no D/A function in a commer-cial FPGA XC3S200 chip, an external A/D converter is used to sense the output voltage, and some D/A converters are used to show the control variables of the implemented ICSC in the scope. In addition, a zero-crossing detecting circuit is used to detect the zero crossing of the input voltage.
A. Steady-State Performance
The input voltage and input current waveforms with var-ious load powers of 600, 400, and 200 W were plotted in Fig. 10(a)–(c), respectively. Due to the practical current-dependent conduction voltage drop, the experimental input current waveforms were not purely sinusoidal waveforms, as shown in the simulated waveforms in Fig. 7. However, from the measured input current harmonics and the listed class D harmonic limitations of IEC61000-3-2 in Table III, the har-monic performance of the proposed ICSC was able to meet the standards.
As plotted in Fig. 5, the circuit parameters rLand L are used
in the proposed ICSC, and therefore, the practical difference between the real circuit parameters and the nominal parame-ters may have an effect on the performance of ICSC. In the simulation environment, the control parameters were exactly equal to the circuit parameters, and thus, the simulated current waveforms were purely sinusoidal waveforms.
Therefore, current distortion due to parameter mismatch can be easily found in the experimental waveforms. However, the
Fig. 11. Experimental responses during the change of active-phase number n from 2 to 1: (a) with the adjustable gain (N/n) and (b) without the adjustable gain (N/n).
harmonic currents were acceptable to the standard limits in Table III.
B. Phase-Shedding Operation
At light load, more than one boost cell should be shut down to reduce the total switching loss and to increase the light-load efficiency. To work well under the phase-shedding operation, an adjustable gain (N/n) was included in the proposed ICSC.
Some experimental waveforms with and without an ad-justable gain (N/n) were plotted in Fig. 11(a) and (b), respec-tively. Like the simulation results, the proposed adjustable gain
(N/n) was able to reduce the voltage dip due to the phase-shedding operation.
VI. CONCLUSION
The ICSC has been proposed and implemented in this paper. A two-phase boost-type SMR had also been established in FPGA-based environment for evaluation. From the provided simulation and experimental results, the proposed ICSC is able to meet the harmonic standards and has near-zero voltage dip during the phase-shedding operation.
The proposed ICSC is the first method applied to the mul-tiphase boost-type SMR. In addition, the proposed ICSC only needs to sense two voltage signals without sensing any current signal. Thus, ICSC may become a competitive solution for the digital control of an N -phase boost-type SMR with phase-shedding operation.
ACKNOWLEDGMENT
The author would like to thank Zen-How Wu for his contri-butions on the original version of this paper.
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Hung-Chi Chen (M’06) was born in Taichung,
Taiwan, in June 1974. He received the B.S. and Ph.D. degrees from the Department of Electrical En-gineering, National Tsing Hua University, Hsinchu, Taiwan, in 1996 and 2001, respectively.
In October 2001, he became a Researcher with the Energy and Resources Laboratory, Industrial Tech-nology Research Institute, Hsinchu. Since August 2006, he has been with the Department of Electrical and Computer Engineering, National Chiao Tung University, Hsinchu, where he is currently an Asso-ciate Professor. His research interests include power electronics, power factor correction, inverter-fed motor control, and DSP/MCU/field-programmable-gate-array-based implementation of digital control.
