超薄化矽轉移與氧化矽接合在背照式感光元件上之應用

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Chapter 1 Introduction

1-1 General Background

Since 1960, chip functions can be improved by scaling down the volumes of the transistors and enhancing abilities of computing. Basically the progression of IC follows the Moore’s law, the roadmap by Intel is shown at Figure 1-1. But in the future, due to lithography and physical limitation, the development of scaling down will meet its bottleneck [1]. Not only the transistor itself gets the limitation but also the number of transistors keeps increasing on the single chip. The key to dominate IC performance is not the single transistor anymore. The global interconnect RC delay plays an important role [2]. Although it can reduce the transmission distance of some important areas by IC design, the total conduct distances are still the same. If the chip function needs to keep making progressing, efficiently reducing the total transmission distance of conduce lines is the essential factor.

Moreover, semiconductor industries always increase some unique processes and materials with requests of boosting IC function. So the

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heterogeneous integration is more important than usual, this concept is described at Figure 1-2. This kind of heterogeneous integration involves using different heterogeneous substrate materials and fabricating chips at different process temperatures. For integration of heterogeneous substrate materials, it is apparently to use new approaches to integrate them together. And for fabricating chips at different process temperatures, the latter process temperature needs to lower than the former one. Or it will exceed the thermal budget; this will restrict many transistors application like the waveguide transistors and the integration of traditional CMOS [3].

For the purpose of resolving the challenges and requirement above, the concepts of 3D Integration and 3D IC appear. The general idea of 3D IC technique is to change the traditional method placing IC at X and Y two dimensions. It enhances Z dimensions. The space of vertical stacking can be created. According to this concept, utilizing 3D technique can avoid the problems of traditional 2D IC keeping scaling down like the too long total conduct lines and the volume of chips is too large to get the frivolous requirements in Figure 1-3 [4].

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and chip stacking. And it use through–silicon via (TSV) to connect the thinning wafers and chips. It can convert the traditional 2D IC to 3D IC, and the benefits are shown in Figure 1-4.

Due to 3D IC can efficiently put the space to use and shorten the transmission distance of current signals, resistance-capacitance delay and total resistance can be reduced. Besides, owing to using these unique concepts of wafer bonding and chip stacking, fabrications of heterogeneous substrate materials can be separated at the beginning and stack together in the end. As mentioned above, the process temperatures and other circumstance requirements will restrict different ICs. But now these problems can be resolved by the method of stacking. Through optimized design of the chip stacking, the heterogeneous integration of 3D-IC can achieve future demand. Form SoC to SiP, 3D SiP and Terminal product 3D-IC as shown in Figure1-5. And TSV technology can provide more benefits which is shown as Figure 1-6. So 3D IC can provide a lot of advantages like multi-functions heterogeneous integration, high performance and low power dissipation under the requirements of frivolous demands and cost down.

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subvert traditional 2D IC. And it is closely linked to IC design, process techniques, instruments, packaging, testing methods, terminal product application and performance. These fields will dominate the maturity of 3D IC and its terminal products. In other words, 3D IC is a novel technology to integrate all fields. In all these fields, the process of 3D IC is the most essential factor [5].

3D IC brings many new process techniques such as wafer bonding, chip stacking, TSV fabrication and wafer thinning in Table I-I. Directions of stacking are face-to-face and face-to-back. And stacking approaches are die-to-die, die-to-wafer and wafer-to-wafer. In addition, 3D IC involves using different substrate materials, bonding materials and stuffing materials. So many derivative phenomena of material and physics need to be resolved. Under so many kinds of process selections, developing 3D IC with low cost, high yield and high performance is the most key point.

1-2 Motivation – Why do we need good oxide bonding quality and ultra-thin Si layer transfer?

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can be used on heterogeneous integration, reduce RC delay, small form factor, high performance, high throughput, low power consumption, hetero-integration and so on. It is the key of 3D IC technology. There are three major bonding methods which are metal-to-metal, polymer-to-polymer and oxide-to-oxide. Metal bonding has some advantages that other bonding techniques can’t achieve, such as it can be served as an extra metal layer, good heat dissipation, strong bonding strength, less cleanness requirement and it is softer than oxide. And also there are some metals materials used for bonding have been researched such as Cu, Ti, Sn, and Au [6-7]. These metals are often used in the semiconductor industry. But it major weakness is contaminant issue, so it can only use at BEOL (Back-End-Of-Line)

Polymer bonding can provide an opportunity to achieve a low temperature in photo-sensitive patterned technique suitable for MEMS, and 3D integration, packaging of VLSI for smaller size packaging. The advantages include low bonding temperature about below 300℃, an extremely high bonding strength, no metal ion contamination to device, excellent surface planarization property, and high plasticity to absorb the stress induced during bonding process. But such as above, polymer

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bonding also have contamination issue, and the process after bonding can`t be too high or transubstantiation will occur, then bonding strength will reduce and bring our reliability problem.

Oxide bonding can use at FEOL (front-end-of-line), compatible with now days semiconductor procedure and can bonding at relative low temperature. Semiconductor history keep following Moore`s Law so the device are is getting smaller, some problems appear and will getting more worse, such as leakage current, SCE (short channel effect), DIBL (drain induce barrier lower) and so forth. If there is a silicon substrate that cover ultra-thin silicon layer on oxide layer can reduce these problems which affect device performance and improve electric characteristic, but the main issue is that substrate source is too expensive compare to traditional silicon wafer. Because it has so many advantages, so how to develop an easy and fit in with economic concern is very important. The objectives of this research are to development of ultra-thin bulk silicon wafer thinning technology to improve the performance of the device on it. Because it has so many applications in semiconductor procedure, our goal is make backside illumination CMOS image sensor (BSI-CIS) on the substrate that we mentioned before. BSI-CIS is the next generation image

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sensor, it has many advantages compare to front side illumination CMOS image sensor (FSI-CIS), like reduce the noise signal beyond low illumination to lighten color distortion, enhance the sensor current, lower the effect of Young's interference so the sensor can further scaling and so on. In this age, most of cell phone are integrated with camera, and the evolution of cell phone is scaling beneath more function, under these proposes, BSI-CIS is essential to study.

Because the whole process is too hard to accomplish directly, so our goal is to accomplish the ultra-thin silicon substrate less than 4μm to developing BSI-CIS testing structure and accomplishing optical-electrical devices stacks with memory by 3D-IC bonding technology.

1-3 Organization of the Thesis

In Chapter 2, the major characteristics of all instruments which are used in this thesis will be literally introduced. In Chapter 3, we do chip level and wafer level oxide bonding parameter identification, procuring solution, oxide species choice, bonding temperature, given force magnitude, and given force type. In Chapter 4, develop procedure to do ultra-thin Si transfer on oxide, analysis H atoms diffuse result, inspect

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transferred silicon film quality. In Chapter 6, it will jump to conclusion for this thesis and make some suggestions. Also the future work for this study will be told.

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(Intel) Figure 1-1 Intel demonstrates roadmap

(Zycube, MNCN) Figure 1-2 3D-IC technology integrate different function chips by

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( LETI, EMC 2007) Figure 1-3 3D integration can improve performance compare with now

days 2D circuit

(Sematech and Gartner) Figure 1-4 Comparison between SoC, SiP, and 3D-IC

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(Yole development) Figure 1-5 Development of 3D-IC scheme

(Yole development) Figure 1-6 Comparison between wire bonding and TSV

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Category Detail terms

Stacking approaches

a. Die to Die (D2D) b. Die to Wafer (D2W) c. Wafer to Wafer (W2W)

Wafer selection a. Bulk (Si, Ge, GaAs, sapphire) b. SOI

Bonding method

a. Metal to Metal b. Oxide to Oxide c. Polymer to Polymer Direction of stacking a. Face to Face

b. Face to Back

Fabrication of TSV

a. Via first b. Via middle c. Via last

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Chapter 2 Experimental Instruments

2-1 Introduction

In this chapter, some of the equipment instruments are been described. They play an important role in our research. It is divided into two parts to do introduction: process instruments and material analysis instruments. All the samples studied in this work are prepared in Nano Facility Center (NFC), Center for Nanotechnology, Materials Science, and Microsystems (CNMSM) and National Nano Device Laboratories (NDL). Material analysis and microscope instruments are used to let us understand the related and the corresponding properties of the process condition. Transmission Electron Microscopy (TEM), Secondary Ion Mass Spectroscopy (SIMS), and scanning electron microscopy (SEM) are used. All the instruments will be introduced as follows. Figure 2-1 will summarize main flow of experimental procedures and material analyses.

2-2 Process Instruments

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Plasma enhanced chemical vapor deposition (PECVD) is usually used for the thin film deposition, and let material source change from gas state into plasma state to accelerate chemical reactions, the outlook of PECVD shows at Figure 2-2. The plasma is filled by process gases and generated by two electrodes which is bias with RF signal or DC signal. Processing plasmas are usually operated at the pressures of a few mTorr to a few Torr so the atoms and ions can reach enough meant free path. Ionized atoms or molecules are accelerated towards or leave the neighboring surface in sheath region (depends on their charges); therefore, all surfaces exposed to the plasma receive energetic ion bombardment. The potential across the sheath layer is typically only 10–20 V, the sheath layer is naturally generated because those electrons move faster than atoms or molecules, and can produce much higher sheath potential by modified reactor geometry. Ion bombardment is not only leaded to increases in density of the film but also remove contaminants that cover the sample surface to improving film quality. Ion bombardment density can be high enough to do planarization of thin film. Silicon dioxide can be deposited by using different silicon precursor gasses like dichlorosilane or silane and oxygen precursors. Silicon nitride can be

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formed by using silane and nitrogen or ammonia. Silicon Dioxide can also be deposited from a tetra-ethyl-ortho-silicate (TEOS) silicon precursor in oxygen or oxygen-argon plasma. Silicon dioxide deposited by High-density plasma can create a nearly hydrogen-free film with good conformality.

II. Bonder

This multipurpose bonding platform FINEPLACER Pico MA for advanced assembly can process bonding step where 5 μm accuracy shows at Figure 2-3. And it has high magnification to do alignment procedure. Advanced device packaging like assembly of MEMS, sensors, RFID, embedded components and surface mount photonics can be completed at this bonder. Also, it can execute precise die attach, flip chip bonding, LED bonding and chip to wafer (6”) bonding. Some high technologies have been adopted on this instrument such as thermo compression, thermo sonic, ultrasonic bonding, soldering (AuSn, C4, Indium), face-up/face-down assembly, flip chip on flex, chip on glass (CoG) and adhesive technologies (ACF/ACP/NCP). Some features are spotlighted like vision alignment system ensures placement accuracy 5μm, larger

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field of view and working area (6”), shifting module for bigger chip sizes, quick and easy setup of new applications, manual & motorized configuration available, hands-off operation in motorized configuration, high resolution video optics with fiber optic lighting, process observation and monitoring and independent substrate handling without tool change. Its software “ WinFlipChip” can advanced process recording and reporting functions, control of all connected process modules, advanced force control, drag & drop function to adjust profiles, options to capture pictures and movies and graphical user interface. The outlook of FINEPLACER Pico MA is shown in Figure 2-2.

III. Electronic Visions Co.501 (EV501)

EVG501 is a bonding tool that can achieve wafer level bonding shows at Figure 2-4, it is compatible with double side aligner, and then aligned wafer level bonding can be done. EVG501 supports a variety of bonding processes, such as anodic, glass frit, eutectic, diffusion, fusion, solder, and adhesive bonds, as well as other thermal processes, including high temperature bakes under a controlled atmosphere. Bonding with EVG501 don`t need adhesive glue, but heat two wafers and apply voltage

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to make them bonded. The theory of anodic bonding is that when heat wafers to 300℃~ 400℃, the metal ions in glass will move and have conductivity, if applied negative voltage at glass side, then metal ions will attracted by electrode to glass surface, the trapped negative ions at glass surface will form a electron layer with silicon surface nearby, it is thought that this electron layer will form ionic bond between silicon dioxide and silicon wafer, this bonding method often begin from the negative electrode to whole wafer.

EVG501 only support 4 inch wafer process and it is a semi-automatic machine that can heat or cool down upper and bottom wafers at the same time in the process, besides, EVG501 can provide a vacuum bonding environment to reach a better result.

IV. EVG520HE

The EVG520HE is a thermo-compress bonding tool shows at Figure 2-5; the theory of thermo-compress bonding is using pressure and heat to make the contact area between these two wafers distortion slightly to increase contact area. At a certain temperature that is high enough at the wafer surface, these wafers will going diffuse between each other to make

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the bonding process complete, but this method doesn`t require strict surface cleaning and high vacuum condition.

Because thermo-compress bonding process is simpler and cost less, it`s more attractive to industry and academic circle, more effort, investigation and development are put in. The most important parameter in this method is temperature cause wafer level bonding is used at 3D-IC electron device and application, so the bonding temperature should compatible with BEOL (back-end-of-line) to avoid to influence device performance and reliability.

EVG520HE is a single chamber tool that the maximum size of procedure wafer is 4 inch, besides it can handle 2 × 2 cm2 chip. It is a semi-automatic tool that can heat or cool upper and bottom wafer at the same time. And EVG520HE has individual ramp system to provide different process temperature to upper and bottom wafer, the maximum process temperature is 350℃, besides, it can provide compress force up to 12000Nt for 4 inch wafer to enhance bonding, this tool doesn`t require vacuum environment to achieve bonding successful.

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I. Scanning Electron Microscopy Hitachi S-4700I

SEM provide an express way to inspect the surface morphology and the cross section inspect image of the critical layer and the resistive switching thin films, are characterized by the scanning electron microscopy (SEM, Hitachi S-4700) with a resolution of 1.5 nm operated at 15 kV, the outlook of SEM shows at Figure 2-6. We need to coat a thin Pt layer on the samples before sent them into the chamber of SEM to enhance conductivity and get a high quality image. The accelerated electron beam, emitted from a cold-cathode electron gun with the extract voltage in the range from 0.5 kV to 30 kV, collides with DUT, and the secondary electrons originated within a few nanometers from the surface of the DTU are detected and rendered into a bright SEM image, which is as shown in Figure 2-11.

II. Optical Microscope

Light incident from the object will be enlarged by at least two optical system such as objective lens and eyepiece, First objective lens to produce a zoom in real image, and the human eye observe real image that enlarge by objective lens through the eyepiece. The optical microscope

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can replace the lens, so that the observer can replaced magnification. These objectives are generally placed on a rotating nosepiece, rotation of nosepiece can let different lens enter into the optical path reached the eyepiece. 1600 times became a light microscope magnification, the maximum limit, making the morphology of the application to be greatly restricted in many areas. If you want to observe smaller objects, you will require other methods such as electron microscopy.

III. P-10 Surface Profiler

The P-10 surface profiler is high-resolution equipment that obtain step height and micron roughness in various applications as shown in Figure 2-7. It is able to measure micron roughness with 1Å resolution over short distance over 60millimeter scanning. The P-10 provides the following features: measurement of vertical features ranging from under 100Å to approximately 0.3 mm with a vertical resolution of 1 or 25Å , a band pass filter allows the separation of intermediated wavelengths, minimizing the effects of environmental noise on measurements, precision mode, allowing precise location of small features, accommodation of samples up to 355 mm (wide), 63.5mm (thick), and

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IV. Transmission Electron Microscopy (TEM)

TEM is short for Transmission Electron Microscopy; it is a powerful tool for materials analysis. The outlook of TEM is shown at Figure 2-8. From 1930, first TEM is applied into industry, now days the resolution of TEM can reach 2~3Å with high working voltage about 1000KV. This nano scale inspection is really important and necessary to semiconductor development. The working principle of TEM is that electrons have wave form brought out by Louis de Broglie. The atomic resolution capability offers an express way to enter nano-scale world. It is commonly used to materials investigation on morphological observation, crystallographic study, and elemental identification. The field applications may cover a wide span from semiconductor, ceramics, metals, alloy, polymer, and bio-medical materials.

V. Scanning Acoustic Tomography (SAT)

SAT is the short for Scanning Acoustic Tomography and it`s also called SAM (Scanning Acoustic Microscope) shown at Figure 2-9. The

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working frequency of SAT is MHz level but not the ultrasonic cleaning that working at KHz frequency. The transmission depth depends on the raise of frequency to decrease, in normal condition, MHz level ultrasonic don`t bring cavitation effect so it can`t use at cleaning or agitate fragile device.

Because this characteristic that MHz ultrasonic don`t cause any damage to the sample and it can transmit a certain depth of solid or liquid material to inspect the structure, but ultrasonic is very sensitive to the air inside the test structure that air can interrupt the transmission of ultrasonic, so this can applied to check the completeness of chips.

Test structure are soaked in dielectric normally be water, by analyze the reflex of ultrasonic with software, we can check the line and layer inside the chip that can`t be seen by bare eye.

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Figure 2-1 Main flow of experimental procedures

(NDL) Figure 2-2 Outlook of plasma enhanced chemical vapor deposition

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(NFC) Figure 2-3 Outlook of flip chip bonder

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(CNMM) Figure 2-4 Outlook of (a) EVG 501 (b) the wafer holder of EVG 501

(CNMM) Figure 2-5 Outlook of EVG 501

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(Hitachi, University of California Riverside) Figure 2-6 Outlook of scanning electron microscopy

(NDL) Figure 2-7 Outlook of P-10 surface profiler and information panel

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(FEI) Figure 2-8 Outlook of Transmission Electron Microscope

(HITACHI) Figure 2-9 Outlook of scanning acoustic tomography (SAT)

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Chapter 3 3D IC Key Technology - Bonding

Bonding process is quite different from the traditional semiconductor processes. Traditional semiconductor manufacturing process direct make device on the wafer by multistep deposition, annealing, lithography, etching to accomplish two dimension device, so all devices are made on one substrate that limit the function of chip, now days we connect different function chip by package, but RC delay and interconnect wire is too long that will lower the performance of electronic system. Three-dimensional integrated circuits can solve these problems with bonding and TSV manufacture technique that can integrate different function chips by just stacking these chips and communicate by through silicon via (TSV) to reduce communication time efficiently, this is a potentially method to maintain Moore`s Law. With these reasons mention above, TSV etching, filling, bonding are the key of 3D-IC integration efficiently. In this paper, oxide bonding is observed for different species of oxide pairs, pre-curing solution choice, bonding temperature, given

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force type and magnitude. Among these oxide species, wet oxide is the prefer candidate that it has a better quality and uniformity, so wet oxide/oxide species as bonding material is our main point. Eventually, wet oxide/oxide species bonding and its bonding characteristics will be spotlighted not only in this chapter but also in the whole content.

3-2 Oxide bonding Mechanism

I. Induction

Silicon oxide layer is an important intermediate for wafer bonding because of its low contamination and the well-development of film deposition technique in semiconductor processes. Therefore, oxide bonding could be an attractive approach of layer transfer in 3D IC. Compared with polymer bonding, oxide bonding has advantages such as no ionic contaminant, excellent thermal property, compatible with CMOS process, and the capability for high density integration. However, the high process temperature is the major concern for application. It has been reported that PECVD oxide with lower process temperature could reduce thermal stress and wafer bow issue [8]. Accordingly, this paper investigates the relation between bonding quality with PECVD oxide,

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other species and parameters to provide the guidelines for low temperature oxide wafer bonding.

A successful oxide bonding has many key points to achieve the goal, such as cleanliness, wafer distortion, oxide film uniformity, etc. The basic explanation for each reason is as follows

(1) Cleanliness

The bonding process is first deposition a thin film as a bonding layer on both wafers, then two wafers contact with bonding layer to bonding layer direction and put force, heat on the wafers to induce diffusion or deteriorate or chemical reaction to make bonding layer stick to each other. Metal bonding or eutectic bonding or polymers bonding are all content contaminant in the view as FEOL, they can display a well bonding result in BEOL, because these bonding layer are softer compare with oxide bonding, and they are bonded by diffusion and deteriorate, so cleanliness isn`t as important as oxide bonding.

(2) Wafer distortion

Oxide can be a good bonding layer material, but the thickness of the oxide film is very important. Because oxide film has stress, so if the film is too thick, then wafer will distortion likes a bow, this will reduce contact

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area. For this reason, the bonding area is less correspond to whole flat wafers, the solution is deposit a proper thickness of oxide film to avoid wafer bow occur.

(3) Film uniformity

Film uniformity is one of the key point of bonding process, bad film uniformity will reduce contact area just like wafer bow that the reason mentioned above already. This situation often occurs at the PECVD tool, after deposition process the wafer appear Newton ring and this can be seen by bare eye in most of my experiment, the reason of Newton ring is that different thickness oxide film shows different color, and in my experiment, more close to the edge of the wafer appears more rings. We get a conjecture to why Newton ring often appear at PECVD tool but not furnace LPCVD, because the product of the chemical reaction falls on the wafer but not reaction at the wafer surface like furnace LPCVD, so if the chamber is not big enough or the chamber is not designed for 4 inches wafer specially, the uniformity problem will exist.

II. Mechanism of oxide bonding process

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Si-O-H + Si-O-H  Si-O-Si + H2O [9, 10]

When two oxide films contact, the OH groups tend to dissociate to form H2O molecules and leaves Si-O-Si bonds alone at the interface.

Figure 1 and 2 present the mechanism of oxide bonding. As the small parts of area bonded, the reaction will propagate into nearby area and finally the whole wafer if the surface flatness and wafer bow are adequate. The bonding results could be investigated clearly under the microscope with IR light source. The edge of bonded area, called bonding wave [11], will extend from wafer center to edge.

3-3 Experiment Procedure

P-type (100) 4-inch Si wafers were adopted in the study. 3000Å thick of different oxide species layers (as shown in Table 1) were deposited on bare silicon wafers after RCA clean (SPM + SC1 + SC2 + HF) for bonding quality evaluation. These wafers were then sawed into dies. The dies were dipped in H2O2 solution at 25℃ for different time, and then

bonded under 400℃, 100N for 50min. With the drop test (20cm height, 3 times) pre-assessment, the passed oxide species were further applied for

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wafer-level bonding. Table 1 summarizes the assessment results of different bonding oxide species with various H2O2 dipping time.

Based on the experiment results, PECVD SiH4 oxide is eliminate

from the next experiment and three kinds of oxide species, PECVD TEOS, LPCVD TEOS and thermal oxide, were chosen to perform wafer-level bonding. These wafers were first dipped in pre-treatment solutions H2O2 and modified cleaning solution (SC1 10min + SPM

10min)[9, 12] respectively, and then bonded with different approaches (EVG 501, EVG 520) with various bonding forces (10kN, 1kN, 40N), bonding temperature[13, 14], oxide species and pre-treatment solutions. After bonding, the wafers were investigated with SAT (scanning acoustic tomography) for bonding quality evaluation. Due to the poor uniformity at the wafer edge resulted from the Newton ring issue of PECVD facility; PECVD TEOS to PECVD TEOS bonding could not perform good bond quality, and LPCVD TEOS can`t provide a good bonding result, too. Therefore, only the combinations of PECVD TEOS to thermal oxide bonding and thermal oxide to thermal oxide bonding are adopted and discussed in the next chapter.

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3-4 Result and Discussion

From Table III-I, PECVD SiH4 oxide to PECVD SiH4 oxide bonding does not perform good bond results with different H2O2 dipping time.

Two possible reasons are suggested. One is PECVD SiH4 causes higher

stress than TEOS oxide, which induces larger wafer bow. The other is the oxide film property of PECVD SiH4 is more stiff than TEOS oxide,

which makes the inflexibility during bonding and results in poor bonding integrity.

Figure 3-3 and Figure 3-4 show the SAT image of wet oxide to wet oxide bonding under 250 ℃, 30 min, 40N with EVG 501 and wet oxide to PECVD TEOS bonding under 250 ℃, 30 min, 40N with EVG 501, respectively. These wafers are pre-curing by dipping with H2O2 20 min

and the dark area on SAT image at the wafer means this area are bonded and the bright area means not bonded. The wafer pairs in this set only change the parameter of oxide species in bonding process, from SAT images we can`t see difference obviously, but at the edge of Figure 3-4, the unbounded area is larger than Figure 3-3, which indicates PECVD oxide has a worse uniformity.

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oxide bonding under 250 ℃, 30 min, 40N with EVG 501 and wet oxide to wet oxide bonding under 250 ℃, 30 min, 1000N with EVG 520, respectively. These wafers are pre-curing by dipping with H2O2 20 min

and change the parameter of bonding force and given force type in bonding process, from SAT images we can`t see difference obviously, too. To be worth mentioning that EVG 501 is a bonding tool that applies force (range from 0N to 40N) by a pin and, but EVG 520 is a nanoprint tool which gives force (range from 0N to 12000N) by a circle pad.

Figure 3-6 and Figure 3-7 show the SAT image of wet oxide to wet oxide bonding under 250 ℃, 30 min, 40N with EVG 501 and wet oxide to wet oxide bonding under 250 ℃, 30 min, 1000N with EVG 520, respectively. These wafers are pre-curing by dipping with SC1 10 min + SPM 10 min and change the parameter of bonding force and given force type in bonding process, from SAT images we can`t see difference obviously, too. The results show that the bonding areas of both two bonding combinations are large and uniformly distributed, expect few bubble areas might be caused by particles or contamination. The bonding failure at the wafer edge is mainly resulted from the non-uniformity of PECVD TEOS deposition. Compare with Figure 3-3 and Figure 3-6, we

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found out that pre-treatment solution is extreme important in oxide bonding, this conclusion also fits in with the comparison of Figure 3-5 and Figure 3-7. Besides, the results in Figure 3-6 and Figure 3-7 show no big difference between the two conditions, which indicates both the two types of bonding tool could be used for oxide bonding, this result can also be discover in Figure 3-3 and Figure 3-5.

As aforementioned, the more hydroxyl bonds can induce better bonding strength. Therefore, the modified clean process was adopted before bonding to enhance the density of hydroxyl bond and remove particles on the oxide surface. The modified clean process includes two steps, one is SC1 treatment to remove ionic contaminant, and the other is SPM treatment to remove the organic contaminant and increase the density of hydroxyl bond. So modified clean is a better pre-treatment solution than H2O2.

Figure 3-8 and Figure 3-9 show the SAT image of wet oxide to LPCVD TEOS bonding under 250 ℃, 30 min, 40N with EVG 501 and wet oxide to LPCVD TEOS bonding under 400 ℃, 30 min, 40N with EVG 501, respectively. These wafers are pre-curing by modified clean and change the parameter of bonding temperature in bonding process,

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from SAT images we can`t see difference obviously that bonding quality is so terrible.

Figure 3-10 and Figure 3-11 show the SAT image of wet oxide to PECVD TEOS bonding under 250 ℃, 30 min, 40N with EVG 501 and wet oxide to PECVD TEOS bonding under 400 ℃, 30 min, 40N with EVG 501, respectively. These wafers are pre-curing by modified clean and change the parameter of bonding temperature in bonding process, from SAT images we can see that no significant difference between them and the bonding quality seems not bad, only a little area is not bonded. Compare with Figure 3-10 and Figure 3-11 , we found out that bonding temperature is not a main factor in oxide bonding, this conclusion also fits in with the comparison of Figure 3-8 and Figure 3-9; besides, compare with Figure 3-8 and Figure 3-10, it shows that wet oxide to LPCVD TEOS isn`t a good combination, this result also fits in with the comparison of Figure 3-9 and Figure 3-11.

Figure 3-12 and Figure 3-13 show the SAT image of wet oxide to LPCVD TEOS bonding under 250 ℃, 30 min, 1000N with EVG 520 and wet oxide to LPCVD TEOS bonding under 400 ℃, 30 min, 10KN with EVG 520, respectively. These wafers are pre-curing by modified clean

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and change the parameter of bonding force in bonding process, from SAT images we can see that higher bonding pressure has a larger bonding area, and this conclusion also fit in with the comparison between Figure 3-14 and Figure 3-15 which are bonded with condition wet oxide to PECVD TEOS bonding under 250 ℃, 30 min, 1000N with EVG 520 and wet oxide to PECVD TEOS bonding under 400 ℃, 30 min, 10KN with EVG 520, respectively.

3-5 Summary

The influence on bonding performance of various bonding parameters, including oxide species, bonding tool with different given force model, bonding temperature, and applied bonding force, was investigated in this study. Both the combinations of thermal oxide to PECVD TEOS bonding and thermal oxide to thermal oxide bonding can perform good bonding quality. The bonding performance has no big difference between the pin type and pad type of bonding tools. In addition, the larger bonding force can induce larger bonding area with better bonding performance, but the bonding temperature seems not an effective factor. The investigation results can provide the guidelines of low

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temperature oxide bonding for 3D integration and MEMS applications.

H2O2 dipping time

(min) Oxide species

20 10 5 1

PECVD TEOS to PECVD TEOS O O O O Thermal oxide to thermal oxide O O O O PECVD SiH4 to PECVD SiH4 X X X X

PECVD TEOS to thermal oxide O O O O Table III-I Oxide bonding combine with different dipping time verse

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Figure 3-1 Wafer bow schematic diagram [24]

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Figure 3-3 SAT image of wet oxide to wet oxide bonding under 40N, 250 ℃ and 30min by EVG 501 with H2O2 pre-treatment

Figure 3-4 SAT image of wet oxide to PECVD TEOS bonding under 40N, 250℃ and 30min by EVG 501 with H2O2 pre-treatment

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Figure 3-5 SAT image of wet oxide to wet oxide bonding under 40N, 250 ℃ and 30min by EVG 520 with H2O2 pre-treatment

Figure 3-6 SAT image of wet oxide to wet oxide bonding under 40N, 250 ℃ and 30min by EVG 501 with modified clean pre-treatment

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Figure 3-7 SAT image of wet oxide to wet oxide bonding under 40N, 250 ℃ and 30min by EVG 501 with modified clean pre-treatment

Figure 3-8 SAT image of wet oxide to LPCVD TEOS bonding under 40N, 250℃ and 30min by EVG 501 with modified clean pre-treatment

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Figure 3-10 SAT image of wet oxide to PECVD TEOS bonding under 40N, 250℃ and 30min by EVG 501 with modified clean pre-treatment

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Figure 3-13 SAT image of wet oxide to LPCVD TEOS bonding under 10KN, 250℃ and 30min by EVG 520 with modified clean pre-treatment

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Figure 3-15 SAT image of wet oxide to PECVD TEOS bonding under 10KN, 250℃ and 30min by EVG 520 with modified clean pre-treatment

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Chapter 4 Ultra-Thin Silicon Layer Transfer

Procedure

When the devices are scaling down to fill the bill of Moore`s law and reach the goal of higher speed, lower power, higher density, etc. But in the path of chasing this goal, the problem of scaling down appears, such as drain-induce-barrier-lowering (DIBL), nonzero sub threshold slope, on/off current speed too low, leakage, etc. But if use transferred silicon layer on buried oxide as the substrate, these problems can get alleviation, furthermore, it can increases the transistor switching speed of a transistor by burying a oxide layer below the source, base, and drain of the transistor to isolate it from the substrate, increase electron mobility, reduce power consumption, etc. These benefits mentioned above can provide a flexible design space to tradeoff between the power saving and device performance.

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We implant 1H ions into silicon substrate with a proper energy, the implant energy is expected to let these ions stop at the depth which we want to. These ions are trap in silicon substrate in 1H state, when this wafers are sent into anneal, these ions will diffuse, once 1H ions contact to each other, they will form H2 molecule and won`t dissociate into 1H

again, because it needs 435KJ/mol to return two 1H atoms, so H2

molecules won`t become two 1H ions and diffuse through dangling bond inside the silicon substrate. Implanted ions will present a Boltzmann distribution, but in the anneal process, ions in the middle of distribution will form H2 molecules more faster than the edge of the distribution tail,

once H2 exists, 1H ions concentration nearby will become lower, so outer

H ions will diffuse toward to the position that we expect implant depth, then more H2 molecule form, after a space will form lots of small cavities

at the implant depth layer. As soon as the amounts of H2 cavities reach a

certain quantity, the silicon will split by stress and leaves two parts [15, 16, 17] like Figure 4-1 shows. The concern of implant dose is that if it`s too low, then the silicon won`t split or anneal temperature must higher, this condition lead to it will not split; if it`s higher than 2.0 × 1017 ions/cm2[18, 19], after anneal process, blister will appear on the wafer

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surface like Figure 4-2 shows, then the process can`t continue cause unflatten surface[20].

4-3 Experimental Procedure

Standard clean for wafers are performed before implant 1H to wafer A with two recipes, implant energy 370KeV/expect depth 4μm/dosage 9E16/implant species 1H+ and implant energy 120KeV/expect depth 1μm/dosage 6E16/implant species 1H+[19], The depth corresponding energy is determined by TRIM[15]. Trim is software written by James F. Ziegler which is a powerful tool for implantation process. After implantation, implanted wafers are sent to do SIMS (Secondary Ion Mass Spectrometry) to identify doping profile, and then deposit 3000Å TEOS on the silicon substrate A and 3000Å wet oxide on the other silicon substrate B. Then dicing wafer A and B into chips A and B, chips A are larger than chips B, the reason why we care about chips sizes is that these chips need to dip in HF so we coat with adhesive on it to prevent is from debond in the coming procedure. And then dip these two chips A and B in SC1 10 min then SPM 10 min, after dip pre-curing solutions is bonding process, wafer A and B are bonded with oxide to oxide. Oxide layers

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from wafer A and B are bonded together and form one complete oxide layer as buried oxide layer, and then this bonded wafer pair is dipped in HF for 12 hour to etch silicon defect[23], this addition curing can lower the following up anneal temperature. This chip pair is sent to furnace to do anneal procedure at 400℃ for 9 hours and do SIMS analysis again after annealing to check profile. As the mechanism that mentioned above, H2 cavities form at the highest doping concentration position, once the

number of the cavities surpasses tipping point, wafer A will split into two parts, because we do implant and deposit from the front side of wafer A, so the front side of wafer A will split from the highest H2 concentration

and stick to wafer B, the rest part of wafer A can do next silicon film transfer process as implant side. These chips are polished and then sent to FIB (Focus Ion Beam) to prepare TEM samples, use TEM we can see the whole structure precisely and check if there are defects exist in the transferred silicon film or not.

4-4 Results and Discussion

I. SIMS analysis

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doping concentration, depth and dosage is fitting in with our expectation or not. We do SIMS analysis after implantation with recipes, each recipe is implant energy 370KeV/expect depth 4μm/dosage 9E16/implant species 1H+, implant energy 120KeV/expect depth 1μm/dosage 6E16/implant species 1H+ and the SIMS data are show at Figure 4-3 and Figure 4-4, respectively. The results are very close to expectation which is confirmed by SIMS data. And we do SIMS again after anneal procedure to check the concentration of H atoms which shows in Figure 4-6 and 4-7 for 4μm implantation and the direction of SIMS data are define by Figure 4-5. The result shows that the highest H atom concentration doesn`t changes its position in depth verse peak of doping concentration diagram after anneal procedure. We can observe obviously that silicon split at the highest doping concentration position.

II. SEM

After oxide film deposited, bonding procedure, anneal, these chips are sent to SEM to check oxide thickness and whole structure, but it can`t be seen obviously in SEM. Just take some picture that can barely recognize the thickness of oxide layer, these picture shows at Figure 4-8.

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Figure 4-9 shows that transferred silicon surface spread hill like shape roughness and we give it a conjecture that it relates to defect shape which is seen by TEM.

III. TEM

In TEM, we can see every layer about their thickness, oxide bonding interface, transferred silicon defect. We had sent chips that implanted 1μm after bonding procedure and after silicon split to check the difference. Figure 4-10 shows the whole structure of the chip before split and the thickness of each layer is shown in Figure 4-11, the white area in oxide film is not oxide interface but the scar in sample preparation for TEM, so we will focus on the left side of the sample which is shown in Figure 4-10. There is nearly no oxide interface can be seen in TEM show at Figure 4-12 which indicate that oxide bonding quality with this procuring method is pretty good. Figure 4-13 (a) and (b) show the defects contain area, these defect are mainly line defects which form triangle appearance, which thought to be relative with Figure 4-9. Figure 4-14 shows that these defects length range is about 10 ~ 20 nm, and we had checked if defects exist at the bottom of transferred silicon film, the

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position and result are shown at Figure 15 (a) and (b), respectively, which prove that there is no defect existence. The other chip is already transferred, Figure 4-16 is the whole structure diagram and the thickness of each layer are shown at Figure 4-17, oxide bonding interface was confirmed at Figure 4-18 which indicate perfect oxide bonding result. Transferred silicon film doesn`t exist defect no meter at top of the film proved by Figure 4-19 (a) and (b), but in the chip after bonding can observe defects at the end of implant path. Defects don`t exist at the transferred silicon film, the reason is that it already dipped in HF for defect etch and this chip is annealed, so it contains no defect. But defect exist at the chips just after bonding procedure, there are two mechanism about defect produce, because when the implant ions are just enter silicon, these ions are slow down by electron stopping power (ion energy > 10eV), when electron stopping power domain, ions collide with electrons of the lattice atoms, incident ion path is almost unchanged, energy transfer is very small and crystal structure damage can negligible. But when nuclear stopping power domain (ion energy < 10eV), then ions collide with atomic nucleus of the lattice atoms, scattering occurs significantly and ion path will change randomly so ions causes crystal structure damage near

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the depth of 1μm. From the mechanism described above, we expect defects exist at the end of implant path, and in TEM images we can see defects at the specific position that we expect.

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Figure 4-1 Ideal split off scheme

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Figure 4-3 Implant depth 370KeV(4μm)/9E16/1H+

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Figure 4-5 SIMS data direction definition

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Figure 4-7 After silicon split after 400 ℃ anneal

Transferred Si layer PECVD TEOS

Wet oxide

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Figure 4-8 (a) (b) Oxide thickness confirm by SEM

Figure 4-9 After silicon split surface

(b)

PECVD TEOS Wet oxide Transferred Si layer

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Figure 4-10 Before silicon split cross section overview

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Figure 4-12 Before silicon split oxide bonding interface

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Figure 4-13 Before silicon split (a) silicon defect position (b) silicon defect

(b)

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Figure 4-14 (a) (b)Silicon defects before annealing process

(a) (b)

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Figure 4-15 Before silicon split (a) defect check position (b) interface between silicon and oxide

Figure 4-16 After silicon split overview

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Figure 4-17 After silicon split thickness check

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Figure 4-19 After silicon split (a) defect check position (b) defect check

(a)

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Chapter 5 Conclusions and Future Work

5-1 Conclusions

Three-dimensional integrated circuit is a new technology that provides significant performance and improves functional benefits such as high device integration density, interconnectivity, heterogeneous integration technologies, and a reduction in length of the long global wires. In this thesis, oxide bonding parameter, like bonding temperature, given force magnitudes, given force types, procuring solution are all demonstrated. Dip in SC1 10 min + SPM 10 min procuring solution can improve bonding area obviously, choose PECVD TEOS + wet oxide match can have a good bonding result and the more given bonding force will reach a larger bonding area.

Then choose 5.0 × 1016 ions/cm2 dosage with 120KeV implant energy combine HF dip 9 hours and anneal at 400℃, we can get a perfect ultra-thin silicon layer transfer that silicon film is only 1μm and this film is single crystal with surface only exist small roughness and oxide bonding quality is so good that oxide bonding interface can`t be examine

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on TEM, this ultra-thin silicon film transfer process can continue to accomplish a good performance device.

5-2 Future work

Continue process to achieve wafer-level ultra-thin silicon film transfer and keep put the effort on lower bonding and anneal temperature to 250℃ or reach a thinner silicon film on oxide layer, then analysis about thin film stress, mechanical structure strength and lattice inspect. After thin film silicon transfer procedure is mature, design a compatible process to integrate BSI-CIS on it. If this terminal purpose can be reached, then this easy and convenient bonding technology will have a lot of applications for 3D-IC.

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