inductance–capacitance network at drain is drawn to further suppress the noise, and a very low noise level is achieved. The pro-posed LNA is implemented by the Taiwan Semiconductor Manu-facturing Company 0.18-μm CMOS technology. Measured results show that the noise figure is 2.5–4.7 dB from 3.1 to 10.6 GHz, which may be the best result among previous reports in the 0.18-μm CMOS 3.1- to 10.6-GHz ultrawideband LNA. The power gain is 10.9–13.9 dB from 3.1 to 10.6 GHz. The input return loss is below−9.4 dB from 3.1 to 15 GHz. It consumes 14.4 mW from a 1.4-V supply voltage and occupies an area of only 0.46 mm2.
Index Terms—Broadband, complimentary metal–oxide– semiconductor (CMOS) low-noise amplifier (LNA), feedback, ultrawideband (UWB).
I. INTRODUCTION
I
N RECENT YEARS, ultrawideband (UWB) systems have attracted more interest due to their capability of transmitting data with a high data rate and low power consumption. For the IEEE 802.15.3a standard, the allocated band of UWB is between the 3.1- and 10.6-GHz frequency range [1]. The wideband low-noise amplifier (LNA) for a wireless front-end RF receiver is a critical block, which needs to fulfill several requirements, such as broadband input matching, sufficient power gain, low-noise figure (NF), etc.Several major types of UWB CMOS LNAs have been re-ported in literature [1]–[9]. The distributed amplifier (DA) provides good wideband input matching and flat gain; however, it consumes more power and chip area. The resistive shunt feedback is a well-known wideband technique, which provides wideband input matching but increases NF due to the local feedback [1]. The inductive degeneration can only provide narrow-band input matching, but it can achieve better noise performance; therefore, it needs other technology to extend the bandwidth [3]. Another technology is to use a multistage input filter for broadband input matching [4]. However, the
Manuscript received August 2, 2009; revised December 10, 2009; accepted February 11, 2010. Date of publication June 28, 2010; date of current version August 13, 2010. This work was supported in part by the National Science Council, R.O.C., under Contract NSC97-2219-E-009-012. This paper was recommended by Associate Editor A. I. Karsilayan.
The authors are with the Department of Communication Engineering, Na-tional Chiao Tung University, Hsinchu 30050, Taiwan (e-mail: hkc.cm96g@ nctu.edu.tw).
Digital Object Identifier 10.1109/TCSII.2010.2050943
Fig. 1. Proposed UWB LNA.
input filter insertion loss degrades the LNA’s NF, and a large chip area is unavoidable. According to the points discussed above, the parallel resistance–capacitance shunt feedback with a source inductance is proposed to obtain the broadband input matching and to reduce the noise level effectively. The parallel
LC network at drain is drawn to further suppress the
high-frequency noise, and a low noise level is achieved. Moreover, the input stage in cascade with cascode topology can provide broadband power gain (3.1–10.6 GHz) with both relatively low power consumption and a small chip area.
II. CIRCUITDESIGN ANDANALYSIS
The proposed wide-band LNA is depicted in Fig. 1. It con-sists of an input stage, a cascode second stage, and an output buffer. The output buffer is a simple source follower that is added for measurement purposes only.
A. Input Stage
The input stage provides the broadband power and noise matching. The input impedance Zin looking into the gate of transistor M1(as seen in Fig. 1) is
Zin = gm1 LS1 Cgs1 + sLS1+ 1 sCgs1 (1) where gm1 and Cgs1 are the transconductance and the
gate-to-source capacitance of the transistor M1, respectively. From 1549-7747/$26.00 © 2010 IEEE
Fig. 2. (a) Miller equivalent circuit. (b) Series converted to parallel of the equivalent circuit.
Fig. 1, using Miller’s theorem to convert the input stage to that shown in Fig. 2(a), we obtain RF = RF/(1 + Av) and CF = CF(1 + Av), where Avis the voltage gain from gate to
drain and is equal to
Av=
(sCgs1Zin − gm1ZF) ZL sCgs1Zin (ZF+ ZL)
. (2)
Equation (1) presents a series-RLC network. For simplicity, the series combination of R, L, and C can be converted to the equivalent parallel circuit shown in Fig. 2(b),1 where Rp, Lp,
and Cpcan be derived as Rp= R2+ (ωL− 1/ωC)2 R (3) Lp= R2+ (ωL− 1/ωC)2 ω2L (4) Cp= 1 ω2C (R2+ (ωL− 1/ωC)2). (5) Thus, the input impedance Zinis approximated as
Zin= (RFRp) sLp 1 s (CF + Cp) . (6)
Referring to (6), we can make the following observations. First, the form of (6) clearly shows that the input impedance is purely resistive at resonance. Thus, a proper choice of gm1, LS1, RF, and CF yields a 50-Ω part. In (6), CF makes
inductive reactance of Zin closer to capacitive reactance. In
other words, CF makes the imaginary part of Zin closer to zero (see Fig. 3). Thus, Zin is dominated by RF Rpduring
several gigahertz. As a result, the optimal choice of gm1, LS1, RF, and CF ensures broadband input matching condition.
Second, the resistive component at the input is the parallel combination of RF and Rp, and the local feedback noise is
inversely proportional to RF; hence, we can select the larger
feedback resistor RFin order to suppress noise. The simulation 1The quality factor Q of the IC component is quite low, that is, the impedance
curve of the IC component is not so sharp; therefore, we can expect that the conversion range is wide.
Fig. 3. Simulation effect of CFon input impedance.
Fig. 4. Simulation effect of the RF on the NF.
effect of RFon the NF is shown in Fig. 4. Third, different from
the conventional inductive degeneration [3], the design in this study only uses a small inductor LS1 for input matching, so
the core area can be reduced. From the above observations, the proposed input stage can provide wideband input matching and better noise performance with a relatively small area. Moreover, a general noise figure of a common-source amplifier is linearly proportional to the frequency in 3–10 GHz. The noise factor of input stage Finis equal to
Fin= V2 n,o1 A2 v 1 4kT RS (7) where Vn,o1represents the total noise power at the output of the
input stage, which includes the thermal noise of RS, RF, RL1,
and M1. The output noise power contributed by RF and M1 is inversely proportional to f . As the frequency goes higher,
Av becomes low, and the output noise power contributed by RF and M1 is abated; therefore, RL1 plays a critical role in
increasing Fin due to low Av at a high frequency. Thus, we
Fig. 6. Simulation effect of LD, CD, and LS1on the NF of the input stage.
NF. As depicted in Fig. 5, we assume that the impedance seen looking into the drain of M1 is equal to Zo, the impedance
of parallel-LC circuit is ZLC, and the output noise power
contributed by RL1can be derived as Vn,o12 = 4kT RL1×
Z2
o
(Zo+ RL1+ ZLC)2
. (8)
From (8), Vn,o1 is inversely proportional to ZLC, so the
output noise voltage can be effectively reduced at resonance. As shown in Fig. 6, LD1, CD1, and LS1can reduce high-frequency
noise (7–15 GHz) effectively.
B. Second Stage
The second stage is a cascode common-source stage, which provides high-frequency gain and better isolation. The transis-tor M3is used for the improvement of M2’s Miller effect, better isolation, and higher gain. The series peaking inductor LD2can
resonate with the total parasitic capacitances CD3at the drain
of M3, and a resistor RL2 is added to reduce the Q factor of LD2for flat gain. As shown in Fig. 1, we use a voltage divider
that consists of resistors RB1 and RB2 to realize the forward
body bias (FBB) technique for reducing the threshold voltage of the transistor [10]. A general FBB needs an extra dc bias. In other words, we can save an extra dc pad by using a voltage divider, so the complexity of the layout is lessened, and the FBB can further obtain the same gm2with a low supply voltage so
that the power consumption can be reduced. Fig. 7 shows the
Fig. 7. Simulation frequency response of the input stage, the second stage, and the overall stage.
simulation frequency response of the input stage, the second stage, and the overall stage. The input stage and the second stage provide low-frequency power gain and high-frequency power gain, respectively. The combination of both frequency responses results a broadband power gain. The parameters of the UWB LNA design are listed in Table I.
III. EXPERIMENTALRESULTS
The proposed UWB LNA has been fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-μm CMOS process. The chip microphotograph is shown in Fig. 8. The chip area is 0.697 × 0.657 mm, including testing pads. The measurement is carried out on a wafer for RF characterization.
Fig. 9 shows the power gain and the input return loss of the UWB LNA. The measured power gain is 12.4 dB (± 1.5-dB variation) from 3.1 to 10.6 GHz. The measured high-frequency gain is less than the simulated one by about 1.4 dB. It may be due to process variation and inaccuracy of inductor and transistor models. The measured input return loss is −9.4 to
−32.5 dB from 3.1 to 15 GHz. Fig. 10 shows the output return
loss and the reverse isolation of the UWB LNA. The measured output return loss is below−8.5 dB, and the measured reverse isolation is below−45 dB across the entire band.
The measured and simulated NFs are illustrated in Fig. 11. The measured NF is 2.5–4.7 dB from 3.1 to 10.6 GHz. The measured NF is larger than the computed one due to degraded power gain. The measured and simulated group delays are illustrated in Fig. 12. The average delay is 75 ps with maximum and minimum values of 125 and 25 ps, respectively. Fig. 13 shows IIP3 measured by applying a two-tone test with 1-MHz spacing. The measured IIP3 is −8.5 dBm at 8 GHz. Fig. 14 shows the measured IIP3 versus frequency. The measured IIP3 is higher than −8.5 dBm from 4 to 10 GHz. In general, the figure of merit (FoM) is applied to evaluate performance of LNAs and is defined as [11]
FoM (mW−1) = S21[1]× BW (GHz)
(N F− 1)[1] × Pdc(mW)× ft(GHz) .
TABLE I
CIRCUITPARAMETERS OF THEUWB LNA
Fig. 8. Chip microphotograph of the UWB LNA.
Fig. 9. Power gain and input return loss of the UWB LNA.
Fig. 10. Output return loss and reverse isolation of the UWB LNA.
Fig. 11. Measured and simulated noise figures of the UWB LNA.
Fig. 12. Measured and simulated group delay of the UWB LNA.
Fig. 13. Measured IIP3 at 8 GHz.
Fig. 14. Measured IIP3 versus frequency.
The measured performance of the proposed LNA is com-pared with others, which is summarized in Table II. It is found that our circuit achieves an excellent noise figure and the best ratio of FoM to chip area.
IV. CONCLUSION
A UWB LNA has been proposed and implemented by the TSMC 0.18-μm CMOS technology. By using the proposed input stage, the local feedback noise can be reduced to achieve a very low NF and broadband input matching. The measured NF is 2.5–4.7 dB, and the power gain is 10.9–13.9 dB from 3.1 to 10.6 GHz. The measured input return loss is below−9.4 dB from 3.1 to 15 GHz. The IIP3 is −8.5 dBm at 8 GHz. It consumes 14.4 mW from a 1.4-V supply and occupies a chip area of only 0.46 mm2. The proposed UWB LNA compared with other UWB techniques has excellent noise performance, a small size, and a higher FoM.
ACKNOWLEDGMENT
The authors would like to thank the National Chip Implemen-tation Center, Taiwan, for chip fabrication and measurement support.
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