A Low-Voltage CMOS LNA Design Utilizing the
Technique of Capacitive Feedback Matching
Network
Chung-Yu Wu
Integrated Circuits and Systems Laboratory Institute of Electronics, National Chiao Tung University
Hsinchu, Taiwan cywu@alab.ee.nctu.edu.tw
Fadi Riad Shahroury
Integrated Circuits and Systems Laboratory Institute of Electronics, National Chiao Tung University
Hsinchu, Taiwan fadi rs@alab.ee.nctu.edu.tw
Abstract— In this paper, a CMOS low noise amplifier (LNA) with a new input matching topology has been proposed, analyzed, and measured. The input matching network is designed through the technique of capacitive feedback matching network. The proposed LNA which is implemented in a 0.18-µm 1P6M CMOS technology is operated at the frequency of 12.8 GHz. It has a gain S21 of 13.2 dB, a noise figure (NF) of 4.57 dB and anNFmin
of 4.46 dB. The reverse isolation S12 of the LNA can achieve -40 dB and the input and output return losses are better than -11 dB. The input 1-dB compression point is -11 dBm. This LNA drains 10 mA from the supply voltage of 1 V.
I. INTRODUCTION
In the design of RF CMOS LNAs, it is known that the key performance parameters are power gain and noise figure (NF), besides stability, linearity and isolation. The goal of LNA design is to achieve maximum power gain and minimum NF simultaneously at any given amount of power dissipation. To reach this goal, the input impedance Zin of a LNA must be kept close enough to the optimum source noise conjugate impedance Zn,opt∗ .
Conventionally, the inductive source degeneration technique is used to achieve this goal. However, this inevitably decreases the equivalent transconductace of the LNA at high frequencies, which reduces the power gain [2]. To retain the power gain, the power dissipation has to be increased significantly. For the LNAs operated above 10 GHz, an accurate and small source degeneration inductor value is required. The variations of the inductance makes Zin not close enough to Zn,opt∗ . To realize the accurate and small source degeneration inductance, microstrip line can be used at frequencies higher than 20 GHz. But it is chip area consuming if used at frequencies below 20 GHz.
So far, many high frequency RF CMOS LNAs have been proposed [3]-[7]. Among them, the proposed LNA structure at 17 GHz and 24 GHz [3] uses microstrip line to realize accurate source degeneration inductor. But the chip area is still large. The multistage common-source amplifiers are used
0this work was supported by National Science Council (NSC) Taiwan, under
the Grant NSC-94-2215-E-009-043
Fig. 1. a) The common-source amplifier as the input stage, b) The small-signal equivalent circuit for noise calculations.
in the LNAs in [4]-[6]. Each stage is designed with inductive source degeneration. To reach sufficient gain and good stability at frequencies from 8 GHz to Ku-band, high power dissipation is needed [4]-[6]. Although power gain match can be achieved by utilizing the input microstrip line in the LNA design [7], but
Zinis not equal to Zn,opt∗ in this case. Thus the minimum NF and maximum power gain cannot be achieved simultaneously. In this paper, a new LNA design technique is proposed, which uses the gate-drain capacitance and output capacitance of the input MOSFET to form the capacitive feedback match-ing network and brmatch-ing the input impedance Zin close to the optimum source noise conjugate impedance Zn,opt∗ . The current of the input MOSFET is then amplified by a RF current-mirror amplifier. It is shown that the proposed LNA has a high power gain of 13.2 dB, a high reverse isolation of
−40 dB, and a good linearity with the input 1-dB compression
point at−11 dBm. The NF and NFminof the proposed LNA are 4.56 dB and 4.46 dB, respectively. Therefore, the LNA has good noise performance because NF and N Fminare very close to each other. Besides, the proposed LNA has a small power consumption of 10 mW under the low power supply voltage of 1 V.
The details of design methodology and the designed CMOS circuit of the LNA are presented in Section II. Section III describes the experimental results. Finally, conclusion is given in Section IV.
II. OPERATIONALPRINCIPLES ANDCIRCUIT
IMPLEMENTATIONS
The common-source amplifier as the input stage is shown in Fig. 1(a), where Zsis the impedance seen from the right node of the input matching inductor Lg, Zinis the input impedance of M1, Cgd is the gate-drain capacitance, Cgs is the gate-source capacitance, Cfis the output loading capacitance which is the input capacitance of the next stage, Rs is the signal-source resistance, and Vs is the input signal voltage source. By using Millers theorem on Cgd, the input impedance Zin can be derived as Zin= Rf (Q2 f+ 1) + 1 jωo(Cgs+ Cgd)(Q12 f + 1) (1) where Qf = ωo(Cgs+ Cgd)Rf, Rf = g1 m Cf Cgd, gm is the
transconductace of M1, and ωo is the operating angular frequency. As may be seen from the above equations, both
Cgd and Cf with gm together provide a real term Rf which contributes to the real input impedance in Zin. They are called the capacitive feedback matching network.
Fig. 1(b) shows the small-signal model of the input stage for noise calculation. Three noise sources have been considered in Fig. 1(b). They are the thermal noise of the source resistance
in,Rs, the thermal noise of the channel current in,d, and the
gate induced current noise in,g.
The noise factor F is defined as the total output noise power divided by the noise power at the output due to the input source. F can be expressed as
F = 1 +γ α 1 gmRs |c|α δ 5γ 2 +R2s− s2L2g 1 R2f − α2δ 5γ (1 − |c|2)s2Ct2 −sCtRs 2 1 + |c|α δ 5γ 2 +2Rs Rf (2) where Ct= Cgs+Cgd, gd0is the zero-bias drain conductance,
γ is thermal noise coefficient, δ is the gate induced current noise factor, α ≡ gm/gd0, and c is a correlation coefficient theoretically equal to j0.395 [8]. By taking the derivatives of (2) with respect to Rs and Lg and let the derivatives equal to zero, optimum source noise impedance Zn,opt= Rsn,opt+ jωLgn,opt corresponds to minimum noise figure can be written
as Zn,opt = α2δ 5γ (1 − |c|2) + 1 Q2f + j 1 + α|c| δ 5γ α2 δ 5γ(1 − |c|2) +Q12f + 1 + α|c| δ 5γ 2 × 1 ω(Cgs+ Cgd). (3)
Using (1), (3) can be re-expressed in Zn,opt∗ as
Zn,opt∗ = Re[Zn,opt] + βImag[Zin]. (4)
β = 1 + 1 Q2f 1 + α|c| δ 5γ α2 δ 5γ(1 − |c|2) + 1 Q2f + 1 + α|c| δ 5γ 2 (5) From (4), the imaginary part of Zn,opt∗ is nearly the same as the imaginary part of Zin and expressed as βImag[Zin].
For the circuit in Fig. 1(a), the condition for maximum input power transfer (thus power gain) is Zin= Zs∗and that for the minimum noise figure is Zs = Zn,opt. Ideally, we have the condition for maximum power gain and minimum noise figure is Zin= Zn,opt∗ . From (1), (3), and (4), this condition can be satisfied if β is close to 1 and
1
gm(Q2f+ 1) Cf
Cgd = Rs
n,opt. (6)
In the proposed technique of capacitive feedback matching network, the value of β is more close to 1 as compared to the inductive source degeneration technique. Moreover, (6) can be satisfied by designing suitable device parameters gm,
Cgd, and Cgs of the device M1, which are related to gate-source voltage Vgs and transistor size W/L. In other words, the proposed design technique and input stage in Fig. 1(a) helps to maximize the power gain and to minimize the noise figure simultaneously by bringing Zin close to the optimum source noise conjugate impedance Zn,opt∗ .
It can be seen from (1) that without the feedback gate-drain capacitance Cgd, the input impedance of the common-source amplifier would have no real part. However, the optimum source noise impedance Zn,opt in (3) has a real part. Then it is impossible to satisfy the condition Zin = Zn,opt∗ . In the proposed technique, Cgdand the capacitive feedback matching network are used to satisfy the condition. Thus the technique is called the technique of capacitive feedback matching network. The complete circuit of the proposed LNA with the output stage is shown in Fig. 2 where in the LNA stage, M1 with the input amplifier transistor and M2/M3 forms the current-mirror amplifier as the second amplifier stage. The effective transconductance of the two stages is given by
|Gef f| = 1 2Rs ωT ωo gm3 ωoCf (7) where ωT is unit gain angular frequency, gm3is the transcon-ductance of M3, Cf is the total capacitance at the drain of M1 which is dominated by Cgs of M2 and M3. M2 is used as the master transistor of the MOS current-mirror amplifier along with the slave transistor M3. The size of M2 is chosen to be very small as compared to M1 and M3 to obtain a higher current gain. Since the cascode structure is not adopted, the proposed LNA can be operated at a low supply voltage.
Fig. 2. The complete circuit diagram of proposed LNA.
In order to make the parallel resonance circuit behave like a capacitive load, a parallel resonance circuit composed of L2 and the parasitic capacitance at the drain of M1 resonates at the frequency below the operating frequency of the LNA. R1 is used to ensure stability. C1 and C2 are dc blocking capacitors. The tank L3 and C3 is used to resonate with the parasitic capacitances of the gate M4. R2 is used to provide the gate dc bias of M1 and chosen large enough that its equivalent noise current is small enough to be ignored.
In the output stage, the output buffer composed of M4, L4, C4, and R3, is designed for the measurement purpose. R3 is used to provide the gate dc bias of M4, C2 and C4 is the dc blocking capacitor. The output inductor L4 is used to resonate with the parasitic capacitances at the drain of M4. The voltage gain of the buffer is unity.
Form (5) and under the condition of the short channel devices, the expected noise parameters of device are α= 0.6,
δ/γ= 2, |c| = 0.5 and Qf = 2. In the proposed LNA, the β is
0.87, while the β of the of the LNA with source degenerative method is equal to 0.82.
It is important to notice that some amount of mismatch in the input matching Zin = Zs∗ has negligible effect on the LNA performance, while the mismatch in Zs= Zn,optdirectly affects the NF [9]. Thus Re[Zin] is designed to be equal to the calculated Rsn,opt which is equal to48Ω.
III. EXPERIMENTALRESULTS
Based upon the proposed technique of capacitive feedback matching network and LNA structure, an experimental chip of a LNA operated at 13 GHz was designed and fabricated in 0.18-µm CMOS technology. The chip photograph is shown in Fig. 4 and the total die area is746.5µm × 884.6µm including all testing pads and dummy metals. The performance of the fabricated LNA circuit was tested through on-wafer probing technique. Fig. 3(a) shows the measured S21 of 13.2 dB at 12.8 GHz and a low input return loss S11. Fig. 3(b) shows the measured output return loss S22 and reverse isolation S12. As seen from Figs. 3(a) and 3(b), the measured reverse isolation S12 of the LNA achieves −40 dB whereas the input and output return losses are better than −11 dB. The frequency shift from 13 GHz to 12.8 GHz is due to the inaccurate modeling of planar inductor at high frequency.
The fabricated LNA has a NF of 4.57 dB and the minimum noise figure N Fmin of 4.46 dB at 12.8 GHz as shown in
Fig. 3(c). As may be seen from Fig. 3(c), NF and N Fminare very close to each other over a large frequency range. Thus the proposed LNA is insensitive for operating frequency vari-ations. The measured output power versus the input power is shown in Fig. 3(d) where the input referred 1-dB compression gain is−11 dBm.
The measured performance parameters are summarized in Table I where comparisons with other published works are also listed. A figure of merit (FOM) [10] used for comparisons is defined in the following
F OM = [10 (S21+IIP 3)/10] × fc 109 [10N F /10− 1] × PDC 10−3 . (8)
This FOM takes into account the operating frequency fc, NF, S21, and IIP3 of LNA. Based upon Table I, it is clear that the proposed LNA outperform all the other LNAs with a higher value of FOM. As expected, the proposed LNA with the technique of capacitive feedback matching network has high power gain and low noise figure under low power dissipation. It can be operated at a low supply voltage of 1 V since the cascode structure is not adopted. However, it still has a high reverse isolation.
IV. CONCLUSION
A new LNA structure with the technique of capacitive feedback matching network is proposed and analyzed. An experimental chip of 13-GHz LNA has been successfully designed and fabricated. The measurement results have shown that the proposed LNA can achieve minimum noise figure and maximum power gain simultaneously. Moreover, the NF is insensitive to the large operating frequency shift.
Future research will be conducted to design LNAs at frequencies below 24-GHz or higher using the technique of capacitive feedback matching network and integrated them with mixers. Since the proposed LNA can be designed in transconductance mode with an output current to drive the current-mode mixers, the designed transconductance LNA (TLNA) will be explored in the future.
ACKNOWLEDGMENT
The authors would like to thank the National Chip Imple-mentation, National Applied Research Laboratory, Taiwan, for the fabrication of the testing chip.
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(a) (b)
(c) (d)
Fig. 3. LNA measurement results: (a)S11andS21, (b)S22andS12, (c) noise figure NF and minimum noise figureFmin, and (d)PinversusPout. TABLE I
THE MEASURED PERFORMANCE PARAMETERS OF THE FABRICATEDLNAAND COMPARISONS WITH OTHER PUBLISHEDLNAS.
This work [5] [6] [6] [7]
Tech. 0.18µm 0.18µm 0.18µm 0.18µm 90nm
CMOS CMOS CMOS CMOS CMOS
Topology of Capacitive Source Degeneration inductor Microstrip Line
Input matching Feedback
Freq.(GHz) 12.8 14 8 9 20 Gain(dB) 13.2 10.71 13.5 12.2 5.8 NF(dB) 4.57 3.16 3.2 3.7 6.4 IIP3(dBm) −1∗ 1.6 −3.2∗ −1.3∗ 5.2 Power(mW) 10 28.6 22.4 19.6 10 Supply (V) 1 1.3 1 1 1.5 S11(dB) −11 −10 −5.8 −5.4 – Chip Size (mm2) .746 × .885 .88 × .77 – 1 × .9 .7 × .8 FOM 11.6 7.2 3.5 4.2 7.4
*The IIP3 is predicted by input P1dB+10dBm
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Fig. 4. The chip photograph of the proposed LNA.
