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154 IEEE ELECTRON DEVICE LETTERS, VOL. 26, NO. 3, MARCH 2005

High-Performance Nonvolatile HfO

2

Nanocrystal

Memory

Yu-Hsien Lin, Student Member, IEEE, Chao-Hsin Chien, Ching-Tzung Lin, Chun-Yen Chang, Fellow, IEEE, and

Tan-Fu Lei

Abstract—In this letter, we demonstrate high-performance

non-volatile HfO2nanocrystal memory utilizing spinodal phase sepa-ration of Hf-silicate thin film by 900 C rapid thermal annealing. With this technique, a remarkably high nanocrystal density of as high as0 9 1 9 1012cm 2with an average size 10 nm can be easily achieved. Because HfO2nanocrystals are well embedded inside an SiO2-rich matrix and due to their sufficiently deep energy level, we, for the first time, have demonstrated superior character-istics of the nanocrystal memories in terms of a considerably large memory window, high-speed program/erase (P/E)(1 s 0 1 ms), long retention time greater than108s for 10% charge loss, and excellent endurance after106P/E cycles.

Index Terms—Hafnium oxide, nanocrystals, nonvolatile

memo-ries, phase separation.

I. INTRODUCTION

A

CCORDING to the International Technology Roadmap for Semiconductors, there are critical limitations for aggressively scaling the conventional nonvolatile floating-gate memories below sub-70-nm node [1]. Therefore, the poly-sil-icon–oxide–nitride–oxide–silicon (SONOS)-type structure memories including nitride memories and nanocrystal memo-ries have recently attracted much attention for the application in the next-generation nonvolatile memories [2]–[11] because of their great potential for achieving high program/erase (P/E) speed, low programming voltage and low power performance. However, many concerning issues are still presented for both types of memories. For conventional SONOS, erase saturation and vertical stored charge migration [8], [9] are the major drawbacks; while for nanocrystal memories good enough charge keeping capability of the discrete storage nodes and the formation of nanocrystals with constant size, high density and uniform distribution are the extremely challenging issues [10]. In recent years, many papers have ever shown Al O trapping layer as the potential candidate for replacing Si N [11] and also demonstrated different kinds of nanocrystals to provide charge storage for the nonvolatile memories, such as Si nanocrystals, germanium (Ge) nanocrystals, and metal nanocrystals [2]–[7].

Manuscript received November 12, 2004. This project was sponsored by the National Science Council, Taiwan, R.O.C. under Contract 93A0500001. The review of this letter was arranged by Editor C.-P. Chang.

Y.-H. Lin, C.-T. Lin, C.-Y. Chang, and T.-F. Lei are with the Department of Electronics Engineering and Institute of Electronics, National Chiao-Tung Uni-versity, Hsinchu 300, Taiwan, R.O.C.

C.-H. Chien is with the National Nano Device Laboratory, Hsinchu 300, Taiwan, R.O.C. (e-mail: [email protected]).

Digital Object Identifier 10.1109/LED.2004.842727

In this letter, we explore a novel technique, which is fully compatible to current CMOS technologies, to form the very local HfO nanocrystals for the application of the nonvolatile flash memories utilizing spinodal decomposition of hafnium sil-icate after sufficiently high temperature rapid thermal annealing (RTA) treatment [12]. With this technique, we can well isolate the HfO nanocrystals from each other with SiO -rich matrix. Combining with the effect of large band gap offset between HfO and SiO , we have successfully achieved the nanocrystal memories with superior characteristics in terms of considerably large memory window, high speed P/E, long retention time, and excellent endurance.

II. DEVICESFABRICATION

The fabrication process of the HfO nanocrystal memory de-vices was demonstrated with LOCOS isolation process on a p-type 5–10 cm (100) 150-mm silicon substrates. First, a 2-nm tunnel oxide was thermally grown at 1000 C in ver-tical furnace system. Next, a 12-nm amorphous HfSiOx silicate layer was deposited by co-sputtering method with pure Silicon (99.9999% pure) and pure Hafnium (99.9% pure) targets in the oxygen gas ambient. The co-sputtering process was performed at torr with precursors of O (3 sccm), Ar (24 sccm) and the both dc sputter power was set to 150 W at the room temperature. After that, the samples went through RTA treat-ment in O ambient at 900 C for 1 min in order to convert HfSiO silicate film into the separated HfO and SiO phases which compositions were identified both by energy dispersive spectrometer (EDS) and X-ray photoelectron spectroscopy (not shown). A blocking oxide of about 8 nm was then deposited by high-density plasma chemical vapor deposition followed by 900 C 1 min N densification process. Then, poly-Si deposi-tion, gate patterning, source/drain (S/D) implant, and the rest of the subsequent standard CMOS procedure were complete for fabricating the HfO nanocrystal memory devices.

III. CHARACTERIZATIONRESULTS ANDDISCUSSION

Fig. 1 shows the plane-view high-resolution transmission microscopy (HRTEM) images of the HfO nanocrystals. The average nanocrystal size is around 5–8 nm and the density can be as high as cm . Clearly, they are well separated with an average distance 5 nm in two-dimensional with SiO . This leads to the well isolation of nanocrystals from each other and effectively prevents formation of good conductive paths between the adjacent nodes. The mechanism responsible for the formation of HfO nanocrystals is well

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LIN et al.: HIGH-PERFORMANCE NONVOLATILE HfO NANOCRYSTAL MEMORY 155

Fig. 1. Plane-view HRTEM image of the HfO nanocrystals. The size is about 5–8 nm and the dot density is0:9 0 1:9 2 10 cm . The inset show the diffraction patterns of as-deposited and 900 C RTA-treated samples.

Fig. 2. I –V curves of programmed memories with different programming conditions. The programming time is 10s. A memory window of larger than 3 V can be achieved withV = V = 10 V programming operation.

known to be the transformation of hafnium silicate into a phase separated microstructure [13]. Basically, compositions within metastable extensions of the spinodal are unstable and will spontaneously unmix in the amorphous phase upon cooling from RTA processing. The atomic concentrations in the as-deposition HfSiOx layer examined by EDS analysis are 12.61%, 18.99%, and 68.40% for Hf, Si, and O, respectively. With this element composition, we can easily and reproducibly produce high density HfO nanocrystal dots embodied by an SiO -rich matrix after RTA in O ambient. In addition, from the diffraction patterns, it is clearly observed that the as-deposited film is amorphous and the sample that is subject to RTA is polycrystalline. The crystalline structure of HfO nanocrystal is monoclinic.

Fig. 2 shows the – curves of the HfO nanocrystal memory devices with programming time of 10 s for different programming conditions. Channel hot-electron injections and band-to-band hot-hole injections were employed for program-ming and erasing, respectively. A relatively large memory window of about 3 V can be achieved at the V program operation. Program characteristics as a function of pulsewidth for different operation conditions are shown in Fig. 3(a). Both source and substrate terminals were biased at 0 V. The “ shift” is defined as the threshold voltage change of a device between the written and the erased states. With

Fig. 3. (a) Program characteristics of HfO nanocrystal memory devices with different programming conditions. A memory window of about 5 V can be achieved withV = V = 10 V, and time = 100 s programming operation. (b). Erase characteristics of HfO nanocrystal memory devices with different erasing voltages.

V, relatively high speed (10 s) programming performance can be achieved with a memory window of about 2.2 V. Meanwhile, Fig. 3(b) displays the erase characteristics as a function of various operation voltages. Again, excellent erase speed of around 0.1 ms can be obtained. More important, there is only a very small amount of overerase observed. The reason is owing to the fact that the vertical electric field decreases with decreasing amount of trapped electrons in the nanocrystals during erasing and the hole injection into the nanocrystals will reduce significantly due to the higher hole tunneling barrier presented in HfO SiO stack after all programmed charges are removed [14].

The retention characteristics of the HfO nanocrystal memory devices at both room temperature C and higher temperature C are illustrated in Fig. 4. The retention time can be up to seconds for 10% charge loss at room temperature. Only slight charge loss has been seen even at the temperature up to 125 C. We ascribe these results to the combining effects of the tight embrace of HfO nanocrystals by SiO -rich matrix and the sufficiently deep trap energy level [14]. The extracted activation energy lies in the range of around 2.1 3.3 eV for our memories, which is obviously higher than that reported in the previous work for the conventional SONOS memories [15]. Therefore, albeit with a tunnel oxide down to

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156 IEEE ELECTRON DEVICE LETTERS, VOL. 26, NO. 3, MARCH 2005

Fig. 4. Retention characteristics of HfO nanocrystal memory devices atT = 25 C and 125 C. Very low charge loss is seen even after 10 s.

Fig. 5. Endurance characteristics of HfO nanocrystal memory devices. Negligible degradation is found even after10 P/E cycles.

2 nm in thickness, no significant lateral and vertical charge migrations occurred. As a result, superior retention charac-teristic of the charge storage can be procured. The endurance characteristics after P/E cycles are also shown in Fig. 5. The programming and erasing conditions are V for 10 s and V, V for 1 ms, respectively. No detectable memory window narrowing has been displayed. Moreover, the individual threshold voltage shifts in program and erase states only become visible after cycles. This trend indicates that the amount of operation-induced trapped electrons is very tiny. Certainly, this is intimately related to the use of ultra-thin tunnel oxide and very minute amount of residual charges in the HfO nanocrystals after cycling.

IV. CONCLUSION

In this letter, we have proposed a novel simple, repro-ducible, reliable technique for preparation of high density HfO

nanocrystals using spinodal decomposition of hafnium silicate and achieved nanocrystal memories with superior characteris-tics in terms of large memory windows, high speed P/E, long retention time, and excellent endurance.

REFERENCES

[1] Test and test equipment, in The International Technology Roadmap for Semiconductors, San Jose, CA, pp. 27–28, 2001.

[2] R. Ohba, N. Sugiyama, K. Uchida, J. Koga, and A. Toriumi, “Non-volatile Si quantum memory with self-aligned doubly-stacked dots,”

IEEE Trans. Electron Devices, vol. 49, no. 8, pp. 1392–1398, Aug.

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[3] R. Muralidhar, R. F. Steimle, M. Sadd, R. Rao, C. T. Swift, E. J. Prinz, J. Yater, L. Grieve, K. Harber, B. Hradsky, S. Straub, B. Acred, W. Paulson, W. Chen, L. Parker, S. G. H. Anderson, M. Rossow, T. Merchant, M. Paransky, T. Huynh, D. Hadad, K.-M. Chang, and B. E. White, Jr., “A 6 V embedded 90 nm silicon nanocrystal nonvolatile memory,” in IEDM

Tech. Dig., 2003, pp. 601–605.

[4] T. Baron, B. Pellissier, L. Perniola, F. Mazen, J. M. Hartmann, and G. Polland, “Chemical vapor deposition of Ge nanocrystals on SiO2,” Appl.

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[5] Q. Wan, C. L. Lin, W. L. Liu, and T. H. Wang, “Structural and electrical characteristics of Ge nanoclusters embedded in Al O gate dielectric,”

Appl. Phys. Lett., vol. 82, pp. 4708–4710, 2003.

[6] C. Lee, A. Gorur-Seetharam, and E. C. Kan, “Operational and relia-bility comparison of discrete-storage nonvolatile memories: Advantages of single- and double-layer metal nanocrystals,” in IEDM Tech. Dig., 2003, pp. 557–561.

[7] M. Takata, S. Kondoh, T. Sakaguchi, H. Choi, J.-C. Shim, H. Kurino, and M. Koyanagi, “New nonvolatile memory with extremely high density metal nano-dots,” in IEDM Tech. Dig., 2003, pp. 553–557.

[8] P. Xuan, M. She, B. Harteneck, A. Liddle, J. Bokor, and T.-J. King, “FinFET SONOS flash memory for embedded applications,” in IEDM

Tech. Dig., 2003, pp. 609–613.

[9] T. Sugizaki, M. Kobayashi, M. Ishidao, H. Minakata, M. Yamaguchi, Y. Tamura, Y. Sugiyama, T. Nakanishi, and H. Tanaka, “Novel multi-bit SONOS type flash memory using a high- charge trapping layer,” in

Proc. VLSI Symp. Tech. Dig., 2003, pp. 27–28.

[10] M. L. Ostraat, J. W. De Blauwe, M. L. Green, L. D. Bell, M. L. Brongersma, J. Casperson, R. C. Flagan, and H. A. Atwater, “Syn-thesis and characterization of aerosol silicon nanocrystal nonvolatile floating-gate memory devices,” Appl. Phys. Lett., vol. 79, pp. 433–435, 2001.

[11] T. Sugizaki, M. Kobayashi, H. Minakata, M. Yamaguchi, Y. Tamura, Y. Sugiyama, H. Tanaka, T. Nakanishi, and Y. Nara, “New 2-bit/Tr MONOS type flash memory using Al O as charge trapping layer,” in

Proc. IEEE Non-Volatile Semiconductor Memory Workshop, Feb. 2003,

pp. 60–61.

[12] S. Stemmer, Z. Chen, C. G. Levi, P. S. Lysaght, B. Foran, J. A. Gisby, and J. R. Taylor, “Application of metastable phase diagrams to silicate thin films for alternative gate dielectrics,” Jpn. J. Appl. Phys., vol. 42, pp. 3593–3597, 2003.

[13] S. Saito, Y. Matsui, K. Torii, Y. Shimamoto, M. Hiratani, and S. Kimura, “Inversion electron mobility affected by phase separation in high-per-mittivity gate dielectrics,” Jpn. J. Appl. Phys., vol. 42, pp. L1425–L1428, 2003.

[14] W. J. Zhu, T.-P. Ma, T. Tamagawa, J. Kim, and Y. Di, “Current transport in metal/hafnium oxide–silicon structure,” IEEE Electron Device Lett., vol. 23, no. 2, pp. 97–99, Feb. 2002.

[15] B. De Salvo, G. Ghibaudo, G. Pananakakis, G. Reimbold, F. Mondond, B. Guillaumot, and P. Candelier, “Experimental and theoretical inves-tigation of nonvolatile memory data-retention,” IEEE Trans. Electron

數據

Fig. 2. I –V curves of programmed memories with different programming conditions. The programming time is 10 s
Fig. 4. Retention characteristics of HfO nanocrystal memory devices at T = 25 C and 125 C

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