Investigation on CDM ESD events at core circuits in a 65-nm CMOS process

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Investigation on CDM ESD events at core circuits in a 65-nm CMOS process

Chun-Yu Lin

⇑

, Tang-Long Chang, Ming-Dou Ker

National Chiao-Tung University, Hsinchu, Taiwan

a r t i c l e

i n f o

Article history:

Received 25 November 2011

Received in revised form 26 February 2012 Accepted 27 April 2012

Available online 19 May 2012

a b s t r a c t

Among three chip-level electrostatic discharge (ESD) test standards, which were human-body model (HBM), machine model (MM), and charged-device model (CDM), the CDM ESD events became critical due to the larger and faster discharging currents. Besides input/output (I/O) circuits which were con-nected to I/O pads, core circuits also suffered from CDM ESD events caused by coupled currents between I/O lines and core lines. In this work, the CDM ESD robustness of the core circuits with and without insert-ing shieldinsert-ing lines were investigated in a 65-nm CMOS process. Veriﬁed in a silicon chip, the CDM ESD robustness of the core circuits with shielding lines were degraded. The failure mechanism of the test cir-cuits was also investigated in this work.

1. Introduction

The major reliability issue for IC products is the damage caused by electrostatic discharge (ESD)[1,2]. Against ESD damages, on-chip ESD protection circuit must be included in IC products. A gen-eral concept of on-chip ESD protection for ICs is shown inFig. 1 [3,4]. The ESD protection device at input/output (I/O) pad and the power-rail ESD clamp circuit must be provided to accomplish the whole-chip ESD protection.

The ESD robustness of IC products can be tested. The chip-level ESD test standards are known as human-body model (HBM)[5], machine model (MM)[6], and charged-device model (CDM)[7]. The real-case HBM (MM) ESD events are caused from human (ma-chine). The electrostatic charges are initially stored in the human (machine), and then transfer into the IC, when the human (ma-chine) touches the IC. A 2-kV HBM (200-V MM) ESD event can gen-erate an ESD current peak of 1.3 A (3.5 A) with a rise time of 10 ns[8]. The CDM ESD event happens as a certain pin of the IC is suddenly grounded, and the electrostatic charges originally stored within the IC will be discharged through the grounded pin. The typical 1-kV CDM ESD event from a charged IC (with an equivalent 4-pF capacitance to ground) can generate a current peak as high as 15 A within a rise time of only 0.2 ns[8]. Among the chip-level ESD test standards, the CDM ESD events play major roles to cause failures in today’s manufacturing and packaging environments [9,10]. Therefore, several ESD protection designs against CDM ESD events have been reported to protect the I/O cir-cuits which are directly connected to the external pins[11–13]. Be-sides the I/O circuits, the core circuits would also suffer the dangers

when the CDM ESD events happened at the I/O circuits. As com-pared with HBM and MM ESD events, the discharging current in CDM ESD event is larger and faster. Such very fast transient ESD pulse will be inherently conducted by the displacement current of capacitor, I = C (dv/dt), to the external ground through the path with parasitic capacitance. Therefore, the coupling effects be-tween I/O line and core line should be considered during CDM ESD events. The core circuit may also suffer from ESD stress caused by the coupled current when I/O circuit is stressed by ESD.

Adding the shielding lines near to the signal lines of high-speed circuits is an efﬁcient method to limit the inductive coupling and to reduce the crosstalk noise between signal lines [14]. The signal lines are generally shielded by the shielding lines which are biased at VDDor VSS. However, the coupling effect between the shielding

and signal lines during CDM ESD event could induce large transient current to damage the core circuits[15,16]. The coupling effect be-tween I/O line and core line during CDM ESD event can induce large transient current to damage the core circuit, even if the shielding line is inserted. In this paper, the CDM ESD events at core circuits due to coupling effects are investigated in a 65-nm CMOS process.

2. Test circuits

To investigate the CDM ESD events at core circuits due to the coupling effects between I/O line and core line, the test circuit with and without shielding line is shown inFig. 2. The I/O circuit real-ized with inverter is connected to the I/O pad through the I/O line with ESD protection device at the I/O pad. The ESD protection device is realized with the gate-grounded NMOS (GGNMOS) of 360

l

m/0.12

l

http://dx.doi.org/10.1016/j.microrel.2012.04.021 ⇑ Corresponding author.

E-mail address:[email protected](C.-Y. Lin).

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Microelectronics Reliability

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inserting the shielding line between I/O line and core line 1 (core line 2) are arranged in parallel to the I/O circuit. The I/O line and core line are realized with metal 3, while the shielding line is

realized with metal 1 metal 6. The spacing between I/O line and core line is labeled as S, and it is split with 0.78

l

m and 1.98

l

m. The length of I/O line, core line, and shielding line are the same and labeled as L. The length of L is split with 20

l

m, 50

l

m, and 100

l

m. The spacing between I/O line and the shielding line, the width of shielding metal, and the spacing between the shielding line and the core line are labeled as S1, S2, and S3, respec-tively. The S1 and S2 are kept at 0.3

l

m and 0.18

l

m, respectively, while the S3 is split with 0.3

l

m and 1.5

l

m in the test circuit with shielding line. The split conditions of the test circuits with different L, S, S1, S2, and S3 are summarized inTables 1 and 2.Fig. 3shows the layout top view of one set of test circuits (A5 and B5). 3. CDM ESD test results

All test circuits have been fabricated in a 65-nm CMOS process with the thin-gate oxide of 20 Å. The test circuits with a die size of 2 1.5 mm2have been assembled in DIP-40-pin packages. The CDM ESD stresses are applied by the ﬁeld-induced CDM tester. The electrostatic charges are stored into the IC, including P-substrate and VDDmetal bus, and then discharging through a grounded metal

probe. The failure criterion is deﬁned as the I–V characteristics seen at I/O pad shifting over 30% from its original curve after CDM ESD stressed at every test level. The measured CDM ESD robustness among these test circuits without and with shielding lines are listed inTables 1 and 2, respectively. The negative CDM ESD robustness of all core circuits exceeded 600 V. The positive CDM ESD robustness of some core circuits without inserting the shielding line exceeded 600 V. Even if the metal length (L) of core circuits without inserting shielding is reduced, which leads to the lower impedance and higher overshoot voltage, the positive CDM ESD robustness can still achieve 400 V. However, the positive CDM ESD robustness of core circuits with inserting the shielding lines are seriously degraded to only 100 V.

4. Failure analysis and discussion

The leakage current of the test circuit will increase if the test circuit is failed after CDM ESD stresses. The scanning electron microscope (SEM) was used to ﬁnd the failure location to cause the large leakage current. The SEM photo of the core circuit in test circuit A1 after 500-V CDM ESD test is shown inFig. 4. Besides, the

Fig. 1. ESD protection design at I/O pad.

Fig. 2. Test circuit without (with) inserting shielding between I/O line and core line 1 (core line 2).

Table 1

CDM ESD robustness of test circuits without inserting the shielding line between I/O line and core line.

Test circuit L (lm) S (lm) S1 (lm) S2 (lm) S3 (lm) Positive CDM ESD robustnessa

(V) Negative CDM ESD robustnessa

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A1 20 0.78 N/A N/A N/A 400 < 600

A2 20 1.98 N/A N/A N/A >600 < 600

A3 50 0.78 N/A N/A N/A 400 < 600

A4 50 1.98 N/A N/A N/A >600 < 600

A5 100 0.78 N/A N/A N/A >600 < 600

A6 100 1.98 N/A N/A N/A >600 < 600

a

The CDM ESD test voltage was increased in 100-V step.

Table 2

CDM ESD robustness of test circuits with inserting the shielding line between I/O line and core line.

Test circuit L (lm) S (lm) S1 (lm) S2 (lm) S3 (lm) Positive CDM ESD robustnessa

(V) Negative CDM ESD robustnessa

(V) B1 20 0.78 0.3 0.18 0.3 100 < 600 B2 20 1.98 0.3 0.18 1.5 100 < 600 B3 50 0.78 0.3 0.18 0.3 100 < 600 B4 50 1.98 0.3 0.18 1.5 100 < 600 B5 100 0.78 0.3 0.18 0.3 100 < 600 B6 100 1.98 0.3 0.18 1.5 100 < 600 a

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SEM photos of the core circuits in test circuits B5 and B6 after 200-V CDM ESD tests are shown inFigs. 5 and 6, respectively. The fail-ure points are located at the poly gates of transistors in core cir-cuits. The similar phenomena are founded in the other test circir-cuits. During negative CDM ESD stress, the negative charges located in P-substrate and VDDmetal bus of core circuit 1 can be discharged

through the ESD protection device at the I/O pad, VSS bus, and

the power-rail ESD clamp circuit or the P+ pickup of NMOS in core circuit 1, as the current paths shown inFig. 7a. Besides the core cir-cuit 1, the main current discharging paths of negative charges lo-cated in P-substrate and VDDmetal bus of core circuit 2 consist of

the ESD protection device, CS1, VSS bus, and the power-rail ESD

clamp circuit or the P+ pickup of NMOS in core circuit 2, as the cur-rent paths shown inFig. 7b. Although the capacitive current paths (CS, CS1, and CS3) exist between the gate terminals of core circuits

and the I/O pads, the main ESD currents will discharge through the low-impedance paths shown inFig. 7a and b rather than the CSand CS3to prevent the gate oxide of core circuits from

break-down under negative CDM ESD stresses. Therefore, the negative CDM ESD robustness of all core circuits exceeded 600 V.

During positive CDM ESD stress, there are multiple current dis-charging paths from the core circuits to the grounded I/O pad, as shown inFig. 8a and b. The positive electrostatic charges located in P-substrate and VDDmetal bus can be conducted through the P+

pickup of NMOS in core circuits or power-rail ESD clamp circuit into the VSSbus, and then discharged through the ESD protection

device or CS1 to external ground, as the dashed lines shown in Fig. 8a and b. However, if the power-rail ESD clamp circuit is lo-cated far from the I/O pad, the CDM current will not be efﬁciently discharged through this path. The positive electrostatic charges located in P-substrate and VDD bus may also be conducted

through the gate oxide in core circuits to damage the PMOS and NMOS. Without inserting the shielding line, the coupling current through CS is less. Therefore, only some damages are found at

the PMOS and NMOS in core circuit 1 after higher voltage CDM tests, as shown inFig. 4. After inserting the shielding lines, the coupling effects of CS1and CS3are increased. If the CS3is large

en-ough, the current path consisted of the gate oxide of PMOS, CS3,

and ESD protection device or CS1will be more destructive. This

discharging current causes the damage on PMOS of core circuit 2, as shown inFig. 5. If only the CS1is increased, the current path

consisted of the gate oxide of PMOS, gate oxide of NMOS, P+ pick-up of NMOS, and CS1will also be destructive. The damages of core

circuit 2 are located at both PMOS and NMOS, as shown inFig. 6. Therefore, the positive CDM ESD robustness of core circuits with inserting the shielding line are only 100 V in the test circuits. In contrast, the negative CDM ESD robustness was not degraded by inserting the shielding line in chip layout, as compared inTables 1 and 2.

To prevent from ESD damage at core circuits, ESD protection de-vices are also needed for core circuits which are close to the I/O cir-cuits, as shown inFig. 9.

Fig. 3. Layout top view of one test circuit for fabrication in a 65-nm CMOS process with 1-V devices.

Fig. 4. SEM photo of core circuit 1 in test circuit A1 after 500-V CDM ESD test.

Fig. 5. SEM photo of core circuit 2 in test circuit B5 after 200-V CDM ESD test.

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5. Conclusion

In this paper, the CDM ESD issue at core circuit which is not connected to I/O pad has been addressed. The CDM ESD tests are performed to several test circuits fabricated in 65-nm CMOS process. The measured results show that the core circuit also

suffers from CDM ESD issue due to the coupled current when I/O circuit is stressed by CDM ESD. The coupling effect during CDM ESD event is even critical to induce larger transient current to damage the core circuits, after inserting the shielding line between I/O line and core line. The failure mechanism is also addressed in this paper. This work can help foundries or IC design houses to improve their IC products with better CDM ESD robustness.

Acknowledgments

This work was supported by National Science Council, Taiwan, under Contract NSC 100-2221-E-009-048, and by the ‘‘Aim for the Top University Plan’’ of National Chiao-Tung University and Ministry of Education, Taiwan.

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Fig. 7. (a) Core circuit 1 and (b) core circuit 2 under negative CDM ESD event.

Fig. 8. (a) Core circuit 1 and (b) core circuit 2 under positive CDM ESD event.

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