394 IEEE ELECTRON DEVICE LETTERS, VOL. 26, NO. 6, JUNE 2005
Hot-Carrier Effects in P-Channel Modified
Schottky-Barrier FinFETs
Chia-Pin Lin, Student Member, IEEE, and Bing-Yue Tsui, Senior Member, IEEE
Abstract—High-performance p-channel modified
Schottky-barrier SOI FinFETs (MSB pFinFETs) with low temperature source/drain annealing process was recently suggested for future nano-scale devices. In this letter, the hot-carrier (HC) immunity of the MSB pFinFETs with different gate lengths( ) and fin widths ( ) are presented. The experimental data shows that the MSB pFinFET with narrower has less hot carrier degra-dation than that with wider . The effects of electrical field in Si fins induced from lateral-gate electrode and the degree of uniformity of source/drain extension are illustrated cautiously by two-dimensional simulation and transmission electron microscopy (TEM) micrographs, respectively. It is found that the devices with narrower have weaker electrical field from gate electrode and better uniformity of source/drain extension resulting in superior hot-carrier immunity. The projected operation voltage at ten years dc lifetime exceeds 1.6 V as the is narrower than 60 nm. It is thus concluded that the MSB pFinFET would be a very promising nano device.
Index Terms—FinFET, hot carrier, Schottky-barrier (SB),
silicon-on-insulator (SOI).
I. INTRODUCTION
A
high-performance tri-gate modified Schottky-barrier (SB) p-channel FinFET (MSB pFinFET) with ultrashort source/drain extension (SDE) at the interface of silicide and inverted channel has been recommended recently to overcome the drawbacks of SB MOSFETs while preserving the advantages such as the low S/D external resistance and the low tempera-ture process [1], [2]. When the devices are scaled down, MSB pFinFETs may also suffer from hot-carrier (HC) effects. For the prediction of the long-term reliability of the proposed tri-gate MSB pFinFETs; therefore, the HC reliabilities of the proposed devices are firstly investigated for various bias stress condi-tions and device dimensions. The superior HC reliability of the devices with narrower fins is confirmed. It is also pointed out that the proper balance and decrease of gate electric field in the narrow fin is the major reason of extraordinary hot carrier immunity in MSB pFinFET. On the other hand, as the gate length decreases, the quite exceedingly uniform of the SDE region in the narrow Fins is also regarded as the possible dominative mechanism of excellent HC reliability of MSB pFinFETs.Manuscript received January 3, 2005. The review of this letter was arranged by Editor E. Sangiorgi.
C.-P. Lin is with the Department of Electronics Engineering and the Institute of Electronics, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C. (e-mail: [email protected]).
B.-Y. Tsui is with the Department of Electronics Engineering and the Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C., and also with the National Nano Device Laboratories, Hsinchu 300, Taiwan, R.O.C.
Digital Object Identifier 10.1109/LED.2005.848096
II. EXPERIMENTS
Detail fabrication processes for the MSB pFinFETs used in this letter have already been reported elsewhere [2]. The fully depleted devices were fabricated on SIMOX substrate with 150-nm-thick buried oxide (BOX), 40-nm-thick Si active layers , 4-nm-thick thermally grown gate oxide, and 50-nm composite SiO Si N spacer. After NiSi was formed at the S/D contact, the SDE in the devices between silicide and channel was formed by implant-to-silicide process (ITS) and furnace annealing at 600 C for 30 min [3].
To investigate the HCE of the proposed MSB pFinFETs, the worst-case bias condition for HC stress was determined first. The degradations of device parameters including threshold voltage , transconductance , and drain current were found to be higher when the gate voltage was set at
in comparison with . Therefore, all the stress experiments were performed at for a wide range of stress biases at 300 K. Degradation in device parameters under several stress conditions were then tracked over time for MSB pFinFETs with two different and several fin widths . The degradations of the maximum transcon-ductance and drain current were measured in the linear region ( V and ). The electric field distribution in Si fins was simulated for MSB pFinFETs with various
ratios [4]. The roughness of the silicide front with nm and 200 nm were examined by planar view transmission elec-tron microscopy (TEM) micrographs.
III. RESULTS ANDDISCUSSIONS
The degradations of and for the MSB pFinFETs with
nm and different stressed at V
were shown in Fig. 1, respectively. Perhaps due to the sharp Si fin corner and mechanical stress induced by S/D silicide; the hot-carrier integrity (HCI) of MSB pFinFETs is slightly worse than that of conventional fully depleted SOI devices. Hole trapping at the interface of SiO /Si were still observed to dominate the HC degradation, similar to the conventional bulk and fully depleted SOI pMOSFETs [5]–[7]. We also discovered that the degrada-tion of MSB pFinFETs with wider is more serious than that of devices with narrower . The HC lifetimes of the devices with different (49 and 130 nm) and various were plotted against the reciprocal of the stress voltage in the inset of Fig. 2. The lifetime is defined as the stress time to reach 10% degrada-tion in because the is the most degradable parameters among , , and . As shown in the inset of Fig. 2, MSB pFinFETs with both nm and 130 nm meet the 10-yr life-time requirement under normal operating condition at V.
LIN AND TSUI: HOT-CARRIER EFFECTS IN P-CHANNEL MODIFIED SCHOTTKY-BARRIER FinFETs 395
Fig. 1. Degradation of the maximum transconductance(G ) and the drain current(I ) versus stress time for MSB pFinFETs with L = 49 nm and differentW .
Fig. 2. Projected operation voltages to twn-year lifetime of the MSB pFinFETs with differentL and W . The inset figure shows dc hot-carrier lifetime of the MSB pFinFETs withL = 49 and 130 nm and various W versus the reciprocal of the drain voltage. The failure criterion is 10% degradation inG .
The extrapolated operation voltages to a ten-year lifetime of devices with two different as a function of were dis-played in Fig. 2. It is surprising that when the decreases from 200 to 60 nm, the allowable operation voltage of the device with nm increases steeply from 1.33 to 1.67 V. For the devices with nm, the allowable voltage increases from 1.04 Vto 1.61 V. In order to explain the HC degradation dependence on , the cross-sectional electrical field simula-tions of Si fins with different ratio of were performed. The potential distribution in Si fin of the proposed device
bi-ased at V with nm and 40 nm were
shown in Fig. 3(a) and (b). Obviously, as the fin becomes wider, almost the energetic hot carriers are accelerated toward the top gate oxide as shown in Fig. 3(a). Nevertheless, in the narrow fin, the lateral gate voltages relax the electric field apparently due to the different direction of electric fields induced by the top gate and the two lateral gates, as shown in Fig. 3(b). With this result,
Fig. 3. Cross-sectional potential distribution in Si fins of the MSB pFinFETs with (a)W =T = 200 nm=40 nm and (b) W =T = 40=40 nm. The gate voltage is02 V.
Fig. 4. Plane view TEM and schematic images of the MSB pFinFETs with (a) narrow(W = 40 nm) and (b) wide (W = 200 nm) fins.
396 IEEE ELECTRON DEVICE LETTERS, VOL. 26, NO. 6, JUNE 2005
the electric field and then the HC degradation of narrower fin is distinctly smaller than that of wide ones.
Another important observation from Fig. 2 is the allowable operation voltage decrease apparently with the decrease of when the increases from 100 to 200 nm. In order to ex-plain the different HC degradation rates of the devices with different , it is postulated that the roughness of SDE may affect the HCI. The TEM micrographs and schematic images of the MSB pFinFETs with of 40 and 200 nm are shown in Fig. 4. Whenever the becomes wider, not only the mi-crostructure of the silicided fin changes from bamboo struc-ture to multigrain strucstruc-ture, but also the silicide/Si interface becomes rougher. Therefore, the uniformity of channel length of the wider devices degrades more than that of the narrower ones. For example, as the wide device shown in the inset of Fig. 4, because the channel length along A-A is shorter than that along B-B , the lateral electric field at A is higher than that at B, and then the HCI of wide device becomes poor.
IV. CONCLUSION
In this letter, we first demonstrated that the MSB pFinFETs with low temperature process also have strong resistance against HC degradation. The mechanisms of HC degradation of the de-vices with different geometries are demonstrated. The electric field in fins induced by the top and the two lateral gates domi-nate the HCI of the MSB pFinFETs. As the fin width decreases, the net electric field in fin is balanced off by the lateral gates, and therefore, predominately reduces the HC degradation of the
devices. Moreover, the roughness of SDE regions also affects the HCI, especially for devices with wide and short . As the result, in the devices with nm, the uniform SDE diffused from the bamboo-like silicide fin relieves the HC degra-dation in the narrow fin devices. To conclude, it is thus expected that the ultranarrow MSB pFinFETs with strong resistance against HC degradation would be a very promising nano device at sub-45-nm technology nodes.
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