Abstract—The physical mechanism of transient-induced latchup
(TLU) in CMOS ICs under the system-level electrostatic discharge (ESD) test is clearly characterized by device simulation and exper-imental verification in time domain. For TLU characterization, an underdamped sinusoidal voltage stimulus has been clarified as the realistic TLU-triggering stimulus under the system-level ESD test. The specific “sweep-back” current caused by the minority carriers stored within the parasitic pnpn structure of CMOS ICs has been qualitatively proved to be the major cause of TLU. All the simu-lation results on TLU have been practically verified in silicon with test chips fabricated by 0.25- m CMOS technology.
Index Terms—Holding voltage, latchup, silicon controlled
rec-tifier (SCR), system-level electrostatic discharge (ESD) test, tran-sient-induced latchup (TLU).
I. INTRODUCTION
T
RANSIENT-INDUCED LATCHUP (TLU) will increas-ingly be a primary reliability issue in CMOS IC products [1]–[5]. Recently, the test standard to verify the immunity of TLU on CMOS ICs has been announced [6]. This TLU ten-dency is caused by several reasons. First, there are much more complicated implementations of ICs, such as mixed-signal, mul-tiple power supplies, RF, system-on-chip, etc. The environment where these CMOS devices locate will suffer from consider-able noises coming from both interior and exterior of CMOS ICs. Thus, such transient stimuli, those unpredictably exist on power, ground, or I/O pins of ICs, certainly induce TLU much more easily than before. Second, more and more ICs, unfortu-nately, are rather susceptible to TLU under a strict demanded system-level electrostatic discharge (ESD) test [7]. Third, ag-gressive scaling of both device feature size, as well as the clear-ance between pMOS and nMOS devices, leads the inevitable parasitic silicon controlled rectifier (SCR) in CMOS ICs to ex-hibit a rather worse latchup immunity. The occurrence of latchup could still happen, even though the power supply voltage is re-duced with the scaling rule of CMOS ICs. The latchup triggering current does not prominently increase with the scaling rule of CMOS ICs while the power supply voltage keeps decreasing [8]. To investigate the physical mechanism of TLU under the system-level ESD test, the most significant part is to clarify theManuscript received December 2, 2004; revised May 20, 2005. This work was supported by Himax Technologies, Inc., Taiwan, R.O.C. The review of this paper was arranged by Editor C.-Y. Lu.
The authors are with the Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C. (e-mail: mdker@ieee.org).
Digital Object Identifier 10.1109/TED.2005.852728
TLU-triggering stimulus at first. So far, several TLU-triggering stimuli have been found to probably trigger on TLU [9]–[11]. The first developed TLU-triggering stimulus is to consider the power-on situation when power supply voltage ramps up from 0 V to its normal operating voltage during the power-on transition [9]. Once the rise time (ramp rate) of the power supply voltage during the power-on transition is short (fast) enough, latchup will probably be triggered on by the transient displacement current that flows through the parasitic well/sub-strate resistance of CMOS ICs. However, this situation only interpreted the occurrence of TLU during the initial power-on transition, but cannot reflect most TLU during the normal circuit operation. The second developed TLU-triggering stimulus is to utilize a single-positive (single-negative) voltage pulse applying on the pMOS (NMOS) drain terminal of CMOS ICs [10]. Such single-positive (single-negative) voltage pulse is used to gen-erate the transient overshooting (undershooting) noise on the output nodes of CMOS logic gates to simulate the dynamically switching operations. Thus, TLU could be triggered on due to the instantaneous forward-biased emitter/base junction current of the parasitic pnp (or npn) bipolar junction transistor (BJT). However, TLU issue still exists even if CMOS ICs are operated in a dc steady state without dynamically switching under the system-level ESD test. Recently, a single-positive current pulse [11] applying to the power pins of CMOS ICs is also used for TLU characterization. This TLU-triggering stimulus, however, does not reflect the real one under the system-level ESD test.
To clarify this issue, an underdamped sinusoidal voltage stim-ulus, which can be observed on all ICs within the equipment under test (EUT) under the system-level ESD test [12]–[14], is adopted in this paper as the TLU-triggering stimulus for both TLU measurement and device simulation [15]. With the clearly defined TLU-triggering stimulus, the physical mechanism of TLU under the system-level ESD test can be well explained in time domain by device simulation. Finally, all the simulation re-sults on TLU have been practically verified in silicon with test chips fabricated by 0.25- m CMOS technology.
II. TLU UNDERSYSTEM-LEVELESD TEST
To evaluate the performance of electrical/electronic equipments when subjected to ESD events, performing the system-level ESD test for the electrical/electronic equipments is necessary. For example, a notebook under the system-level ESD test with direct contact-discharge test mode is shown in Fig. 1. An electrical/electronic product with CMOS ICs must
Fig. 1. System-level ESD test on a notebook with direct contact-discharge mode according to IEC 61 000-4-2 international standard [7]. The inset figure depicts the typically measured waveforms of transient noise voltage on the power pins of CMOS ICs, which locate within the EUT, under the system-level ESD test [12]–[14].
Fig. 2. Measurement setup of the system-level ESD test with indirect contact-discharge test mode [7]. CMOS IC#1 is one of the CMOS ICs inside the EUT. The ESD gun zapping on the HCP could cause TLU events on the ICs, especially those inside the EUT.
sustain the ESD level of kV ( kV) under contact-dis-charge (air-discontact-dis-charge) test mode to achieve the immunity requirement of “level 4” in the system-level ESD test [7]. During such a system-level ESD test, electromagnetic interfer-ence (EMI) coming from the ESD will be coupled into the driver ICs of the liquid crystal display (LCD) panel. The inset figure in Fig. 1 depicts the typically measured ESD-generated voltage waveforms on the power pins of CMOS ICs, which locate within the equipment under test (EUT), under the system-level ESD test [12]–[14]. This ESD-generated transient voltage is quite large (with an amplitude of several tens to hundreds of volts) and fast (with period of several tens of nanoseconds), which can randomly exist on power, ground, or I/O pins of the driver ICs to cause TLU failures.
To clarify this issue, the system-level ESD test with indirect contact-discharge test mode is shown in Fig. 2, [7]. When the ESD gun zaps to the horizontal coupling plane (HCP), EMI
Fig. 3. MeasuredV transient waveform on one of the CMOS ICs (CMOS IC#1) inside the EUT, when the ESD gun with ESD voltage of+1000 V zapping on the HCP.
Fig. 4. MeasuredV ; I , andV transient waveforms on CMOS IC#1 inside the EUT, when the ESD gun with ESD voltage of+2000 V zapping on the HCP, to verify the occurrence of TLU during system-level ESD test.
coming from the ESD will be coupled into all CMOS ICs in-side the EUT. With ESD voltage of V, the measured transient waveforms on one of the CMOS ICs (CMOS IC#1) in-side the EUT are shown in Fig. 3. The transient peak voltage on is as large as V in Fig. 4. Clearly, the with initial dc voltage of V will become an underdamped sinewave-like voltage due to the disturbance of the ESD energy. Once the ESD voltage keeps increasing, the TLU can be initiated and results in the malfunction or damage of the CMOS IC inside the EUT. For example, with an ESD voltage of V, the measured , and transient waveforms on CMOS IC#1 are shown in Fig. 4. The transient peak voltage on is greater than V, during such a system-level ESD test. TLU occurs with instantaneously increasing , so that (100-MHz voltage clock) will fail to function correctly (pulled
Fig. 5. (a) Device cross-sectional view and (b) layout top view of the SCR structure for TLU measurements. Geometrical parameters such asD; S, and W represent the distances between well-edge and well (substrate) contact, anode and cathode, and the adjacent well (substrate) contacts, respectively. The specified SCR structure, fabricated by 0.25-m CMOS technology, with layout parameters ofD = 6:7, S = 1:2, and W = 22:5 m is used for all the TLU measurements in this paper.
down to 0 V). Thus, it can be clarified that the underdamped sinusoidal voltage existing on the power (ground) line of the CMOS ICs is the major cause to initiate TLU during the system-level ESD test.
III. TESTSTRUCTURE
The SCR structure is used as the test structure for TLU mea-surements because the occurrence of latchup is due to the in-herent SCR of two cross-coupled BJTs, parasitic vertical pnp and lateral npn BJTs, in bulk CMOS ICs [8]. The device cross-sectional view and layout top view of the SCR structure are sketched in Fig. 5(a) and (b), respectively. The geometrical pa-rameters such as , and represent the distances between well-edge and well (substrate) contact, anode and cathode, and the adjacent well (substrate) contacts, respectively. In CMOS ICs, the p anode (source of PMOS) and the n well contact are connected to , whereas the n cathode (source of NMOS) and the p substrate contact are connected to ground. Once latchup occurs inside the SCR structure, huge current will be generated through a mechanism of positive-feedback regenera-tion [16]. As a result, the huge current will conduct through a low-impedance path from to ground, and further probably burn out the chip due to excess heat.
Different values of geometrical parameters such as , and in Fig. 5(a) and (b) will certainly result in different TLU immunities of the SCR structures due to different latchup trig-gering (holding) voltages or currents [8]. However, TLU phys-ical mechanism should be the same and not related to the vari-ations of geometrical parameters. As a result, to qualitatively analyze the physical mechanism of TLU through TLU mea-surements, a specified SCR structure with layout parameters of
, , and m fabricated in 0.25- m
CMOS technology is used for all TLU measurements in this paper. Because the parasitic SCR existing in the core circuitry of CMOS ICs is most sensitive to TLU due to compact inte-gration, the minimum anode-to-cathode spacing ( m) according to foundry’s design rule is used to consider the worst case situation (most sensitive to TLU) encountered in the core circuitry of CMOS ICs.
Fig. 6. SCR structure used in a 2-D device simulation tool (MEDICI). The specified SCR structure with the geometrical parameters ofD = 6:7 m andS = 1:2 m is used for all the TLU device simulations in this paper.
Fig. 7. Component-level TLU measurement setup [3]. It can accurately simulate how an IC inside the EUT will be disturbed by the ESD-generated noise under the system-level ESD test.
To verify the relationship between the TLU measurement and device simulation, the specified SCR structure with the same ge-ometrical parameters of and m is used for all TLU device simulations in this paper by the two-dimensional (2-D) device simulation tool (MEDICI), as shown in Fig. 6. With the specified 2-D SCR structure, the boundary condition can be well defined to perform the numerical analysis of elec-trical characteristics such as electric potential, electric field, car-rier concentration, 2-D current flow line, etc.
IV. MEASUREMENTSETUP
For the system-level ESD test, it can only judge whether the EUT passes the required criterion through its abnormal function (e.g., EUT shuts down). Nevertheless, it is hard to directly eval-uate the TLU immunity of single IC inside the EUT. To solve this problem, a component-level TLU measurement setup with the following two advantages is used. First, it can easily eval-uate the TLU immunity of single IC by the related measured voltage/current waveforms through oscilloscope. Second, with the ability of generating an underdamped sinusoidal voltage, it can accurately simulate how an IC inside the EUT will be dis-turbed by the ESD-generated noise under the system-level ESD test. Fig. 7 depicts such a component-level TLU measurement
Fig. 8. MeasuredV waveform for the SCR structure with V of (a)+10 V, and (b) 02 V. Clearly, the intended positive-going (negative-going) underdamped sinusoidal voltage can be generated just as that under the system-level ESD test for ESD gun with positive (negative) voltage [12].
setup [3]. The SCR structure shown in Fig. 5 is used as the device under test (DUT) where the p anode and the n well contact are connected together to , but the n cathode and the p substrate contact are connected to ground. An electro-static-discharge simulator is used as the TLU-triggering source, , to produce an underdamped sinusoidal voltage stim-ulus. Through applying a positive (negative) , the in-tended positive-going (negative-going) underdamped sinusoidal voltage can be generated just as that under the system-level ESD test for ESD gun with positive (negative) voltage [12]. For ex-ample, with of V ( V), Fig. 8(a) and (b) shows the measured waveform across the SCR structure. Clearly, the intended underdamped sinusoidal voltage can be produced to simulate the transient voltage on power pins of CMOS ICs under the system-level ESD test, no matter which polarity (pos-itive or negative) the ESD voltage is. Because a large discharge resistance will result in a large damping factor of the intended underdamped sinusoidal voltage [3], there is no discharge resis-tance (0 ) between the relay and the node, as shown in Fig. 7. As a result, the intended underdamped sinusoidal voltage can be produced, but not the unwanted overdamped voltage
waveform due to a large discharge resistance [3]. In addition, a charged capacitance of 200 pF is used to store charges of-fered by the TLU-triggering source, , and then these stored charges are discharged to DUT through the relay. Be-cause the charged capacitance will affect the damping frequency of the underdamped sinusoidal voltage, it should be properly selected to achieve the reasonable damping frequency as that under the system-level ESD test. For example, the damping fre-quency ( MHz) observed in Fig. 8(a) and (b) is slightly smaller than that under the system-level ESD test ( MHz) [12], therefore indicating that this measurement setup is reason-able for TLU characterization. Moreover, a small current-lim-iting resistance (5 ) is recommended to protect the DUT from electrical-over-stress (EOS) damage during a high-current (low-impedance) latchup state.
V. DEVICESIMULATION FORTLU
A 2-D device simulation tool (MEDICI) is used to investi-gate the physical mechanism of TLU in time domain under the system-level ESD test. In this 2-D device simulation tool, a spe-cific time-dependent voltage source given by
(1) is used to apply an underdamped sinusoidal voltage on of the already defined SCR structure in Fig. 6. With the proper parameters such as initial voltage , applied voltage ampli-tude , damping factor , damping frequency , and time delay , the intended underdamped sinusoidal voltage can be constructed. In the following TLU simulation with positive or negative , the same parameters such as V,
s MHz, and ns are used
in both positive and negative , whereas the only
differ-ence is V for positive , but V for
negative . In addition, the specified SCR structure with geometrical parameters of m and m is used for all TLU device simulations in this paper.
A. Simulated Latchup DC – Characteristics
The simulated latchup dc current–voltage ( – ) character-istic of the specified SCR structure is shown in Fig. 9. Once latchup occurs in the SCR structure, a low-impedance path will exist from to ground, resulting in huge current conducting through this low-impedance path. The inset figure in Fig. 9 shows that the dc latchup triggering voltage (current),
, is about 15.5 V (0.24 mA), while the dc latchup holding voltage (current), , is about 1.25 V (0.5 mA). Clearly, under a latchup state, when the power supply voltage, , keeps at its normal circuit operating voltage ( V), the total power supply current, , flowing into both anode and well contact is about 150 mA. This will offer a vital evidence to verify whether TLU certainly occurs in time domain through device simulation.
B. TLU Simulation With Negative
With a negative , the simulated and tran-sient responses on the SCR structure are shown in Fig. 10. This can be divided into several parts for detailed discussions
Fig. 9. Simulated latchup dcI–V characteristic for the SCR structure. Under a latchup state, the fact thatI is about 150 mA whenV keeps at its normal operating voltage (+2:5 V) will offer a vital evidence to prove whether TLU certainly occurs in time domain through device simulation.
Fig. 10. SimulatedV andI transient responses for TLU with a negative V . During the period of62:5 ns t 87:5 ns, the “sweep-back” current,I , will be produced to initiate TLU (I significantly increases) whenV increases from its negative peak voltage to the normal operating voltage of+2:5 V.
in time domain. First, during the period of ns ns, the SCR operates in the blocking condition and is fixed at its normal operating voltage, V. Within this duration, the n-well/p-substrate junction is at a normal reverse-biased state, and only comes from the negligible leakage cur-rent in the reverse junction. Second, during the period of
ns ns, begins to decrease rapidly from
V at ns, and will eventually reach the negative peak voltage, ( V), at ns. Within this dura-tion, the n-well/p-substrate junction gradually becomes slightly reverse biased when decreases from to 0 V, and even becomes forward biased when drops below 0 V. Thus, at ns, the largest forward-biased n-well/p-substrate junc-tion can generate the forward peak current, ( mA). Third, during the period of ns ns, when increases from to its normal operating voltage, V, the n-well/p-substrate junction will rapidly change from the forward-biased state to its original reverse-biased state. Mean-while, inside the n-well (p-substrate) region, large number of stored minority holes (electrons) offered by the forward peak current at ns, will be instantaneously “swept-back” to
Fig. 11. Simulated transient responses of both anode current and well contact current for TLU with a negativeV . During the period of62:5 ns t 87:5 ns, latchup will be triggered on by I . Meanwhile, huge anode current will conduct through the pnpn latchup path of the SCR structure.
the p-substrate (n-well) region where they originally come from. Thus, such “sweep-back” current, , will produce a localized voltage drop while flowing through the parasitic p-substrate or n-well resistance. Once this localized voltage drop approaches to some critical value, the emitter-base junction of either vertical pnp or lateral npn BJT in the SCR structure will be forward biased to further trigger on latchup. This can be further illustrated by the simulated transient responses of both anode and well contact current, as shown in Fig. 11. It clearly proves where these stored minority carriers, , come from and when they will be “swept-back” to cause TLU. For example, the gradually-enhanced forward-biased n-well/p-substrate junction will lead the gradually-increasing well contact current during the period of ns ns. Meanwhile, anode current is the negligible junction-leakage current due to an almost zero bias across the p -anode/n-well junction. Afterwards, during the period of ns ns, the forward well contact current will gradually decrease when increases from to V, indicating that the stored minority electrons (holes) are swept-back to the n-well (p-substrate) region where they originally come from. As a result, once the returns to, and even above, V ( ns ns), latchup will be triggered on and huge anode current will conduct through the pnpn latchup path of the SCR structure. Meanwhile, the well contact current, however, is much smaller than the anode current because the well contact current is only the small base current of the parasitic vertical pnp BJT in the SCR structure.
In real CMOS ICs, when a low-impedance latchup state ap-pears, may be pulled down to about the dc latchup holding voltage. This phenomenon is caused by two reasons. One is a finite current-supply ability of the system power supply, and the other is the inevitable parasitic series resistance existing be-tween the node and the system power supply. In device simulation, however, when TLU occurs during the period of ns ns shown in Figs. 10 and 11, was not immediately pulled down to the dc latchup holding voltage. In-stead, keeps at the given underdamped sinusoidal voltage.
Fig. 12. Simulated 2-D current flow lines with respect to various transient timing points for TLU with a negativeV . Forward well (substrate) contact current appears when n-well/p-substrate junction is forward-biased (timing points A, B, and F), and TLU will be triggered on due to large enoughISb (timing points C-E, G, and H).
This fact results from the native limitation of device simula-tion tool for transient analysis in time domain. However, TLU is sure to occur because huge (150 mA, refer to Figs. 10, and 11) can be found when finally returns to its normal op-erating voltage, V. More importantly, it is consistent with the simulated latchup dc - characteristics that is 150 mA when keeps at its normal operating voltage, V, under a latchup state in Fig. 9.
To further judge whether TLU indeed occurs, Fig. 12 shows the corresponding simulated 2-D current flow lines with respect to various transient timing points with a negative . Clearly, large forward well (substrate) contact current appears when n-well/p-substrate junction is forward-biased (timing points A, B, and F). Once the n-well/p-substrate junction quickly changes from the forward-biased state to its original reverse-biased state, TLU will be triggered on due to large enough (timing points C-E, G, and H).
C. TLU Simulation With Positive
With a positive , Fig. 13 shows the simulated and transient responses on the SCR structure. During the period of ns ns, unlike the waveform with a neg-ative shown in Fig. 10 where begins decreasing rapidly at ns, starts to increase at ns and eventually reaches a positive peak voltage at ns. Within this duration, the n-well/p-substrate junction is always reverse biased, and thus only transient displacement current caused by n-well/p-substrate junction can be found within the SCR. Such displacement current will not cause TLU unless the frequency
Fig. 13. SimulatedV andI transient responses for TLU with a positive V . During the period of50 ns t 75 ns, TLU will not be triggered on by the n-well/p-substrate junction displacement current. Afterwards, during the period of87:5 ns t 112:5 ns, I will be produced to initiate TLU (I significantly increases) whenV increase from its negative peak voltage to the normal operating voltage,+2:5 V.
(amplitude) of is large enough to induce large enough dis-placement current [9]. Afterwards, decreases from its pos-itive peak voltage, at ns, to its negative peak voltage, at ns. Within this duration, n-well/p-substrate junction gradually changes from the reverse-biased state to the forward-biased state, while more and more minority electrons (holes) are injected into the p-substrate (n-well) region. Once these are subsequently ( ns ns) swept back to n-well (p-substrate) regions where they originally come from, TLU will be triggered on. As a result, will considerably increase during the period of ns ns. Obviously, TLU
Fig. 14. Simulated 2-D current flow lines with respect to various transient timing points for TLU with a positiveV . The n-well/p-substrate junction displacement current will not cause TLU (timing points A and B) until large enoughI is produced (timing points E-H).
is sure to occur because the huge (150 mA, refer to Figs. 9 and 13) can be found when eventually returns to its normal operating voltage of V.
Fig. 14 shows the simulated 2-D current flow lines with re-spect to various transient timing points with a positive . The n-well/p-substrate junction displacement current will not cause TLU (timing points A and B). However, large forward well (substrate) contact current will appear when n-well/p-sub-strate junction is forward-biased (timing points C and D), and then TLU will certainly be triggered on if is large enough (timing points E-H).
D. More Realistic Case
In real situation under the system-level ESD test, the oscil-latory resonance voltage can randomly occur at both and GND nodes [12]–[14], but not only at the node. With considerations of such a realistic situation, Fig. 15 shows the simulated , GND, and transient responses on the SCR structure. Obviously, once -to-GND voltage is negative
enough ( ns ns) to produce large enough
within the n-well/p-substrate junction, TLU can be easily triggered on afterwards when -to-GND voltage returns to a positive voltage ( ns ns). Because the power and ground lines are widely distributed over the whole circuitry in a chip, such oscillatory resonance voltage can appear on some core circuitry. This fact implies that TLU can occur within the core circuitry, but not only in I/O circuitry. Thus, unlike the quasi-static latchup issue [17] which primarily concerns about latchup immunity on I/O circuitry, the latchup prevention skills such as layout optimization with additional guard rings [18],
Fig. 15. SimulatedV , GND, andI transient responses for TLU under a more realistic situation.V and GND can be disturbed simultaneously by EMI under a system-level ESD test [12]–[14]. OnceV -to-GND voltage is negative enough (87:5 ns t 100 ns) to produce large enough I , afterwards TLU could be easily triggered on whenV -to-GND voltage returns to a positive voltage (100 ns t 112:5 ns).
other specific advanced process technologies, or even latchup self-stop circuit [19] may be necessary for the core circuitry to prevent TLU in CMOS ICs.
VI. EXPERIMENTALRESULTS FORTLU
The component-level TLU measurement setup in Fig. 7 is used to perform the TLU test. With both positive and negative , the measured transient response will be recorded through the voltage (current) probe to display on the oscilloscope. This will clearly indicate whether the TLU occurs ( significantly increases) when the absolute value of pos-itive or negative gradually increases from 0 V during
Fig. 16. Measured latchup dcI-V characteristic for the SCR structure.
the TLU test. More importantly, this will provide useful infor-mation for the comparisons between the TLU measurement and the device simulation. In addition, the specified SCR structure
with layout parameters of m, m, and
m fabricated in 0.25- m CMOS technology is used for all the TLU measurements in this paper.
A. Measured Latchup DC - Characteristics
The measured latchup dc – characteristic for the fabricated SCR structure is shown in Fig. 16. The inset figure in Fig. 16 indicates the dc latchup trigger voltage (current), , is about 19.5 V (2 mA), while the dc latchup holding voltage (holding current), , is about 1 V (9.5 mA). Through comparing these measured dc latchup parameters with the sim-ulated ones in Fig. 9, there is no large difference between the measured and the simulated dc latchup parameters. Thus, this noncalibrated device simulation tool is capable of performing the reasonable qualitative analysis to TLU.
B. TLU Measurement With Negative
With a negative of V, the measured and
transient waveforms on the SCR structure are shown in Fig. 17. Obviously, forward current appears due to the forward-biased n-well/p-substrate junction when initially decreases below 0 V. Afterwards, will greatly increase while returns to above 0 V, and therefore TLU does occur. As a result, both and waveforms are slightly oscillatory under a low-impedance (high-current) latchup state. Finally, will eventually be pulled down to about the dc latchup holding voltage ( V) with the huge ( mA) after this transition.
Through the comparisons between the experimental and the device simulation results in Figs. 10 and 17, the experimental results are consistent with the device simulation results in time domain. For example, TLU will be triggered on due to large enough while increases from - to its normal oper-ating voltage of V. This can once again verify that the large number of can trigger on TLU while they are quickly swept back to the regions where they originally come from.
Fig. 17. MeasuredV andI transient waveforms from the TLU test with a negativeV of05 V. It is consistent with the device simulation results in Fig. 10 that TLU will be triggered on (I significantly increases) whenV increase from its negative peak voltage to the normal operating voltage,+2:5 V.
Fig. 18. MeasuredV and I transient waveforms from the TLU test with a positiveV of+20 V. It is consistent with the device simulation results in Fig. 13 that TLU will not be initially (V > 0 V) triggered on by the n-well/p-substrate junction displacement current until large enoughI is produced whenV increases from its negative peak voltage to the normal operating voltage,+2:5 V.
C. TLU Measurement With Positive
With a positive of V, the measured and
transient waveforms on the SCR structure are shown in Fig. 18. begins to increase rapidly from the normal operating voltage ( V) to a positive peak voltage of V. Meanwhile, the n-well/p-substrate junction is reversed biased, and thus only transient displacement current caused by the n-well/p-substrate junction can be founded within the SCR. Such junction displacement current is too small to initiate TLU because doesn’t significantly increase when increases from the normal operating voltage ( V) to the positive peak voltage of V. Afterwards, once large enough is produced when increases from its negative peak voltage back to the normal operating voltage ( V), TLU will be initiated with large-increasing . Moreover, both and waveforms are slightly oscillatory under a low-impedance (high-current) latchup state. Finally, will eventually be
Fig. 19. Total stored minority carriers,Q , causingI (t t t ) inside the n-well region. The inset figure is an ideal 1-D diode used for deriving the 1-D analytical model of the averagedI ( I ) [15].
pulled down to about the dc latchup holding voltage ( V) with the huge ( mA) after this transition.
The physical mechanism of TLU under the system-level ESD test can be well proved once again by comparing the experimental results with the device simulation. As shown in Figs. 13 and 18, large enough caused by the instantaneously forward-biased n-well/p-substrate junction can trigger on TLU more easily than the reverse junction displacement current does.
VII. DISCUSSION
It has been clarified that the sweep-back current, , caused by the minority carriers stored within the parasitic pnpn struc-ture of CMOS ICs is the major cause of TLU under the system-level ESD test. Based on a simple 1-D analytical model of [15], the dominant parameter to initiate TLU can be identified. In addition, the minimum magnitude of the applied voltage to initiate TLU under different damping frequencies can be deter-mined by the device simulations. By combining these 2-D de-vice simulation results and the 1-D model of , the minimum or the minimum number of the total stored minority car-riers to initiate TLU can be also estimated. To further provide the evidence that is the major cause of TLU, the transient responses on the minority carriers stored within SCR are calculated.
A. Dominant Parameter to Induce TLU
As shown in the inset figure of Fig. 19, with the assumption that the n-well/p-substrate junction is treated as an ideal 1-D diode with step junction profile, a simple 1-D analytical model of the averaged [15] can be expressed as
(2) where is the initial (final) timing point of a specific dura-tion when exists, as shown in Fig. 19. represents the
Fig. 20. SimulatedV dependences on damping frequency(f). V is defined as the minimum magnitude of the negative applied voltage to initiate TLU.
total stored minority carriers (holes) causing inside the n-well region, which is given by
(3) From (2) and (3), can be further simplified as
(4) where
(5) is a constant and independent on damping frequency , ap-plied voltage amplitude , and damping factor . By
sub-stituting into (1), can be expressed
as
(6) From (4) and (6), it can be obviously identified that is dominant to (i.e., dominant to induce TLU), because there is not only a proportional exponential relationship between and in (6), but also a multiplication factor “ ” on in (4).
B. Minimum Applied Voltage Amplitude to Initiate TLU
The minimum to initiate TLU can be determined by the de-vice simulation results. For the underdamped sinusoidal voltage
are shown in Fig. 20. is defined as the minimum mag-nitude of the negative applied voltage to initiate TLU. Clearly, decreases with . This can be demonstrated by (2) where the higher (i.e., smaller - ) can initiate TLU by a smaller (i.e., smaller ), if the critical to initiate TLU is fixed. Thus, the critical value of , or to initiate TLU isn’t fixed but correlated with each other, because , and are all correlated with to determine the occurrence of TLU [20].
C. Minimum or to Initiate TLU
By combining the 2-D device simulation results and the 1-D analytical model of , the minimum or to ini-tiate TLU can be estimated. As shown in Fig. 20, for the un-derdamped sinusoidal voltage with of s and of 10 MHz, the minimum magnitude of the negative applied voltage to initiate TLU is 6 V. With this trigger condition, it can be calculated from (1) that
ns V. However, it is improper to directly apply such a high of 3.26 V into (3) to obtain , because the forward-biased p-substrate/n-well junction current is dom-inated by the parasitic series resistance effect at a high current state . As a result, the considering the parasitic series resistance effect of the p-substrate/n-well diode can be defined as and extracted from
(7) where is the distance perpendicular to direction of the ideal 1-D p-substrate/n-well diode, as shown in the inset figure of Fig. 19. With of about A/ m at K, of about 5 m (approximated from the 2-D SCR struc-ture in Fig. 6), and of A/ m from the simula-tion result, of 0.95 V can be calculated from (7). Thus,
with cm m at
K, ( V, and the assumption that the dis-tance between the depletion region edge and the contacts of 1-D p-substrate/n-well diode is much larger than the minority carrier diffusion length (i.e., ), the minimum to initiate TLU of C/ m can be calculated from
(3). With the known and - ns,
the minimum to initiate TLU of A/ m can
be calculated from (2).
D. Transient Responses on the Minority Carriers Stored Within SCR
To further provide the evidence that is the major cause of TLU, the transient responses on the minority carriers stored within SCR can be estimated from (3) by using to substitute for . For the underdamped sinusoidal voltage with
the same parameters ( , and of , 20 MHz,
V, respectively) as those in the case with negative of Figs. 10 and 11, the calculated transient responses of (hole) in the n-well region are shown in Fig. 21. Compared with the simulated TLU transient responses in Figs. 10 and 11, the minority carriers (holes) stored in the n-well region signif-icantly increases with forward well contact current ( ns
Fig. 21. Calculated transient responses ofQ (hole) in the n-well region. The underdamped sinusoidal voltage has the same parameters as those used in the negativeV case of Figs. 10 and 11 (D ; f , and V of 2 2 10 s , 20 MHz, and014:6 V, respectively).
ns) when decreases from 2.5 V to . Af-terwards, decreases because these minority holes are swept back to their original p-substrate region ( ns
ns). As a result, TLU will be triggered on by these swept-back , so the anode current will significantly increase ( ns ns). From Figs. 10, 11, and 21, the swept-back current can be confirmed as the major cause of TLU during system-level ESD stress.
VIII. CONCLUSION
The underdamped sinusoidal voltage stimulus has been clarified as the realistic TLU-triggering stimulus under the system-level ESD test. With the aid of device simulation, the specific “sweep-back” current caused by the minority carriers stored within the parasitic pnpn structure of CMOS ICs has been qualitatively proved to be the major cause of TLU. Through comparisons between device simulations and experimental measurements, TLU reliability issue may still exist in a quali-fied CMOS IC product through quasi-static latchup test. Thus, an efficient TLU measurement setup is needed to evaluate the TLU reliability of CMOS IC products. Because TLU reliability issue potentially exists within the whole circuitry of CMOS ICs, latchup prevention skills such as layout optimization, the specific advanced process technologies, or circuit technique may be necessary to improve TLU immunity for core circuitry. Through both the understanding of physical mechanism and the proposed simulation/verification methodology on TLU, the safe design/layout rules or circuit techniques in CMOS ICs can be developed against TLU events.
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of design houses or semiconductor companies in Hsinchu, Silicon Valley, San Jose, CA, Singapore, and Mainland China. His research interests include reliability and quality design for nanoelectronics and gigascale systems, and high-speed and mixed-voltage I/O interface circuits, especially sensor circuits, and on-glass circuits realized with TFTs.
Dr. Ker has also received many research awards from ITRI, the Dragon Thesis Award (by Acer Foundation), National Science Council, and National Chiao-Tung University. He has been a Member of the Technical Program Committee and as Session Chair of some International Conferences. He was elected as the first President of the Taiwan ESD Association in 2001. In 2003, he was selected as one of the Ten Outstanding Young Persons in Taiwan by Junior Chamber International (JCI).
Sheng-Fu Hsu (S’04) received the B.S. degree
from the Department of Engineering and System Science, National Tsing-Hua University, Hsinchu, Taiwan, R.O.C. in 2000, and the M.S. degree from the Institute of Electronics, National Chiao-Tung University, Hsinchu, in 2002, where he is currently pursuing the Ph.D. degree.
His current research interests include semicon-ductor device physics and IC reliability.
