o1 i2 1 o i2

L4: Sequential Building Blocks L4: Sequential Building Blocks (Flip

(Flip - - flops, Latches and Registers) flops, Latches and Registers)

Acknowledgements:

J. Rabaey, A. Chandrakasan, B. Nikolic. Digital Integrated Circuits: A Design Perspective.

Prof. Randy Katz (Unified Microelectronics Corporation Distinguished Professor in Electrical Engineering and Computer Science at the University of California, Berkeley) and Prof. Gaetano Borriello (University of Washington Department of Computer

Science & Engineering) from Chapter 2 of R. Katz, G. Borriello. Contemporary Logic Design.

Materials in this lecture are courtesy of the following sources and are used with permission.

2nd ed. Prentice-Hall/Pearson Education, 2005.

Prentice Hall/Pearson, 2003.

Combinational Logic Review Combinational Logic Review

ƒ Combinational logic circuits are memoryless

ƒ No feedback in combinational logic circuits

ƒ Output assumes the function implemented by the logic network, assuming that the switching

transients have settled

ƒ Outputs can have multiple logical transitions before settling to the correct value

Combinational Circuit

in₀ in₁

in_N-1

in₀ in₁

in_M-1

A Sequential System A Sequential System

ƒ Sequential circuits have memory (i.e., remember the past)

ƒ The current state is “held” in memory and the next state is computed based the current state and the current inputs

ƒ In a synchronous systems, the clock signal orchestrates the sequence of events

COMBINATIONAL LOGIC

Registers

Outputs

Next state

CLK

Q D

Current State Inputs

Memory element

A Simple Example A Simple Example

in₀ in₁

in₂

in_N-1

Adding N inputs (N-1 Adders)

in

D Q

reset

clk

Current_Sum

Using a sequential (serial) approach

Implementing State: Bi

Implementing State: Bi - - stability stability

V_i1

A

C

B

V_o2

V_{i 1}= V_o2

V_o1 V_i2

V_{i 2}= V_o1

V

= V

V

= V

Point C is

Metastable

Vi2=Vo

V_i1 = V _o2 A

δ Vi2=Vo1

V_i1 = V_o2 C

δ

1

Points A and B are stable

(represent 0 & 1)

B

NOR NOR - - based Set based Set - - Reset (SR) Reset (SR) Flipflop Flipflop

ƒ Flip-flop refers to a bi-stable element

(edge-triggered registers are also

“asynchronously” with the inputs

Q Q Q Q

Q Q

0 1 1 0

0 0 SR = 1 0

SR = 0 1 SR = 0 1

SR = 1 1

SR = 1 0

SR = 1 1

SR = 00, 01 SR = 00, 10

SR = 0 0

SR = 11

SR = 0 0

Reset Hold Set Reset Set

R S Q

Q

??

Forbidden State S

S R

Q

Q

Q S R Q

Q 0

0

1 0

1

0 1

0

0 1

1

R Q

Q Q 0 1 0

Making a Clocked Memory Element:

Making a Clocked Memory Element:

Positive D

Positive D - - Latch Latch

CLK

D Q

D Q

clk

ƒ A Positive D-Latch: Passes input D to output Q when CLK is high and holds state when clock is low (i.e., ignores input D)

ƒ A Latch is level-sensitive: invert clock for a negative latch S

R

clock R and S

sample hold sample hold hold

G

Multiplexor

Multiplexor Based Positive & Negative Latch Based Positive & Negative Latch

1 in

0

in

out

SEL

Out = sel * in

+ sel * in

2:1 multiplexor

1 0

D Q

CLK

Positive Latch

0 1

D Q

CLK

Negative Latch

"remember"

"load"

"data" "stored value"

clk

clk

74HC75 (Positive Latch) 74HC75 (Positive Latch)

2 13

1D 1Q

2Q

3Q

4Q 16 LE1-2

LE3-4

1Q

2Q

3Q

4Q 1

D CP

CP

CP

CP L2 L1

L3

L4 Q

Q

Q

Q 3 2D

3D

15

14

6 4

7 4D

10

11

9

8 Q

D Q

D Q

D Q

Operating Modes Inputs Outputs

LEn-n nD nQ nQ

Data Enabled Data Latched

H

H H L

L X q q

L

H L H

Figures by MIT OpenCourseWare.

Building an Edge

Building an Edge - - Triggered Register Triggered Register

„

Master-Slave Register

†

Use negative clock phase to latch inputs into first latch

†

Use positive clock to change outputs with second latch

„

View pair as one basic unit

†

master-slave flip-flop twice as much logic

1 D 0

Master

0 1

Q

Slave

Q_M Q_M

Q D CLK

D G

Q D

G Q

CLK CLK

CLK CLK

D Q D D Q Q

Q_M

Negative latch Positive latch

Image by MIT OpenCourseWare.

Latches vs. Edge

Latches vs. Edge - - Triggered Register Triggered Register

Edge triggered device sample inputs on the event edge Transparent latches sample inputs as long as the clock is asserted

Timing Diagram:

Behavior the same unless input changes while the clock is high

7474

7475

Bubble here for negative edge triggered

register

Positive edge-triggered register

Level-sensitive latch

D Q

D Q C

Clk

Clk

D

Clk Q

Q

7474

7475

Important Timing Parameters Important Timing Parameters

Setup Time (T

) Clock:

Periodic Event, causes state of memory element to change

memory element can be updated on the:

rising edge, falling edge, high level, low level

There is a timing

"window" around the clocking event

during which the input must remain

stable and

unchanged in order to be recognized There is a timing

"window" around the clocking event

during which the input must remain

stable and

unchanged in order to be recognized

Minimum time before the clocking event by which the input must be stable

Hold Time (T

)

Minimum time after the clocking event during which the input must remain stable

Input Clock

T _su T _h

Propagation Delay (T

for an edge-triggered register and T

for a latch)

Delay overhead of the memory element

The J

The J - - K Flip K Flip - - Flop Flop

„

Eliminate the forbidden state of the SR Flip-flop

„

Use output feedback to guarantee that R and S are never both one

J K Q+ Q+

0 1 0 1

Q 0 1 Q

0 Q

0 1

1 0

1 Q

J K Q

\ Q

100

S

R

Q

Q J

K

J J - - K Master K Master - - Slave Register Slave Register

Correct Toggle Operation

Master outputs Slave outputs

Set Reset T oggle

1's

S R

Q

Q J

K

S R

Q

Q

Sample inputs while clock high Sample inputs while clock low

P

P

Catch 100

J K Clk

P

\ P Q

\ Q

Is there a problem with this circuit?

CLK

J K

Q

φ Q

Pulse Based Edge

Pulse Based Edge - - Triggered J Triggered J - - K Register K Register

S R

Q Q J

K

φ

J

K

Q φ Q

JK Register Schematic

JK Register Logic Symbol

Input

φ

Output

Input

X

Output

t_pLH

X

φ

Schematic

Pulse

Pulse - - Triggered Registers Triggered Registers

Ways to design an edge-triggered sequential cell:

Pulse-Based Register Master-Slave Latches

D Clk

Q D

Clk Q

L1 L2

Clk

Data D

Clk Q

Latch

Data Clk

Short pulse around clock edge

ƒ Pulse registers are widely used in high-performance

microprocessor chips (Sun Microsystems, AMD, Intel, etc.)

ƒ The can have a negative setup time!

D Flip

D Flip - - Flop vs. Toggle Flip Flop vs. Toggle Flip - - Flop Flop

T

Clk Q

T (Toggle) Flip-Flop

0 1

1 1

0

T Q

0 Q

1 Q

0

D

Clk Q

D Flip-Flop

0 1

0 1

0

D Q

0 0

1 1

1

Realizing Different Types of Memory Realizing Different Types of Memory

Elements Elements

Characteristic Equations

D:

J-K:

T:

Q+ = D

Q+ = J Q + K Q Q+ = T Q + T Q

E.g., J=K=0, then Q+ = Q J=1, K=0, then Q+ = 1 J=0, K=1, then Q+ = 0 J=1, K=1, then Q+ = Q

Implementing One FF in Terms of Another

D implemented with J-K J-K implemented with D

D

J J K

K C

Q Q

C

D Q

Q

Q

Design Procedure Design Procedure

Excitation Tables: What are the necessary inputs to cause a particular kind of change in state?

Implementing D FF with a J-K FF:

1) Start with K-map of Q+ = ƒ(D, Q)

2) Create K-maps for J and K with same inputs (D, Q) 3) Fill in K-maps with appropriate values for J and K

to cause the same state changes as in the original K-map

E.g., D = Q= 0, Q+ = 0 then J = 0, K = X

D

0 1 0 1 Q + = D

0 1 0

1 Q

D

X X 1 0

K = D 0 1 0

1 Q D

0 1 X X

J = D 0 1 0

1 Q

D 0 1 0 1 T

0 1 1 0 Q ⁺

0 1 0 1 Q

0 0 1 1

K X X 1 0 J 0 1 X X

Design Procedure (cont.) Design Procedure (cont.)

Implementing J-K FF with a D FF:

1) K-Map of Q+ = F(J, K, Q)

2,3) Revised K-map using D's excitation table

its the same! that is why design procedure with D FF is simple!

Resulting equation is the combinational logic input to D

to cause same behavior as J-K FF. Of course it is identical to the characteristic equation for a J-K FF.

0 0 1 1

1 0 0 1 00 01 11 10

J

K JK

Q

Q

= D = JQ + KQ 0

1

System Timing Parameters System Timing Parameters

D

Clk

In Q

Combinational

Logic

D

Clk Q

Register Timing Parameters

T

: worst case rising edge clock to q delay

T

: contamination or minimum delay from clock to q

T

: setup time T

: hold time

Logic Timing Parameters

T

: worst case delay

through the combinational logic network

T

: contamination or minimum delay

through logic network

System Timing (I): Minimum Period System Timing (I): Minimum Period

D

Clk

In Q

Combinational

Logic

D

Clk Q

CLK

T_su T_h

T_su T_h

T_cq

T_cq,cd

T_cq

T_cq,cd

FF1

IN

CLout

CLout

T_l,cd T_su2

T_logic

T > T

+ T

+ T

System Timing (II): Minimum Delay System Timing (II): Minimum Delay

D

Clk

In Q

Combinational

Logic

D

Clk Q

CLK

T_su

T_h T_h

T_cq,cd

FF1

IN

CLout

T_l,cd

T

+ T

> T

CLout

Shift

Shift - - Register Register

all measurements are made from the clocking event that is,

the rising edge of the clock

„

Typical parameters for Positive edge-triggered D Register

5nsTh

Tw 25ns 25nsTplh 13ns

40nsTphl 25ns 20nsTsu

D

CLK

Q

20nsTsu Th 5ns

IN Q0 Q1 CLK

100

CLK

IN Q0 Q1

DQ DQ OUT

„

Shift-register