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### (Flip--flops, Latches and Registers)flops, Latches and Registers)

Acknowledgements:

J. Rabaey, A. Chandrakasan, B. Nikolic. Digital Integrated Circuits: A Design Perspective.

Prof. Randy Katz (Unified Microelectronics Corporation Distinguished Professor in Electrical Engineering and Computer Science at the University of California, Berkeley) and Prof. Gaetano Borriello (University of Washington Department of Computer

Science & Engineering) from Chapter 2 of R. Katz, G. Borriello. Contemporary Logic Design.

Materials in this lecture are courtesy of the following sources and are used with permission.

2nd ed. Prentice-Hall/Pearson Education, 2005.

Prentice Hall/Pearson, 2003.

(2)

in0 in1

inN-1

in0 in1

inM-1

(3)

(4)

in0 in1

in2

inN-1

in

reset

clk

(5)

Vi1

A

C

B

Vo2

Vi 1= Vo2

Vo1 Vi2

Vi 2= Vo1

o1

i2

o2

i1

Vi2=Vo

Vi1 = V o2 A

δ Vi2=Vo1

Vi1 = Vo2 C

δ

1

B

(6)

### NORNOR--based Setbased Set--Reset (SR) Reset (SR) FlipflopFlipflop

 Flip-flop refers to a bi-stable element

### (edge-triggered registers are also

called flip-flops) – this circuit is not clocked and outputs change

### “asynchronously” with the inputs

Q Q Q Q

Q Q

0 1 1 0

0 0 SR = 1 0

SR = 0 1 SR = 0 1

SR = 1 1

SR = 1 0

SR = 1 1

SR = 00, 01 SR = 00, 10

SR = 0 0

SR = 11

SR = 0 0

Reset Hold Set Reset Set

R S Q

Q

### ??

Forbidden State S

S R

Q

Q

Q S R Q

Q 0

0

1 0

1

0 1

0

0 1

1

R Q

Q Q 0 1 0

(7)

### R

clock R and S

sample hold sample hold hold

(8)

0

1

1

0

### Negative Latch

"remember"

"data" "stored value"

(9)

### 74HC75 (Positive Latch)74HC75 (Positive Latch)

2 13

1D 1Q

2Q

3Q

4Q 16 LE1-2

LE3-4

1Q

2Q

3Q

4Q 1

D CP

CP

CP

CP L2 L1

L3

L4 Q

Q

Q

Q 3 2D

3D

15

14

6 4

7 4D

10

11

9

8 Q

D Q

D Q

D Q

Operating Modes Inputs Outputs

LEn-n nD nQ nQ

Data Enabled Data Latched

H

H H L

L X q q

L

H L H

Figures by MIT OpenCourseWare.

(10)











### master-slave flip-flop twice as much logic

1 D 0

Master

0 1

Q

Slave

QM QM

Q D CLK

D G

Q D

G Q

CLK CLK

CLK CLK

D Q D D Q Q

QM

Negative latch Positive latch

Image by MIT OpenCourseWare.

(11)

### Latches vs. Edge--Triggered Register Triggered Register

Edge triggered device sample inputs on the event edge Transparent latches sample inputs as long as the clock is asserted

Timing Diagram:

Behavior the same unless input changes while the clock is high

7474

7475

Bubble here for negative edge triggered

register

Positive edge-triggered register

Level-sensitive latch

D Q

D Q C

Clk

Clk

D

Clk Q

Q

7474

7475

(12)

su

### Periodic Event, causes state of memoryelement to change

memory element can be updated on the:

rising edge, falling edge, high level, low level

h

Input Clock

T su T h

cq

dq

(13)





J K Q+ Q+

J K Q

\ Q

100

(14)

### JJ--K MasterK Master--Slave RegisterSlave Register

Correct Toggle Operation

Master outputs Slave outputs

Set Reset T oggle

1's

### Q

Sample inputs while clock high Sample inputs while clock low

Catch 100

J K Clk

P

\ P Q

\ Q

(15)

S R

Q Q J

K

φ

### Q φ Q

JK Register Schematic

JK Register Logic Symbol

Input

X

Output

tpLH

φ

Schematic

(16)

(17)

### D Flip--Flop vs. Toggle FlipFlop vs. Toggle Flip--Flop Flop

T

Clk Q

T (Toggle) Flip-Flop

N

N-1

N-1

D

Clk Q

D Flip-Flop

N

(18)

## ElementsElements

### Characteristic Equations

D:

J-K:

T:

Q+ = D

Q+ = J Q + K Q Q+ = T Q + T Q

E.g., J=K=0, then Q+ = Q J=1, K=0, then Q+ = 1 J=0, K=1, then Q+ = 0 J=1, K=1, then Q+ = Q

### Implementing One FF in Terms of Another

D implemented with J-K J-K implemented with D

(19)

### Design ProcedureDesign Procedure

Excitation Tables: What are the necessary inputs to cause a particular kind of change in state?

Implementing D FF with a J-K FF:

2) Create K-maps for J and K with same inputs (D, Q) 3) Fill in K-maps with appropriate values for J and K

to cause the same state changes as in the original K-map

E.g., D = Q= 0, Q+ = 0 then J = 0, K = X

D

0 1 0 1 Q + = D

0 1 0

1 Q

D

X X 1 0

K = D 0 1 0

1 Q D

0 1 X X

J = D 0 1 0

1 Q

D 0 1 0 1 T

0 1 1 0 Q +

0 1 0 1 Q

0 0 1 1

K X X 1 0 J 0 1 X X

(20)

### Design Procedure (cont.)Design Procedure (cont.)

Implementing J-K FF with a D FF:

1) K-Map of Q+ = F(J, K, Q)

2,3) Revised K-map using D's excitation table

its the same! that is why design procedure with D FF is simple!

Resulting equation is the combinational logic input to D

to cause same behavior as J-K FF. Of course it is identical to the characteristic equation for a J-K FF.

+

(21)

D

Clk

In Q

D

Clk Q

cq

cq, cd

su

h

logic

logic,cd

(22)

D

Clk

In Q

D

Clk Q

Tsu Th

Tsu Th

Tcq

Tcq,cd

Tcq

Tcq,cd

Tl,cd Tsu2

Tlogic

cq

logic

su

(23)

D

Clk

In Q

D

Clk Q

Tsu

Th Th

Tcq,cd

Tl,cd

cq,cd

logic,cd

hold

(24)

### Shift--RegisterRegister

all measurements are made from the clocking event that is,

the rising edge of the clock



### Typical parameters for Positive edge-triggered D Register

5nsTh

Tw 25ns 25nsTplh 13ns

40nsTphl 25ns 20nsTsu

D

CLK

Q

20nsTsu Th 5ns

IN Q0 Q1 CLK

100

CLK

IN Q0 Q1

DQ DQ OUT



### Shift-register

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Given a sample space  and an event  in the  sample space  , let

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The min-max and the max-min k-split problem are defined similarly except that the objectives are to minimize the maximum subgraph, and to maximize the minimum subgraph respectively..

1 camera sample and 16 shadow samples per pixel. 16 camera samples and each with 1 shadow sample

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