A high performance spread spectrum clock generator using two-point modulation scheme

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(1)IEICE TRANS. ELECTRON.,. VOL.E91-C,. NO.6 JUNE 2008 911. PAPER. Special Section on Analog Circuits and Related SoC Integration Technologies. A High. Performance. Two-Point. Spread. Modulation. Spectrum. Clock. Generator. Scheme Yao-Huang. SUMMARY. A. two-point the. divider. lated.. but. technique. can. of EMI. can. the. posed. SSCG. such. has. the. and. jitter. peak EMI reduction is 0.90•~0.89mm2.. total in. spread. for. loops. order ƒ°ƒ¢. a 0.35ƒÊm. CMOS. the case. (PLLs),. be. and. to. that. In. adthe pro-. The. clock The. size. area. spectrum,. of chip. and. Members. the. are verified.. The. HSIEH•õ•õ,. and. The. process.. Yi-Bin. only. reduce. achieved.. 2.5%. of 2.5%.. spread. so. filter. and. modu-. profile.. loop can. of 1.25%. is. modulator. modulation the. KAO•õa). using Not. oscillator. integration. ratios. is 19.73dB. phase-locked. the to. paper.. bandwidth. lower. is applied. (SSCG). this. modulation. the. the. generator in. controlled. with. fabricated. center. clock presented. voltage. enhance. that. been. with. words:. the. of two-path. value. of 400MHz. is. is improved. optimize. method. capacitance. spectrum. also. suppression. simultaneously. dition,. key. spread modulation. is varied,. This. effect. new. delta-sigma. Using. two point,. fractional-N. Fig. 1 1.. diagram Spread-spectrum widely. clock. employed. levels. [1]-[10].. (PLL). with. two. as. [7]. and former. is. the. other. is. used. modulation. profile is. save. tooth. the. been. this ter. .. power,. in. the of. an. to. the. meantime,. the. two-point. In. being by is. trian-. traded by. wide. enough, of. off. the suptri-. improve. the. method. enhance. the. mod-. of. a two-. bandwidth. maintain. the. and. linear. is. used transfer. noted in. the. gain. frequency. function. technique to. that. is the. generator. appears employed. high. data. modulation. as. all-pass. in. a frequency. rate. modulation. with. in. hopping [11].. feature.. transmitblock. Manuscript received October 17, 2007. Manuscript revised December 20, 2007. The author is with the Department of Communication Engineering, Chung-Hua University, Hsin-Chu, Taiwan 300. The author is with the Institute of Communication Engineering, National Chiao-Tung University Hsin-Chu, Taiwan 30050. a) E-mail: yhkao@chu.edu.tw DOI: 10.1093/ietele/e91-c.6.911 Copyright (c). 2008 The Institute. two. due. adder. is. to the. high. and. large. needed. modulation [11].. clock. to. com-. paths. This. In. this. the. study,. and. the. suffer. will. make. also. a kind. The. Conclusions. the. given. for. with. the. (TPDL). is. the ƒ°ƒ¢. circuits. results last. filter. and total integration. SSCG and the linear. CMOS. in the. of. modulation. SSCG. loop. consideration. results.. measurement. are. point. a modified. a dual-path. design. simulation. is. two. achieve wide bandwidth 2 describes the proposed. analysis,. 3.. generator. Therefore,. modulation. Sect.. an. The. spectrum. applied.. and. time,. and. resolution. consumption. mismatch. modulation.. presented to Section. in. delay. spread. be. lator. mean. a high. performance power. signals.. and. Usually. complicated.. two-point. model. high. in Fig. 1 divider. are. are. modu-. described. verified. in. Sect.. 4.. section.. 2.. Proposed. For. a typical. TPDL-SSCG. has. Recently,. The. can. the. VCO.. better. to. is shown. multi-modulus. saw-. PLL. DC-FM. behavior.. gain. frequency. the ƒ°ƒ¢. EMI. In path. more The. of the. leads. [11]. of the. to achieve. two. the. fully a. caused. from design. pre-distorted. to. alternative. presented. the. modulation input. input. It. penalty.. of. effect. gain.. area. [8].. at the. is needed. VCO. bine. modulator. two-point. at the. [1]-. directly. using. presented. DAC. are. other. PLL. bandwidth. and. loop. the. point. within. a ƒ°ƒ¢. not. the. one. divider. controlled. is. method. Here,. the. jitter. EMI. There. advantage. and. been. locked. of. with. waveform. It. Its. The. is. with. loop. distorted. has [10]. VCO. bandwidth. is. modulation. the. is. The. loop. degraded.. profile. point to. the. of. PLL the. profile. waveform. ulation. has. phase. employed. variation. modulator. modulation As. angular. It The. modulator.. a. been. reduced. modulation.. modulate. generator.. the. pression. to. [1]-[7].. waveform. between. is. techniques the. have. with. frequency. a fractional-N. controlled.. gular. of. control. case,. mostly. digital. sources SSCG. case. to. (SSCG). high-speed. modulation. One. the. generators. Basically, special. common. loops.. is. The Traditional TPDSM architecture [9].. Introduction. of Electronics,. PLL,. the. divider. to the. On. contrary,. the. to VCO. output. behaves. function. can. the. VCO. be. simultaneously is. independent. of. the. a phase-frequency an. modulator,. Information. the. loop. a modulation. is. a dual. and Communication. in. path. (PGC),. generator,. Engineers. input all-pass. is excited modulation. The. shown. counter profile. loop The. bandwidth.. (PFD),. programmable. VCO An. the. points.. TPDL-SSCG. feedback function.. the. function.. when. two. the. a low-pass from. pass. hopefully. detector. 8-bit. a high. these of. proposed. from. as. function. as. through. gram. function. behaves. transfer. obtained. speed. VCO,. transfer. output. block Fig. loop. dia2 with. filter,. a. a digital ƒ°ƒ¢ and. a digital. to.

(2) IEICE TRANS. ELECTRON.,. 912. Fig. 3. Fig. 2. The block. diagram. of the proposed. waveform.. converts converter. sists. of. (DAC).. charge. resistor. R1,. and. loop. The. of. C1. than. the. smaller to. generate. ital ƒ°ƒ¢. the. are. current. of. the. the. PGC. input behavior. acts. in the. 2.1. The. Proposed. The. proposed. The. digital. fed. Vx and. the ƒ°ƒ¢. well. Vy.. Point. feature. combine. C1.. minal. is. DAC. of. the. The. two. as ƒ¢Fout/Fout. profile. charges the. generator and. DAC.. The. form. can. tion. filter. into. discharges. a digital. digital. slicer,. triangular. be. C1. area. one.. are. resolution. profile clock, put. Therefore,. greatly generator Fbk, which. of. the. waveform. the. reduced. and is. digital very. the the. slicer well. In. as. the. where. operations. and. to. out. without as. C1.. to. the. and. digital. effects. controlled. voltage. Fout. the the. condition. tracked delay. with mismatch. in. CP1. Vc and. and the. chip. peak. to peak. frequency. 2.2. Linear. defined. frequency,. triangular. Fsig. waveform. is the. modula-. and ƒ¢Fout. is. the. the. waveform. created. proposed shown. architecture in. are. Fig.. 3.. Kd. is. analyzed. the. conversion. gain. of. by. the. PFD. charge divider. pump. and. value. is. Kvco N.. Gm. is is. the. gain. gain. of. for. flat. com-. the. delay. factor. VCO.. pensation. between. two. mismatch. is ignored. modulation. as. points.. mentioned. Here. filter the. transfer. current. function.. above.. of. CP2. of. Ip1. is. F(s). the. is dual-path. Let Ip1=BIp2.. the. filter. can. be. current. of. Here. B=4.. written. CP1,. Ip2 The. as. triangular. between. CP2,. (3). two. the. re-. current Ip3. From. of. According is. the as. trans-impedance. (1). Fsig•á1/(2ƒÎR1C2).. deviation.. Analysis. of model. The. of CP2. be. of. the. Model. dynamics linear. and. is. as. triangular. The. is. the same the out-. 1. analog. which. gate-. [15].. (2). output. of. In. as Ip3. to is. a. (3), other. reduced. by. The. unity. examined.. (1),. ratio ƒÂ,. 1V. the. as. is nominal. frequency. operational. under. MOS. when. than. ter-. the. slicer,. the. be the. between. Vc. spreading. is derived. tion. The. a reconstruc-. can. lation. written. larger. to. one. accumulation. distortion. or. with. clock. compared. use PGC,. avoided. the loading. be. and. to. In this adder. wave-. consumption. addition,. can be Ignoring. can. the. C1. an. perform. in triangular. DAC power. points. CP3. by. equal. filter.. or. It. analog. from. digital. CP3. digital ƒ°ƒ¢ modulator output signal of the. so that. is. of loop VCO. Here. to reduce. role. into. δ=Ip3Kvco/2C1FsigFout.. loop traditional. voltage. between Ip3. point. long. CP3,. The the. resided. smoothed. a high. inputs. signals.. and. important signal. overall. waveform. clock.. through. transitions. effectively. and. a digital the. digital. as a part. two. is implemented area. an. at. the the. bias. acts. the. modulation. to save. source. also. plays. modulation. paragraphs.. consists slices. two. C1. digital. but. grounded. relation. Vx is. the. eliminate. the. dig-. and. The. can. capacitor. DAC. slicer. of the TPDL-SSCG.. Capacitor. only signal,. we. the. The as. matched.. way,. the. is used. into. DAC.. a. CP2. modulator the. all-pass. following. area. current. simultaneously.. through. an. of. not. modulation. and. generator be. con-. C2,. benefit. the. profile. by. are. [12]. C1,. capacitance. to. DAC,. VCO. schemes. analyzed. The. through. of the. modulation. the while. denotes. filter. The. diminish. waveform. are. loop. capacitors. reduced CP1.. and. points. modulation two. be. modulator. at the. CP2,. amplifier.. is to. could. triangular. input. Vy is. filter. the. modulation. dual-path. CP1,. a unity-gain. dual-path area. The. pumps. model. NO.6 JUNE 2008. TPDL-SSCG. square. analog. Linear. VOL.E91-C,. frequency ƒÖt. amplifier. the. zero. is lowered. words, the. the. factor. gain. amplifier.. Then,. 1/(BC1)R1 of. B. It is a favor. amplifier The. It is modeled. is described. to. magnitude. by the as. with. capacitance for. total. implemented non-ideality its. transfer. DC. gain function. aid can. integration.. by of. the C1. a one-stage. the. amplifier. Av and. its. of. the. is. unity-gain unity. gain.

(3) KAO and HSIEH: A HIGH PERFORMANCE. SPREAD SPECTRUM. CLOCK GENERATOR. USING TWO-POINT. MODULATION. SCHEME 913. Aerr/. A(S)=. (4). S/ƒÖt.. where. Sƒ³vco(f). and. 1 +. the ƒ°ƒ¢. found. and. Sƒ³ƒ¢ƒ°(f). modulator,. are. the. noise. respectively.. PSDs. of the. Sƒ³ƒ¢ƒ°(f). [14]. VCO can. be. as. as Aerr=Av/(Av+1) denotes the gain error. By using (4) and re-calculating F(S), one can obtain. (8) Where. m. tional. (5) when ƒÖt•â1/(R1C2). the. gain. tle. higher. will. than. Gm. is. cause. the. the. difference. the. gain. to. (3),. it is clear. will. Vy.. not. the. which. The. depend. analog. on. from. of. process. triangular. of. can. be. on. match. factor. process. variations.. may. Here. the. come. easily. tri-. variations,. frequency. to (2),. the Ip3,. C1. but. will. relationship. the. and. of. frequency. relationship. modulation. is. de-. gain. mis-. general. the. frequency. ous.. From. the ƒ°ƒ¢ with. for. used. frequency. in. traditional. deviation. of. PLL. output. instead. of. the. the. Fout. ƒÖsig. nal. to. Fsig.. derived. The. be. the. closed. frequency loop. na-. is is. the. of. transmit. function. of. Fig.. be. as. the. the. =T(S)+(1-T(S))×Gm. pass. with. (6). NS+KvcoKdF(S). hand. side. appears. is. and. second. term. considered. as. appears. as. a low-passed. a high. pass. behavior.. as. as. a low. F(S). From. equal. to ƒÖsig. if. Gm=1.. It. means. that. is. very. between wide. two. and. gives. modulation rise. to. low. in. there the. distortion. closed. comparthe. spuri-. caused. of the. PLL. In. lower. bandwidth. other. the. by. bandwidth. characteristic. T(f).. the. the. words,. noise. bandwidth. the. is caused. loop. and. jitter. profile.. is. needed. Otherwise,. to. bandwidth. the. is traded. performance.. off. In. jitter. between. a conventional. based. SSCG. to be ten. times. performance fractional to. output. of. the. loop. the. bandwidth. be. shrunk. Hence,. jitter.. In. jitter. this. Bereduce. other. more. words,. area.. two-point. for. loop. third-order. further. jitter.. in. in. a 70kHz. to. and. nature. the and. needed. PLL. performance.. by noise. and. pass. can. and. is. noise. needs. to get better. EMI. phase. filter. distortion.. modulator. better. consumption. all. one. suppressed. the. phase. power to. profile. (5). minimize. band. [4], frequency. then. are. loop. higher. thanks. and spur. a third-order. it needs. (FN-SSCG) modulation. How-. modulation, without. study,. modula-. a second-order. bandwidth. with. a second-. (6), ƒ¢ƒÖout. if. points,. opera-. Sƒ³vco(f). PLL. of the. large. the. in-band. are. loop. filter. are. designed. for. saving. power. and. area.. no The. mismatches. (6).. PSD. of the pass. of is,. Thus,. The. order is. the. avoid. output. outside. modulation. modulation. tion pass. the. to high. profile. fractional-N. ever,. right. due. However, the. degraded.. the. KvcoKdF(S)/. the. the. than to. inside. bandwidth. faithfully. sides,. in. that. decreasing. modulator.. less. detector. characteristic. loop. modulator. term. realized. f2(m-1) and. to low-pass. ωsig. first. in. is is. sig-. 3 can. Δ ωout/. The. defined. is much phase. is increasing. shape. bandwidth. T(S)=. T(f). (9). at the. It is. modulator. smaller. is. assumed. deviation. transfer. PLL. bandwidth. Fbk. modulation conceptually. the. Fbk. and. phase. analysis. ƒ¢ƒÖout. signal. modulator,. as. loop. (8),. the. due. KVCO.. derived. in SSCG. of. derived. ison. by ture. the. modulator. SΦVCO(f)=SΦvn・￨1-T(f)￨2. the. digital. waveform. According from. of the. function. modulator pends. order. a lit-. comes. amplitude. the. transfer. that. multiplication. factor. Vx and. of. loop. In. mismatch. waveform. amplitude. (5). capacitance. expected.. between. angular the. Comparing. error. is. frequency. simulation. results. of. frequency. variation. for. dif-. bandwidth. in. the. ferent. output. loop. ulation. bandwidths. are. parameters. listed. shown in. in. Table. Fig.. 1.. 4 with. The. loop. center. sim-. is. set. at. signal. 400MHz, 2.3. Design. Two. Consideration. important. issues. modulator and. the. loop. that. the. Here,. the in this. fractional. Sigma-Delta. taken. One. is the. known. suppress. are. design.. other. already. for. into. is. account order. bandwidth high. a second. regarding of. of the. order ƒ°ƒ¢. spurious. design,. the. Modulator. the. PLL.. As. order ƒ°ƒ¢. the. we. to. bandwidth.. modulator. and. posed. spread. set. at. for. the. a, the. FN-SSCG. save. the. the. noise. order. area. and. power. performance.. of. the ƒ°ƒ¢. To. modulator. while. maintain. see. the. interrelation. the. PLL. loop. SSCG. with. SSCG. with. quality. phase. investigated. the. phase. noises The. noise. from noise. at the. PLL. the. modulator. between bandwidth,. power. spectral. output. Sƒ³(f). and. the. densities can. be. the the. more. ΔΣ(f). with. with. for. of. the. pro-. FN-SSCG.. 2.667%,. a 70kHz. a 400kHz. a 70kHz. BW. a 400kHz. Four. 2.588%,. BW. denoted. denoted. BW. VCO (PSD). expressed. It is clearly. accurate. to curve-b. and. denoted. curve-. curve-b,. curve-c,. denoted. and. curve-d. the. TPDL-. the. TPDL-. are. obtained,. spread. indicated. because. the. two. ratio,. but. that. curve-b. point. has. modulation. also. curve-c. lower. has. noise. not. smaller ƒ°ƒ¢. with. only. noise. is adopted. for. than. curve-b.. respect curveThere. are of as. is. a 0.18%. widths while. SΦ(f)=SΦVCO(f)+SΦ. bandwidths. account. conventional. 2.487%,. FN-SSCG. loop to. fre-. of. c and output. the of. modulation. is chosen. the. and. ratios. the. with. considered. and. spread. and. Cases. are. TPDL-SSCG. 2.598%. is 2.5%,. 40kHz.. 400kHz. respectively. to. ratio. have. is used. loop. is. 70kHz. different. modulator. modulator. within. the. quency. the. (7). difference. changed there. TPDL-SSCG.. from. is only And. in. spread. 70kHz 0.01% one. ratios. for. to 400kHz difference. more. effect. PLL for. in is. the. spread seen. loop. ratios from. band-. FN-SSCG,. Fig.. for. the. 4 that.

(4) IEICE. TRANS.. ELECTRON.,. VOL.E91-C,. NO.6. JUNE. 2008. 914. the bigger loop bandwidth and the larger jitter appear at the output for both architectures. This confirms the results in (8). The proposed TPDL-SSCG has the advantages of low distortion so that the modulation profile is more like a triangular waveform. The numerical results of phase noise for curve-b and curve-c in Fig. 4 in non-spread spectrum mode are shown in Fig. 5. Here, noise sources from CP1, CP2, reference. clock,. and. filter is. are. the. assumed. with. as. the. sent. of. total. bandwidth. noises. same. SSCG. and. circle. mark. and. noise. from. the. the. and. the. square. with. 1. Simulation. parameters.. with. respectively.. line. a. The. the. FN-SSCG. with. diamond. and mark. Fig.. noise. the. VCO's. dominated. the ƒ°ƒ¢. The. the. loop. 15.80ps. and. that. of. first,. be. used. the. for. minimized jitter the. same. the. VCO. can't. chip. area,. smaller way,. one. phase. jitter. can. can. further. noise. minimized. dominated. is. for. any. phase. lower and. noise. more in. the. FN-. loop. can. filter.. obviously. be. order third, be. for. second-. to. third-order. the. to. jitter. and. modulator. second,. and the. phase. TPDL-SSCG. order ƒ°ƒ¢. By. rms. the. FN-SSCG. compared. and. proposed. smaller. profile. multaneously.. the. the. for 1kHz. the. modulator. 5, the. in-band. from for. The. modulator. consumption,. modulation. because. almost. in. out-of-band. 15.96ps. second-order. a lower. power can. is. noise. in. integrated. respectively.. third-order. advantage. while. jitters. with. filter. with. phase. noise. phase. TPDL-SSCG,. seen. by. phase. rms are. The. ter. by. modulator's. TPDL-SSCG. lower Table. line. FN-. in in-band the phase. SSCG bandwidths. the. are. the. From. order. loop. for. noise while. the. PLL. phase. respectively.. and. for different. are. The. modulator. by. for the. loop. the VCO phase TPDL-SSCG;. 14.31818MHz. frequency. by. 1.. VCO. mark,. modulator. denoted. a 70kHz. the ƒ°ƒ¢ the. denoted. plus. repre-. a 400kHz. by the. FN-SSCG.. output. are with. 1MHz. mark,. is. with. and. of line. parameters. Table. from. noise. phase noise is dominated and output-of-band for. and. Fig. 4 SSCG =2 .5%.. VCO. noises. line. are. line. the. the ƒ°ƒ¢. TPDL-SSCG. with with. in. loop. phase. dashed. simulation. listed. TPDL-SSCG the. and. FN-SSCG. Others. phase. dual-path. VCO. TPDL-SSCG. from The. the. frequency. line. the. parameters. contributed plotted.. phase. for. the. offset. solid. noise. and. of The. at The. respectively.. the. also. amplifier. simplicity.. f-2.. phase. bandwidth, using. gain for. -100dBc/Hz. shape. the. loop. unity. neglected. used. for. loop. fil-. the. linear. optimized lower. the. si-. the. jitter. TPDL-SSCG. for. the. FN-SSCG. out-of-band. is the ƒ°ƒ¢. modulator.. 3.. Circuit. Description. The. circuits. used. order tional. to fulfill part. may. MASH-1-1 ƒ°ƒ¢ overcome. Fig. 5. Phase. noise. simulation. for different. PLL loop bandwidths.. in. the. the. exceed modulator. the. Fig.. overflow. 6. work. various. Extended. are. output than. described. briefly. next.. frequency. where. the. 1, input is extended. problem. range. MASH. [7].. range as. of. the. shown. Assume. 1-1 ƒ°ƒ¢. modulator.. in that. In frac-. modified Fig. the. 6 to bit.

(5) KAO and HSIEH: A HIGH PERFORMANCE. SPREAD SPECTRUM. CLOCK GENERATOR. USING TWO-POINT. MODULATION. SCHEME 915. width of the modulator is BT. The input range of the conventional MASH type modulation is between 1/2BTto 1-1/2BT. When an input exceeds 1, the modulator will be saturated to. collapse sue,. the. the. while. following. the. can way. the. output. put. range. still. and. will. of the. of. ratio. Figs.. than. switching.. is. less The to. used. to. the. enough. The. (a) VCO circuits and (b) delay cell used in VCO.. die. Unity. gain buffer circuit. used in dual-path. loop filter.. CP3. in-. 3-1/2BT. larger. have. feature. are. shown. is not. for. of. sharing for. band. of. cross-coupled. CP3. and. cells,. delay. cell. connection. swing. due [13],. delay. the. for when. VCO. differential. schematic. noise. buffer. needed. wide. in. current. employed. charge. The. full. are. cascoded. A unity-gain the. stages. gain. buffer. the. its. phase. designed linear. loop. is. Mn1. sharp. rail-to-rail. and. waveform. for phase. CP1.. The. noise. noise much. input. filter is shown to be twice that. capacity and. VCO. is. with. dual-path is designed. is. at offset larger. modulation.. TPDL-SSCG. is. single-poly. photograph. 0.89mm2.. Fig. 9. to. The. with stage. simple. the. load. of. for. pole the. out-. 9. The to pro-. one-stage. designed. frequency. than. The. and. in Fig. of Ip1. 1MHz.. of. 1/R1C2. buffer. a small parasitic is needed.. 10dB. of. com-. capacitor;. Measurement. 0.35ƒÊm. Fig. 8. circuit. The. prises a resistor R1 in series therefore, no extra driving. 4.. 1 in. input. handle. still. The. reduce. obtain. driving. GBW. and. buffer. The to. adopted. maintain. the. to. can and. carry to. stages.. extended. supply.. three. 8(a).. unity. than. 2-bit. equal of. is-. carry. jitter.. in the current. is. be. frequency.. 8(b).. the. The. design. power. employed. put used driving vide. Fig.. in Fig. is. The. part. one. bias. the. of. in. to reduce. can. this. a 2-bit. or. following. CP1(2). unity-gain. consists. Mn2. (a) CP1 and CP2 circuits and (b) CP3 circuit.. integer. modulator. of. operating. shown. shown. Fig. 7. is. The. which. than. respectively.. wide-swing. CP2. low. carry.. conventional. (b),. against. and. has. 1-bit. the. one. conquer. stability.. with. immunity. the. saturate. to. stage-1. larger the. proposed. the. and. sources. to. not. charge-pump. 7(a). CP1. quickly. the. unconditional The. inputs. proposed. Moreover, spread. only. the. it bring. order. The. keeps. manifest. that. In. is revised.. stage-2. outputs such. stages.. architecture. designed. is shown The. output. Fig. 10. and. fabricated. quadruple-metal in Fig. spectrum. by. CMOS 10 with without. The TPDL-SSCG. area. TSMC. process. equal. spreading. die photograph.. The. to 0.90•~ is shown.

(6) IEICE TRANS. ELECTRON.,. VOL.E91-C,. NO.6 JUNE 2008. 916. Fig. 11 Measured spectra of 400MHz output frequency (a) at non-spread spectrum mode, (b) of the conventional SSCG with 2.5% spread ratio, and (c) of the TPDL-SSCG with 2.5% spread ratio.. Fig. 12 Measured period jitter of 400MHz output frequency (a) at non-spread spectrum mode, and (b) of the TPDL-SSCG with 2.5% spread. Table in. Fig.. of. the. 11(a) peak. tional. is. are. order. extended. both. Figs.. SSCG. range. 11(b). is. .43dBm. for. reductions that. are. in. small. Fig.. 1.70dB. rms as. as. is. for. when. theoretical. Table SSCG.. 2. the. total. is. the. the. The. of. The. peak. and. to Two. 11(b). the. due. to. loop. The. mea-. 2.5% rms. which. spread. consumption. summaries is. ratio. period. jitter. is. is very. close. to. of 33mW.. the. TPDL-. Conclusion. In this study, the spread. period jit-. 10.42ps(=2.5%•~2500ps/6).. performance. 5.. spectrum. rms. with. a 10.10ps. inhas. same. non-spread. measured. is in active. VCO. TPDL-SSCG with. at. of. respect. FN-SSCG.. 14.13ps. Only. Fig.. reduction. TPDL-SSCG. SSCG. power. in. for FN-. respectively.. proposed. traditional. 12(a).. 12(b).. estimation. gives The. Fig.. path. with. (c),. edges. EMI. adopted. -14.73dBm. 19.73dB and. to. second-. traditional. the to. 2.5%. close The. respectively.. and. the. jitter in. off. (c),. The in. the. reduced. 11(b). at the. to. in Fig.. increased the. 18.03dB. exist. period. 24.23ps. switching. Figs.. (c). is. words,. summaries.. respectively.. bandwidth and. Performance. a tradi-. with. (c),. 2. amplitude. using. modulator. other. bandwidth.. shown. shown. In. 11(b). compared. sured. 11(b). by. improvement. mode. a PLL. and. still. bandwidth. and. Figs.. for. and. Figs.. are. about. loop. 11(b). amplitudes. 11(a). peaks. sufficient. Figs.. both. just. The. spectra. filter. (c).. The. TPDL-SSCG. MASH ƒ°ƒ¢. and. obtained. modulation. -16. for. output. proposed in. loop chosen. at 400MHz.. The the. shown. second-order are. speed. 3.30dBm. and. ratio. 70kHz. ter. clock. FN-SSCG. spread A. with. spectrum. clock generator. with two-. point modulation scheme is presented. The loop bandwidth of the PLL can be small but the modulation bandwidth is effectively expanded. This feature gives us the advantages of the linear modulation profile and using the lower order sigma-delta modulator without quantization noise penalty. Another advantage is the total integration without using an external loop filter. A novel configuration for replacing the high resolution DAC in triangular waveform generation is realized, which not only saves the area but also suppresses.

(7) KAO and HSIEH: A HIGH PERFORMANCE. SPREAD SPECTRUM. CLOCK GENERATOR. USING TWO-POINT. MODULATION. SCHEME 917. the digital spur at the highly. sensitive. VCO input.. provement of EMI reduction is better than spect to the conventional one.. The im-. 1.7dB. with re-. [15]. S. Pavan,. Y. Tsividis,. MOS. apacitors. IEEE. Int.. Symp.. for. and. K.. analog Circuits. Nagaraj, •gModeling digital. of. design. in. VLSI. and. Systems,. vol.6,. Kao. was born. accumulation. processes,•h. Proc. pp. 202-205,. .. June. 1999.. Acknowledgment The authors would like to thank National Chip Implementation Center and National Science Council, Taiwan, R.O.C., for chip implementation and financial support. Yao-Huang. References [1]. J.Y. Michel duction. and. M.. M.. VLSI. T.. with. a 0.3-mW. K. spread. June. [5]. T.. generator. Dig.. Tech.. Papers,. H.R.. Lee,. [7]. O.. [8]. generator. tems,. pp. 2643-2646, Hsieh. and. no.4,. clock. generator. Hua,. Koo,. and. W.. T.. tracking pp. 107-. M.. Suzuki,. S.. PLL. controlled. C.C.. Int.. Symp.. Yi-Bin stitute. Tech.. and. Sys-. us-. fully. J.. clock. Solid-State. integrated. D.R.. gen-. Circuits,. spread. Compatibility, Li,. spectrum. modulation,•h May. IEEE. and. Proc.. pp. 227-231,. 1994.. IEEE. Int.. Horng, •gHigh-performance. two-point. Theory. clock. emissions,•h. T.S.. using. Int.. 2007.. Bush, •gSpread-spectrum. of radiated. transmitters. Huh,. Y.. J. Lee. and. Tech.,. delta-sigma. vol.52,. T.L.. fractional-N. Mb/s. GFSK. no.12,. pp. 2048-2060,. and. no.11,. modupp. 2529-. Aug.. filter. J. Solid-State. phase-locked. J. Solid-State. Jeong, with for. PCS-. Circuits,. Circuits,. loop. with vol.35,. 2000. III,. synthesizer. using. Dec.. D.K.. synthesizer loop. IEEE. fast-lock IEEE. Tewksbury. modulation,•h. Lee,. 2002.. low-noise control,•h. K.. frequency. dual-path. systems,•h May. Kim, •gA. J. Park,. CMOS. wireless. pp. 1137-1145,. Lee,. pump. pp. 536-542, B.. J.. integrated. charge. bandwidth. Perrott,. Cho,. fully. of Technology,. IEEE 1997.. and. J.. C.G.. digital Solid-State. Sodini, •gA compensation Circuits,. 27-mW for. the M.S.. 2.5-. vol.32,. in National. Taipei, degree. Engineering,. Tung. University,. where. he currently. Hsin-Chu, is pursuing. Taiwan,. Taipei. in 1993.. at the Institute National Taiwan,. He Inof. Chiaoin 1998,. the Ph. D. degree.. His research interests include mixed-mode signal processing IC design, and clock and data recovery. 2006.. spread-spectrum IEEE. pp. 2156-2159,. Microw.. generator. modulator,•h IEICE June. was born in 1973, Taiwan.. the B.S. degree. Communication. spectrum. Circuits. clock. delta-sigma. C.J.. Hsieh. Dig.. 2003.. and. appointed. In 1988 he was a visiting. year he was at Bell Communication Research (Bellcore). Currently he is a professor in the Department of Communication Engineering, Chung-Hua University, Hsin-Chu, Taiwan. His current research interests involve nonlinear dynamics and chaos, high speed optical communications, and microwave and RF circuit designs. He is also a technical consultant for RF circuits in many industrial companies and government institutes. Dr. Kao is a member of IEEE.. received. spread. on. range ƒ°ƒ¢. Liu, •gA. Systems,. he was also. of. Chiao-. scholar researching nonlinear circuit at the University of California, Berkeley. In the following. transceiver. Conf.. Su, •gA. pp. 851-857,. April. at National. Conf.. 5000ppm. SATA. Circuits. and. Kao, •gA. where. in. From 1986,. by ƒ¢ƒ°. Circuits. low-jitter. spread-spectrum. S.I.. University. of the Department. Engineering. University,. He received. two-point. Trans.. Noto,. Solid-State. Solid-State. no.6,. Huang,. Kim, •gA. no.5,. CMOS. Gb/s,. Circuits,. Jeong, •gA. IEEE. reduction. cellular-CDMA. M.H.. T. Ishibashi,. 2004. H.. vol.37,. no.8,. ATA,•h. 2002.. Chiao-Tung. 1986, respectively.. he was a member. Communication Tung. J. Kasai, •gSpread-spectrum. an extended. Fessler,. charge-averaging. adaptive. serial. frequency. VLSI. multi-channel. modulation,•h. and. C.H.. Nov.. Y.. S.. 2005.. and. Y.H.. the. D.K.. Lune,. Kao, •gA. J.T. for. IEEE. 2535,. [14]. H.W.. with. Circuits. Peng,. lation,•h. [13]. 2005.. Electromagnetic. K.C.. and. Int.. Feb.. PLL. frequency-hopping. [12]. Tai-. 2005.. for. IEEE. using. Hardin,. Symp.. and. Y.H.. and. on. from National 1977, and. to a full professorship.. T. Noma, •g3. with. Int.. Feb.. generator. pp. 673-676,. Hsieh. K.B.. and. fractional. IEEE. SATA-II,•h. I.H.. generation. [11]. Ahn,. triangular. Y.B.. using. vol.E89-C,. Chang,. Symp.. ATA. May. Electron.,. vol.38,. [10]. for. with. and. G.. Hsu,. fractional-N. H.H.. for June. T. Ishibashi,. Symp.. Oshima,. shifter,•h. CMOS,•h. J.C.. neering 1975,. S. Shimoyama,. detector. PHY. ATA,•h. T.. clock. clock. erator. [9]. Kim,. Chen,. Trans.. re-. Conf.,. spread-spectrum. pp. 60-63,. Sugawara,. pp. 160-161,. W.T.. ing. level. T. Takahashi, serial. pp. 162-163,. Y.B.. EMI. M. Zwerg,. Fukaishi,. 5150-ppm. SerDes. serial. level. spectrum. Papers,. for. ASIC/SOC. Aoyama,. T. Yanagita,. Kawamoto,. for. with. in 0.18ƒÊm. [6]. for. modulator. spread. M.. Papers,. M.. spectrum. T. Hayasaka,. clock. PLL. Int.. 2003.. Kokubo,. Suzuki,. Tech.. Yamaguchi,. interpolator. M.. M.. 1.5-Gb/s. Dig.. K. Ogasawara,. 5000ppm. [4]. Ogasawara,. Noma, •g1.5-Gb/s. Circuits. Aoyama,. 110,. IEEE. T. Yanagita,. and. S. Shimoyama,. phase. K.. Y. Kameyama,. PHY. Symp.. modulated. Proc.. to 2006. T. Ishibashi,. T. Ishihashi, SerDes. frequency. application,•h. 1999.. Sugawara,. Glowinski,. [3]. C. Neron, •gA. in embedded. pp. 362-365, [2]. in Tainan,. wan, Republic of China in 1953. He received his B.S., M.S., and Ph. D. degrees in electronic engi-. circuit. design..

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