Temperature dependent integrity of Sr0.8Bi2Ta2O9 films on ultra-thin Al2O3 buffered Si

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Materials Chemistry and Physics 80 (2003) 325–328

Temperature dependent integrity of Sr

0 .8

Bi

2

Ta

2

O

9

films

on ultra-thin Al

2

O

3

buffered Si

Bang Chiang Lan

a

, San Yuan Chen

a,∗

, Hsin-Yi Lee

b

a_{Department of Materials Science and Engineering, National Chiao Tung University, Hsinchu, Taiwan, ROC} b_{Research Division Synchrotron Radiation Research Center, Hsinchu, Taiwan, ROC}

Received 18 June 2002; received in revised form 18 October 2002; accepted 24 October 2002

Abstract

The annealing temperature dependent integrity of Sr0.8Bi2Ta2O9 (SBT) on ultra-thin 4 nm SiO2 and Al2O3 buffered Si was

inves-tigated in this work. Although the capacitance–voltage characteristics show hysteresis loops in both cases, the memory window of Sr0.8Bi2Ta2O9/Al2O3 capacitor is larger than that of Sr0.8Bi2Ta2O9/SiO2 capacitor. As increasing annealing temperature from 800 to

900◦C, the grain size and memory window of polycrystalline SBT increase both cases. At 800◦C, the leakage current density of Sr0.8Bi2Ta2O9/Al2O3capacitor is 3.2×10−8A/cm2at−3 V, which is low enough for deep sub-␮m application. With increasing temperature

Keywords: Sr0.8Bi2Ta2O9(SBT); Al2O3buffer; Memory window; Leakage current

1. Introduction

The thin films of Bi layered structured perovskite com-pound, SrBi2Ta2O9 (SBT), is well known to show

excel-lent ferroelectric properties because of its specific crystal structure. Due to the particular properties, SBT thin films have been widely studied for the application in metal– ferroelectric–semiconductors field effect transistors (MFS-FETs)[1,2]. Although the metal/ferroelectric/semiconductors memory has been studied for about 40 years[3], the progress of this memory is very slow because of the problems of interface reaction between ferroelectric material and Si

[4,5]. In order to overcome these problems, an intermediate layer of SiO2, CeO2, or Y2O3 [6–8] is inserted between

ferroelectric material and Si layer that results in the metal/ ferroelectric/insulator/semiconductors (MFIS) structure

[9,10]. However, the inserted gate dielectric must be thin enough to avoid significant voltage drop in this layer. Fur-thermore, for process integration with next generation high performance and low voltage logic technology, ultra-thin gate dielectric layer and large capacitance are required. Recently, the ultra-thin Al2O3of 4 nm thickness was used as

both gate dielectric and diffusion barrier for one-transistor (1T) ferroelectric–metal-oxide–semiconductor FET

(FeMO-∗_{Corresponding author. Tel.:}_{+886-3-5731818; fax: +886-3-5725490.} E-mail address: [email protected] (S.Y. Chen).

SFET) memory because of the excellent gate dielectric and diffusion barrier properties [11,12]. Good device memory characteristics of 1T Pb(Zr, Ti)O3 FeMOSFET have also

been achieved [13,14]. Because SBT has better fatigue resistence than PZT [15], in this paper, we have further studied the temperature dependent memory characteristics of SrBi2Ta2O9 on ultra-thin 4 nm Al2O3 buffered Si in

comparison with those on the same 4 nm SiO2buffered Si.

2. Experimental

Four-inch Si p-type wafers were used in this study. A HF-vapor passivation was used to suppress the native ox-ide formation before other treatment. After the deposition, amorphous Al layer was thermally evaporated on wafers. The Al layer was oxidized at a temperature of 400◦C for 2 h to form 4 nm Al2O3and finally annealed at 800◦C for

30 min in nitrogen ambient. More detailed fabrication pro-cess can be found in these researches[11,12]. In comparison with Al2O3, conventional thermal SiO2on Si was grown in

oxygen ambient and annealed at 900◦C for 5 min. The size of memory window in MFIS structure is quite important as the value of Pr in MIM structure. In the previous researches, the size of memory window is linear presented with coer-cive field[16]. Based on the researches Sr0.8Bi2Ta2O9 has

been chosen as the main component[17,18]. The deposition

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process using strontium 2-ethylhexanotate [Sr(C8H15O2)2],

bismuth 2-ethylhexanoate [Bi(C8H15O2)2], tantalum

ethox-ide [Ta(OC2H5)5] as the metal-organic precursors. The

SBT formula solution were prepared and with xylene as the solvent to adjust the concentration of the solution. The solutions with a mole ratio (Sr:Bi:Ta) of 0.8:2:2.0 were spin coated on both gate dielectrics at 4000 rpm for 30 s and then followed by subsequent drying. This procedure was repeated for several times to obtain the desired film thickness of 3500 Å. Between each coating, the wet films were pyrolyzed for several minutes. The as-deposited films were annealed at different temperatures from 600 to 900◦C for 30 min. The chemical composition of the films was determined using inductively coupled plasma (ICP). The molar number (Sr/Bi/Ta= 0.78/2.05/2.0) of Sr, Bi, and Ta in those films is very close to the composition (Sr/Bi/Ta= 0.8/2/2.0) in the precursor solution[19]. After that, the Al backside and Pt upper electrodes were formed by thermal evaporation. The device size of the fabricated MOS capaci-tor is 3.14 × 10−4cm2. The structure property of SBT films was analyzed by MAC Science M18XHF X-ray diffrac-tometer with Cu K␣ radiation. The thickness and surface morphology of the films was observed using Hitachi S-4000 scanning electron microscopy (SEM). The electrical and ferroelectric properties were characterized by I–V and C–V measurements using HP-4155B and HP-4284, respectively.

3. Results and discussion

XRD studies of SBT films as a function of annealing temperature have indicated that the films annealed at 600◦C are amorphous. At 650◦C, SBT phase starts to develop and a broad diffraction peak of (1 1 5) appears around 2θ ∼ 28.5◦,indicating that the film is not fully crystallized. As the annealing temperature increased to 750◦C, the (1 1 5) peak in the XRD pattern becomes sharper.Fig. 1shows the XRD patterns of SBT films on both Al2O3and SiO2annealed at

800–900◦C. The relative intensity of (1 1 5) peak is much higher than any other orientations so that SBT films grown on both insulator are (1 1 5) oriented. The obtained SBT films on both insulators are polycrystalline and no second phases are detected even though the annealing temperature increases

Fig. 2. SEM images of SBT on 4 nm SiO2/Si annealed at (a) 800◦C and (b) 900◦C.

Fig. 1. XRD patterns of SBT on (a) 4 nm SiO2/Si and (b) 4 nm Al2O3/Si.

to 900◦C. In contrast, for the SBT films on Pt/Ti/SiO2/Si,

the pyrochlore phase was usually detected at the annealing temperature higher than 850◦C[20].

Figs. 2 and 3 illustrate the typical SEM surface images obtained from SBT on SiO2/Si and Al2O3/Si, respectively.

It is observed that these films are relatively uniform without cracks and the grain size of SBT thin films is strongly de-pendent on the annealing temperature. At 800◦C, the SBT grains on both cases are rod-like. The grain size of SBT films on SiO2insulator is much smaller than that on Al2O3

as shown in Figs. 2(a) and 3(a). As increasing annealing temperature to 900◦C, the morphology of the SBT films

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B.C. Lan et al. / Materials Chemistry and Physics 80 (2003) 325–328 327

Fig. 3. SEM images of SBT on 4 nm Al2O3/Si annealed at (a) 800◦C and (b) 900◦C.

becomes different in both insulators. As shown inFigs. 2(b) and 3(b), the grains on both insulators become coarsening especially for the SBT films on Al2O3insulator.

Fig. 4shows the typical C–V curves of both SBT/Al2O3/Si

and SBT/SiO2/Si structure. The sweep voltages in this

mea-surement change between +5 and −5 V back and forth at the frequency of 1 MHz. Clockwise hysteresis loops are ob-served, which indicates the switching of the ferroelectric polarization.

The good C–V characteristic of SBT films on Al2O3/SiO2

at 1 MHz is observed and the dielectric constant of Al2O3is

about 9 that is two times larger than that of SiO2. The good

gate dielectric property would be further considered to inte-grate SBT thin films on Al2O3gate dielectric.Fig. 5shows

the memory window of SBT capacitors on both Al2O3and

SiO2insulators at different annealing temperatures of 800,

850, and 900◦C, respectively. For the Sr0.8Bi2Ta2O9

ca-pacitor in the both insulators, it was found that the memory window size increases with annealing temperature in the range of 800–900◦C. The width of memory window of SBT/Al2O3/Si capacitor is larger than that of SBT/SiO2/Si

capacitor. This improved ferroelectric property for the SBT films on Al2O3/Si may be due to the excellent diffusion

barrier property of Al2O3 than SiO2as consistent with the

report by Chin et al. that the low interface trap density and better reliability can be obtained using Al2O3than SiO2as

Fig. 4. C–V characteristics of both Sr0.8Bi2Ta2O9/Al2O3/Si and

Sr0.8Bi2Ta2O9/SiO2/Si structures annealed at 800◦C with program/erase

voltages of±5 V.

buffer layer of Si [21,22]. The atoms in SBT may diffuse into SiO2at the higher annealing temperature and degrades

the ferroelectric property. This result is consistent with our previous work in 1T PZT/Al2O3memory[11,12]. This

fur-ther demonstrates that the memory window value is strongly dominated by the buffer layer of the SBT capacitors.

Fig. 6(a) and 6(b) show the annealing temperature de-pendent leakage current for SBT films on SiO2and Al2O3,

respectively. The leakage current was measured with a hold time 0.5 s and delay time 0.5 s. In both cases, the leakage current shows a general decreasing trend as the annealing temperature increases. This result is probably attributed to the fact that the Al2O3 insulator layer becomes

thick-ness with annealing temperature that makes the leakage current decrease. The current density of 3.4 × 10−7 and 3.2 × 10−8A/cm2 are measured at an applied voltage of

−3 V for SBT/SiO2and SBT/Al2O3at 800◦C, respectively.

As the annealing temperature increases higher than 800◦C, i.e. 900◦C, the SBT/SiO2has relatively low current leakage

(2.5 × 10−8A/cm2) compared to that (3.7 × 10−8A/cm2) of SBT/Al2O3. Since the grain morphology and size of

SBT/SiO2 and SBT/Al2O3 are quite similar at 800◦C, we

may speculate that the SBT/Al2O3capacitor has lower

cur-rent leakage because Al2O3 insulator has larger bandgap

than SiO2. Because the leakage current of dielectric is the

well known Fowler–Nordheim (F–N) tunneling at high field, the smaller leakage current is due to the additional large bandgap Al2O3 gate dielectric because F–N

tunnel-Fig. 5. Memory window of SBT/Al2O3/Si and SBT/SiO2/Si capacitors

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328 B.C. Lan et al. / Materials Chemistry and Physics 80 (2003) 325–328

Fig. 6. Annealing temperature dependent J–V characteristics of SBT on (a) 4 nm SiO2/Si and (b) 4 nm Al2O3/Si.

ing is exponentially dependent on bandgap according to following F–N equation: J = q3E2D 16π2_φ_Dm∗ D exp −4(2m∗D)0.5φ 3/2 D 3qED

where ED,m∗D, andφD are the dielectric electric field,

ef-fective mass and barrier height, respectively. Therefore, a lower leakage current can be obtained for the SBT/Al2O3

structure. On the other hand, at 900◦C, the grain size of SBT film on Al2O3is bigger than that of SBT film on SiO2

that may cause a slight increase in leakage current of the former structure compared to the latter structure. That is because the film with the larger grain size has fewer grain boundaries and presents rough surface that will result in a higher leakage current[23]. However, the leakage current is still low enough for advanced deep sub-␮m application.

4. Conclusion

We have characterized the annealing temperature depen-dent integrity of SBT on ultra-thin Al2O3and SiO2buffered

Si. Over the wide range of annealing temperature, the SBT on ultra-thin Al2O3has superior memory window than that

of SiO2with the same thickness of 4 nm. At 800◦C, the

leak-age current of SBT/Al2O3capacitor is about 3.2 × 10−8A/

cm2 at −3 V which is still low enough for advanced deep

sub-␮m application.

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