420 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 57, NO. 2, FEBRUARY 2008
A Histogram-Based Testing Method for Estimating
A/D Converter Performance
Hsin-Wen Ting, Student Member, IEEE, Bin-Da Liu, Fellow, IEEE, and Soon-Jyh Chang, Member, IEEE
Abstract—A sine-wave histogram-testing structure for
analog-to-digital converters (ADCs) is proposed. The ADC static pa-rameters, i.e., offset error, gain error, and nonlinearity errors, are directly obtained from the sine-wave histogram test. Then, the obtained static parameters are related to the estimation of the degraded signal-to-noise ratio (SNR) value. Therefore, the relationships among these parameters are analyzed, and a single sine-wave histogram test can be performed to evaluate the ADC. With the appropriate approximations in the reference sine-wave histograms and the estimations of the ADC parameters, the re-alization of an ADC output analyzer circuit could be a simple task. An ADC output analyzer circuit is therefore developed and synthesized using a 0.18-µm technique to analyze the outputs of an 8-bit ADC and estimate its performances using the proposed method.
Index Terms—Analog-to-digital converters (ADCs), degraded
signal-to-noise ratio (SNR) value, gain error, nonlinearity error, offset error, sine-wave histogram test.
I. INTRODUCTION
A
NALOG-TO-DIGITAL converters (ADCs) have a wide application in modern electronic devices and systems. Therefore, characterizing the performance of ADCs is an important concern. The ADCs are commonly tested using a specification-oriented method to determine the parameters of interest, such as offset error, gain error, nonlinearity er-ror, signal-to-noise ratio (SNR), and effective number of bits (ENOB). Thus, the tolerance and confidence levels of the testing method that is used to characterize the ADC must be appropriate [1], [2].The histogram method is one of the popular techniques for ADC testing [1]–[6]. Conventionally, the histogram test reveals the offset error, gain error, and nonlinearity error, i.e., differential nonlinearity (DNL) and integral nonlinearity (INL), by comparing the measured histograms to the reference ones. Performing one test to obtain the ADC dynamic and static parameters is a promising strategy for test procedure simpli-fication and ADC test cost reduction. Studies that relate the relationship between the test results of the histogram method and the ENOB value have been reported [7]–[10]. Therefore, one objective of this paper is to relate the commonly obtained Manuscript received January 10, 2007; revised July 13, 2007. This work was supported in part by the National Science Council of Taiwan under Grant NSC-96-2221-E-006-294 and by the Ministry of Economic Affairs, R.O.C., under Grant 94-EC-17-A-01-S1-031.
The authors are with the Department of Electrical Engineering, Na-tional Cheng Kung University, Tainan 701, Taiwan, R.O.C. (e-mail: hwt93@ spic.ee.ncku.edu.tw).
Digital Object Identifier 10.1109/TIM.2007.910106
static parameters, i.e., offset error, gain error, and nonlinearity error, to the degradation in SNR value.
To realize a complete system on a single chip, the ADCs are often integrated with other circuits. Testing these ADC circuits is a challenging task because of the limited controlla-bility and observacontrolla-bility. To resolve the problem, one promising strategy is to estimate the ADC performance on chip [5], [6]. In general, the straightforward realization of the on-chip histogram test method requires hardware resources of memory for storing both the experimental and the reference histograms and computing capabilities for evaluating the ADC param-eters. Either a linear ramp or a sine wave can be used as an input stimulus to establish the histograms. The linear his-togram technique presents a very interesting feature that con-cerns memory saving for storing the reference histograms. In addition, another advantage that is derived from the intrinsic property of a linear ramp input is the reduced circuitry of the ADC output analyzer circuit [5], [6]. However, the linear ramp input slowly changes, and the linear tests are consequently considered to be static tests [4]. The dynamic nonlinearities of the ADC worsen with increasing input slew rate. In applying a higher frequency signal to the ADC, the worse nonlinearities result in a larger harmonic distortion and degrade the ADC’s performance. At higher frequencies, a sine wave is easier to generate than a linear signal, and a sine-wave input signal is usually used to determine the dynamic characterization [4], [11]. However, the characterization of the ADC performance with a sine-wave input is more complicated than that for the linear ramp input due to the nonuniform distribution of the code counts. Then, a large amount of additional circuitry is required to extract the nonuniform distribution. An interesting test technique for resolving this difficulty has been reported [6]. However, the assumption of a symmetric reference his-togram to save on hardware costs generates a testing error. Therefore, another objective of this paper is to investigate the appropriate approximations, which are easy to implement on chip, of the original complex expressions in the ADC sine-wave histogram test. Then, an ADC output analyzer circuit is real-ized according to these approximations in the ADC sine-wave histogram test.
This paper is organized as follows: The basic histogram-testing background is introduced in Section II. The proposed single sine-wave histogram test that determines the ADC pa-rameters is described in Section III, along with an analy-sis and discussion. The simulation and experimental results that validate the proposed testing architecture are given in Section IV. Finally, conclusions are drawn in Section V. 0018-9456/$25.00 © 2008 IEEE
TING et al.: HISTOGRAM-BASED TESTING METHOD FOR ESTIMATING A/D CONVERTER PERFORMANCE 421
II. BACKGROUND
The histogram or the output code density is the number of times every individual code has occurred [3]. The sine-wave histogram-testing technique applies an analog sine-wave signal that is slightly larger than the full scale of the ADC to ensure that all the valid codes are exercised. Then, the code count numbers of the converter output are recorded to establish the histograms.
The size of each ADC quantization level is the least signifi-cant bit (LSB). The number of hits at the upper and lower codes can be used to find the offset (Vo) and amplitude (A) of the
input sine wave in LSBs, i.e.,
Vo= cos [πH(0)/Nt]−cos πH(2N−1)/Nt cos [πH(0)/Nt]+cos [πH(2N−1)/Nt] (2N−1−1) (1) A = 2 N−1− 1 − V o cos [πH(2N− 1)/N t] . (2)
This fitted sine wave is the input as seen through the “eyes” of the ADC device under test (DUT) [4], [11].
When the offset and amplitude of the sine-wave input are de-termined, the reference sine-wave distribution of code counts, which is denoted as Href(i), can be obtained. The expression of
the ith code count for an N -bit ADC is therefore
Href(i) = Nt π sin−1 i + 1− 2N−1− Vo A − sin−1 i− 2N−1− Vo A (3) where Ntis total number of samples.
The offset error should be zero for an ideal ADC. Therefore, the offset error Offset_Error of an N -bit ADC can be expressed in LSBs as
Offset_Error = (2N/V )Vo (4)
where V is the reduced full-scale range of the ADC.
The nominal value of the slope of the ADC transfer curve G is unity, and the gain error Gain_Error of an N -bit ADC can be expressed in LSBs as
Gain_Error = 2N(G− 1). (5) Let H(i) be the number of samples presented in code i. One can therefore subtract one LSB from the ith codeword width to obtain the DNL errors in LSBs, i.e.,
DNL(i) = H(i)
Hideal(i)− 1,
i = 1, 2, . . . , 2N − 2. (6) Then, the DNL values can be integrated to obtain the cumu-lative sum and to calculate the INL errors. The corresponding INL error expression in LSB units can be described as
INL(i) =
i
k=1
DNL(k), i = 1, 2, . . . , 2N− 2. (7)
Fig. 1. (a) Transfer curve for an ideal 3-bit ADC. (b) Quantization error for an ideal 3-bit ADC.
III. ADC SINE-WAVEHISTOGRAM-TESTINGSTRUCTURE This section is divided into three parts. The relationships between the estimated degradation of the SNR value and the test results, which are obtained by using the sine-wave histogram method, are analyzed. Therefore, a single sine-wave histogram test can be used to obtain the ADC static performance and an estimation of the dynamic one. Then, the considerations of employing a sine-wave histogram test method are summarized. In addition, an ADC output analyzer circuit, together with the appropriate approximations needed to determine the ADC parameters, is then developed without using extra memory to store the reference histograms.
A. Relationships Among ADC Performances
The error waveform is generated in the process of quantiza-tion. The nominal size of each quantization level is the LSB. An N -bit ADC with a full-scale analog input range of F S has a corresponding LSB step size of
VLSB =
F S
2N− 1. (8)
Ideally, the quantization error is uniformly distributed, and the root mean square (rms) value of the ideal quantization error is given by
ve,rms=
V√LSB
12. (9)
The transfer curve and the quantization error of a 3-bit ideal ADC are shown in Fig. 1, where the periodicity of the sawtooth is designated as T .
For a full-scale sine-wave input having a peak value of 2N−1 LSB, the best achievable SNR value SNRidealat the output of
the ADC is given in units of decibel as
426 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 57, NO. 2, FEBRUARY 2008
TABLE II
ESTIMATIONS OF THEADC PARAMETERS AND THESYNTHESIZED RESULTS OF THEPROPOSEDADC OUTPUTANALYZER
uncertainty B of 0.1 and a given confidence of 0.95 in INL and DNL, the numbers of records R calculated from (21) were 8 and 15 for INL and DNL, respectively. The total number of samples Nt= RM was therefore 30 720. Concerning the
hardware complexity, Nt was adjusted to a power of 2, as
mentioned in Section III-C. Consequently, the number of Nt
was selected to be 32 768.
Then, the ADC output codes were applied to the proposed ADC output analyzer circuit. The estimated DNL, INL, and SNRd were ±0.40 LSB, ±0.40 LSB, and −1.24 dB,
respec-tively. The total synthesized results of the proposed output analyzer circuit are listed in Table II.
V. CONCLUSION
This paper has analyzed the relationships between the es-timated degradation of the SNR value and the test results obtained by using the sine-wave histogram method. Therefore, a single sine-wave histogram test can be used to characterize an ADC. Furthermore, the considerations of the sine-wave histogram test are summarized. The random effect in estimation uncertainty can be effectively reduced by increasing the record length with consideration of the finite resolution of the syn-thesizers. The systematic contributions in the estimation uncer-tainty can be reduced by increasing the overdrive and improving the instrument hardware. In addition, an ADC output analyzer circuit for determining the ADC parameters is also introduced. This architecture involves calculation of the ADC parameters using appropriate approximations to reduce hardware complex-ity. An ADC output analyzer circuit is therefore developed and synthesized by using a 0.18-µm technique to validate the performance of the proposed ADC output analyzer circuit.
ACKNOWLEDGMENT
The authors would like to thank Y. Z. Lin and Y. C. Lien for valuable technical discussions.
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Hsin-Wen Ting (S’06) received the B.S. and M.S.
degrees in electrical engineering in 2002 and 2004, respectively, from the National Cheng Kung Univer-sity, Tainan, Taiwan, R.O.C., where he is currently working toward the Ph.D. degree.
His research interests include integrated circuit design and testability design for analog and mixed-signal circuits.
TING et al.: HISTOGRAM-BASED TESTING METHOD FOR ESTIMATING A/D CONVERTER PERFORMANCE 427
Bin-Da Liu (S’79–M’82–SM’95–F’06) received
the B.S., M.S., and Ph.D. degrees from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1973, 1975, and 1983, respectively, all in electrical engineering.
From 1975 to 1977, he was an Electrical Of-ficer with the Combined Service Forces. Since 1977, he has been a faculty member with National Cheng Kung University (NCKU), where he is cur-rently a Distinguished Professor with the Department of Electrical Engineering and the Director of the System-on-Chip Research Center. From 1983 to 1984, he was a Visiting Assis-tant Professor with the Department of Computer Science, University of Illinois, Urbana. From 1988 to 1992, he was the Director of the Electrical Laboratories, NCKU. He was the Associate Chair (from 1996 to 1999) and Chair (from 1999 to 2002) of the Department of Electrical Engineering, NCKU. Since 1995 and 1997, he has been a Consultant with the Chip Implementation Center, Tainan; the National Applied Research Laboratories, Taipei, Taiwan; and the Very Large Scale Integration (VLSI) Circuits and Systems Educational Program, Ministry of Education, Taiwan, respectively. He is the author/coauthor of more than 240 technical papers. He also contributed chapters in Neural Networks and
Systolic Array Design (Singapore: World Scientific, 2002), Accuracy Improve-ments in Linguistic Fuzzy Modeling (Heidelberg, Germany: Springer-Verlag,
2003), and VLSI Handbook, Second Edition (Boca Raton, FL: CRC, 2006). His current research interests include low-power circuits, neural network circuits, sensory and biomedical circuits, and VLSI implementation of fuzzy/neural circuits and audio/video signal processors.
Dr. Liu is a member of the Board of Directors of the Taiwan Integrated Cir-cuit Design Society, He is also a member of Phi Tau Phi, the Taiwan System-on-Chip Consortium, the International Union of Radio Science, the Chinese Fuzzy Systems Association, the Chinese Institute of Electrical Engineering (CIEE), and the Institute of Electronics, Information, and Communication Engineers. He was the Chair of the IEEE Circuits and Systems Society (Taipei Chapter) from 2003 to 2004, the General Chair of the 2004 IEEE Asia Pacific Conference on Circuits and Systems, and the Vice President of Region 10 of the IEEE Circuits and Systems Society from 2005 to 2006. He was a Circuit and Systems Associate Editor for the IEEE Circuits and Devices Magazine from 2003 to 2005 and an Associate Editor for the IEEE TRANSACTIONS ONCIRCUITS ANDSYSTEMSI from 2004 to 2005. He is currently an Associate Editor for the IEEE TRANSACTIONS ONBIOMEDICALCIRCUITS ANDSYSTEMS, the IEEE TRANSACTIONS ON FUZZY SYSTEMS, and the IEEE TRANSACTIONS ON VERYLARGESCALEINTEGRATIONSYSTEMS. He received the Low-Power Design Contest Award from the Association for Computing Machinery/IEEE in 2003, the Outstanding Electrical Engineering Professor Award from CIEE in 2004, the Best Paper Award from the Fourth Regional Interuniversity Postgraduate Electrical and Electronics Engineering Conference, and the 2006 IEEE Asia Pacific Conference on Circuits and Systems in 2006.
Soon-Jyh Chang (M’03) received the B.S. degree in
electrical engineering from National Central Univer-sity, Taoyuan, Taiwan, R.O.C., in 1991 and the M.S. and Ph.D. degrees in electronic engineering from National Chiao Tung University, Hsinchu, Taiwan, in 1996 and 2002, respectively.
He is currently an Assistant Professor of electrical engineering with National Cheng Kung University, Tainan, Taiwan. His research interests include the design, testing, and design automation for analog and mixed-signal circuits.
