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A Thesis

Submitted to College of Electrical and Computer Engineering National Chiao Tung University

in partial Fulfillment of the Requirements for the Degree of

Master in

Industrial Technology R & D Master Program on IC Design

September 2007

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Wire Length Driven Flip-Chip Pin-Out Designation by Range

Constrained Pin-Block Floorplanning in Package-Board Codesign

Student: Chia-Lun Weng Advisor: Prof. Hung-Ming Chen

Industrial Technology R & D Master Program of Electrical and Computer Engineering College

National Chiao Tung University

ABSTRACT

With the advanced fabrication technique developing rapidly, more and more circuits could be integrated in a single chip. This trend will cause the complication in package designs and signal interconnection. However, the typical peripheral wire-bond design may not be proper for use in some particular designs, chip becomes a better choice. In flip-chip design, engineers generally arrange the ball chart in the manual manner on experience in package-board codesign. This process is iterative, time-consuming and it will lengthen the time-to-market (TTM) of products. [1] proposed a method of generating the BGA ball chart automatically by pin-block design and floorplanning, thus helped engineers respin the ball chart slightly and saved the arranging time dramatically. In this thesis, we exhibit the procedure of accomplishing the method of [1] and improve the flooplanner in [1]. The proposed pin-block floorplanner designates pin-out for flip-chip BGA package by using the range constraints, and it is based on simulated annealing algorithm. We also develop a representation for this special floorplanning requirement. It not only has flexibility on specifying critical parameters of the pin configuration, but also guarantees the minimum package size. Experimental results show that improved pin-block floorplanner can perform a better pin assignment than that in [1].

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Contents

1 Introduction 1

1.1 Our Contributions . . . 6

1.2 Organization of this Thesis . . . 7

2 Pin-Out Designation and Package Size Optimization by Pin-Block Floorplanning 8 2.1 Overview of Fast Flip-Chip Pin-Out Designation Respin by Pin-Block De-sign and Floorplanning . . . 8

2.1.1 Package-Board Codesign by Considering Signal Integrity and Power Delivery . . . 8

2.1.2 Pin-Out Designation Automation by Pin-Block Construction and Floorplanning . . . 12

2.2 Designation Automation Flow . . . 15

2.3 Pin-Block Floorplanning . . . 16

3 Improved Pin-Block Floorplanner 26 3.1 Problem Definition . . . 26

3.2 Range Constrained Pin-Block Sequence Pair (RCPBSP) . . . 29

3.3 Floorplanning with Range Constraint . . . 32

3.4 RCPBSP Packing by Simulated Annealing . . . 34

3.4.1 Solution Perturbation and Cost Function . . . 34

4 Experimental Results 41

5 Conclusion and Future Work 50

List of Tables

4.1 The summary of these four industrial cases . . . 42 4.2 Experimental results of the method in [1] and our improved pin-block

floor-planner by considering wire length as cost function . . . 43 4.3 Shows experimental results of the method in [1] and SA-random

floorplan-ner. Wire length and penalty term are considered simultaneously in cost function . . . 45 4.4 Shows experimental results of our improved pin-block floorplanner. Wire

length and penalty term are considered simultaneously in cost function . . 46 4.5 Shows the improvement of SA-random floorplanner and our improved

pin-block floorplanner by considering wire length and penalty term simultane-ously . . . 47

List of Figures

1.1 The typical flow and proposed approach in interface design for IC-package-board codesign. The focus of [1] is to automate pin-out designation and to minimize package size during design stage [1]. . . 3 1.2 While empty spaces appear on floorplan, the worse positions will cause

another cost as well. . . 5

2.1 A general layout of PCB board. The location of pins on IC package should be restricted in specific regions to meet minimum net-length [1]. . . 9 2.2 The visible package substrate of chipsets. . . 10 2.3 The cross-section of a flip-chip package which is mounted on PCB board [1]. 11 2.4 A complete pin block includes signal-pin block and its related power-pin

block. It is located on the region close to corresponding component on PCB [1]. . . 12 2.5 An example of pin configuration chart. In this pin configuration we can

define specific information as inputs of our proposed automated approach [1]. 13 2.6 A minimum package size can be obtained after we designate and floorplan

all pin blocks [1]. . . 13 2.7 The design flow of automation process. . . 15 2.8 (a) Result in Case I. (b) Result in Case II. . . 18 2.9 Rough floorplan in Case I. (uppercase P denotes the minimum package size,

uppercase C denotes the minimum core size, uppercase N denotes nothing and pin-block groups are denoted in shaded blocks.) . . . 19

2.10 Rough floorplan in Case II. (uppercase P denotes the minimum package size, uppercase C denotes the minimum core size, uppercase N denotes nothing and pin-block groups are denoted in shaded blocks.) . . . 20 2.11 Diagrams for interpretation of carrying out the algorithm from the rough

floorplan to the final floorplan in Case I. . . 21 2.12 Diagrams for interpretation of carrying out the algorithm from the rough

floorplan to the final floorplan in Case II. . . 22 2.13 Final floorplan in Case I. (uppercase P denotes the minimum package size,

uppercase C denotes the minimum core size, uppercase N denotes nothing and pin-block groups are denoted in shaded blocks.) . . . 24 2.14 Final floorplan in Case II. (uppercase P denotes the minimum package size,

uppercase C denotes the minimum core size, uppercase N denotes nothing and pin-block groups are denoted in shaded blocks.) . . . 25

3.1 Final packing is consisted of core block and pin blocks without range con-straint around the core block. . . 27 3.2 Pin blocks with the range constraint which must be placed within the given

rectangular region. . . 28 3.3 For the other sides, pin blocks with the range constraint must be placed

within rangeSide2, rangeSide3 and rangeSide4. . . . 30 3.4 Some examples of the representation in our problem. . . 31 3.5 An example illustrates groups with range constraint (rangeSide1). . . . 33 3.6 An estimation of wire length between signal pins belonged to rangeSide1

and the edge of side1. . . 35 3.7 An estimation of the penalty term which is the distance between pins and

3.8 Reveals the desired positions in other three rangeSides and the purpose of this specification is hopefully floorplanning the pins to the center of each side approximately. . . 38 3.9 Weight behavior : let the whole floorplan have rotate ability. (a) Center.

(b) Clockwise. (c) Anticlockwise. . . 39 4.1 Shows the improvement of wire length in four industrial cases ([1] vs.

SA-random floorplanner). . . 43 4.2 Shows the improvement of wire length in four industrial cases ([1] vs. our

improved pin-block floorplanner). . . 44 4.3 Illustrates the improvement of SA-random floorplanner by considering wire

length and penalty term simultaneously in four industrial cases with ρ=5 ([1] vs. SA-random floorplanner). . . 44 4.4 Illustrates the improvement of our improved pin-block floorplanner by

con-sidering wire length and penalty term simultaneously in four industrial cases with ρ=5 ([1] vs. our improved pin-block floorplanner). . . . 48 4.5 Our result packing of CaseII. The cost function considers wire length and

Chapter 1

Introduction

Moore’s Law has been announced in 1965, it has gone by almost a half of century. Moore’s Law says that the amounts of transistors on the single chip would be double per two years. In fact, the fabrication technique has improved over double in current age of deep sub-micron (DSM), that is, the amounts of transistors on the single chip would be double per eighteen months. As silicon technology scales, more and more circuits could be inte-grated in a single chip. The amounts of input/output (I/O) signals increase dramatically every unit area. Then, the I/O densities become higher and the space of finite routing resource becomes smaller. This trend will cause the complication in package designs and interaction between package and board. There were several works [17], [18], [20] which were related to package and board physical designs. [17] presented a simulated anneal-ing technique to find a pin assignment solution which considered the routability issue on PGA package and board, but no other DSM effects were considered. [18] presented some efficient patterns to assign the solar balls on board in order to meet the high I/O count for certain products, but still existed a limit to the number of solar balls that were used for power delivery, and routability between package and board. [20] proposed an efficient algorithm which assigned and routed the solder balls of BGA package. But, its fanout routing was only in a single layer and only the routability issue on board was considered. Comparing with the typical peripheral wire-bond design, flip-chip design can

accom-modate more input/output (I/O) signals, and can obtain the smaller area of package size. The ball grid array (BGA) solder balls are arranged between package and board. BGA form fully utilizes the area beneath the substrate to assign signal pins and makes up for the routability that the typical peripheral wire-bond design is restricted. Besides, the power and ground pins are located at the center of package and the die is located upon these power and ground pins. The heat generated from the die can be diffused efficiently through these pins in order to avoid the Hot Spot, and thus reduce the defected rate of chips. Flip-chip design has been used widely at present. For package-board codesign, en-gineers generally arrange the ball chart in the manual manner on experience. This process is iterative, time-consuming and it will lengthen the time-to-market (TTM) of products. [1] proposed a method of generating the BGA ball chart automatically by floorplanning pin-block, thus helped engineers respin the ball chart slightly and saved the arranging time dramatically.

Figure 1.1 shows the typical interface design flow for IC-package-board codesign and a new design flow based on proposed automation design process, respectively. In Fig-ure 1.1(a), we can observe that it spends about one week designating pin-out manually and estimating package size. Then, it spends another one week locating I/O buffer and pad manually and estimating die size. In order to tradeoff signal performance and package cost, engineers always take few weeks to rework package substrate and PCB layout, and rearrange pin-out until the all requirements are satisfied.

On the contrary, Figure 1.1(b) shows the proposed process in [1]. Comparing with manual works shown in Figure 1.1 (a), it completes the works more efficient. The run time of designating pin-out automatically and acquiring the minimum package size is less than five seconds and it just needs about half or one day to fine-tune pin-out. Similarly, if the idea of locating I/O buffer and pad automatically is available, the expected run time of optimizing die size is less than ten seconds. Furthermore, the run time of fine-tuning pad location is expectably half or one day. Obviously, it can shorten the runtime throughout the automation process and obtain the minimum package size and die size.

Figure 1.1: The typical flow and proposed approach in interface design for IC-package-board codesign. The focus of [1] is to automate pin-out designation and to minimize package size during design stage [1].

The focus of [1] is to automate pin-out designation and to minimize package size during package-board codesign stage.

Research [1] is the first attempt in solving flip-chip pin-out placement problem in package-board codesign. It evaluates the minimum package size which can accommodate all pins. Then, it will construct pin blocks, which consist of signal-pin blocks and power-pin blocks, and fill them into the minimum package to create the rough power-pin-out. Finally, the pin-block floorplan will be made into a square one by using an iterative algorithm. The square floorplan can accommodate all pin blocks and has no excess pin blocks in each side. We will accomplish the aforementioned issue in [1] and describe the detail of the automation process implementation in Chapter 3.

However, the method in [1] is less flexible in determining pin configuration chart. The reason is that, we should specify the order for all pin blocks in each side. Because of this order restriction, pin blocks with no freedom have no chance to be placed in better positions in each side of the chip and the results of this floorplan will incur a big cost on the wire length. While empty spaces appear on this floorplan, the worse positions (e.g. the pin blocks which are specified in side1 are assigned in side4 and have empty spaces between the pin blocks which belong to the same group, as shown in Figure 1.2 (b)) will cause another cost as well. Consequently, we have surveyed some methods about floorplanning and placement and try to improve the floorplanner in [1]. The target is to improve the design process and obtain the optimal pin-out.

We have studied some researches about floorplanning and placement which are as follows. Floorplans can be divided into two categories, the slicing floorplanning and non-slicing floorplanning. Many floorplanners are based on non-slicing floorplans [5], [6], [7], [8]. There are two major advantages of using slicing floorplans. Firstly, the one to one cor-respondence between skewed slicing trees and normalized Polish expression reduces the search space and leads to a faster runtime. By using simulated annealing method, the efficiency of this benefit is more significant. Secondly, the shape flexibility, that are the modules which may assume any shape permitted by its shape constraints (e.g. a range

Figure 1.2: While empty spaces appear on floorplan, the worse positions will cause another cost as well.

of possible aspect ratios), can be fully exploited to give a close to optimal final packing based on an efficient shape curve computational technique.

Because of some constraints by using slicing floorplans, there are also some interesting researches in non-slicing floorplans recently. Here are three methods, sequence-pair [3], B*-trees [9], O-Tree [10], which have been proposed for placement of hard modules. How-ever, the B*-trees [9] method can also handle soft modules. The sequence-pair method has later been extended to handle pre-placed modules [2] and soft modules [4]. Recently, there is a research that can handle all of the placement constraint simultaneously in floor-plan design [13], including pre-placed constraint, range constraint, boundary constraint, alignment, abutment, and clustering, etc. In order to handle soft modules, it has to solve a mathematical programming problem to determine the exact shape of each module numerous times in the floorplanning process. It wastes a lots of system’s resources and results in long runtime. By the way, the B*-trees method has been also extended to han-dle pre-placed modules [11] and boundary constraint [12]. Comparing with B*-trees [9] method, [11] provides more complete and stronger structure to solve pre-placed modules

problems. In floorplanning, it is important to allow users to specify placement constraints in order to get improvement of system’s performance, chip area or wire length, etc.

Three common types of placement constraints are pre-placed constraint, boundary constraint, and range constraint. For pre-placed constraint, we require a module to place exactly at a certain position in the final packing. In fact, the problem of floorplanning with obstacles can be solved by treating the obstacles as pre-placed modules. This prob-lem has been considered in both slicing and non-slicing floorplans [2], [4], [6], [11], [13]. For boundary constraint, we require a module to be placed along one particular side of the final floorplan: on the left, on the right, at the bottom, or at the top. This is useful when users want to place some specific modules along the boundary for getting good input-output connections. This problem is considered recently in both slicing and non-slicing floorplans [7], [12], [13]. For range constraint, we require a module to be placed within a given rectangular region in the final packing. This is indeed a more general formulation of the placement constraint problem and any pre-placed constraint can be written as a range constraint by specifying the rectangular region such that it has the same size as the module itself.

1.1

Our Contributions

In our proposed methodology, we can consider the core region as a pre-placed module which must be placed in the center of the final packing and pin-blocks as range constraint modules which must be placed within given rectangular regions such that there are no two rectangular blocks overlapping.

In this thesis, we exhibit the procedure of accomplishing this BGA package [1] auto-matically. We also develop a new representation for this special floorplanning requirement and improve the floorplanner in [1] by using range constraint and simulated annealing al-gorithm to place pin-blocks. The experimental results show that our improved pin-block

floorplanner has more flexibility on specifying critical parameters of the pin configuration and can obtain a better pin-out which has lower cost than that in [1]. Finally, we will show the experimental results of the method in [1] and our improved pin-block floorplanner, and the improvement of our improved pin-block floorplanner.

1.2

Organization of this Thesis

The organization of this thesis is as follows. Chapter 2 describes a key previous work and the detail of the automation process implementation in [1]. Chapter 3 describes our improved pin-block floorplanner which is implemented by simulated annealing algorithm with range constraint. Chapter 4 shows the experimental results. We draw conclusions in Chapter 5.

Chapter 2

Pin-Out Designation and Package Size

Optimization by Pin-Block Floorplanning

In this chapter, we introduce a novel and efficient approach [1] to designate pin-out au-tomatically for flip-chip BGA package when designing chipsets. This approach has taken practical experiences and techniques into account, such as signal integrity, power delivery and routability. It can not only reduce the runtime by means of automation process, but also guarantee the minimum package size and the minimum core size during design stage.

2.1

Overview of Fast Flip-Chip Pin-Out Designation Respin

by Pin-Block Design and Floorplanning

2.1.1

Package-Board Codesign by Considering Signal Integrity and Power

Delivery

Figure 2.1 depicts a sketch of PCB layout. Generally the length of signal net from package pin to component or connector on PCB is the primary contributor to parasitic inductance which will make package pins exacerbate simultaneous switching noise (SSN). In order to minimize the physical length of the package pins thus reduce the total parasitic

induc-Figure 2.1: A general layout of PCB board. The location of pins on IC package should be restricted in specific regions to meet minimum net-length [1].

Figure 2.2: The visible package substrate of chipsets.

tance, the signal pins should be allocated and restricted in the particular region according to the certain location of corresponding components or connectors.

Figure 2.2 represents a diagram of a complete flip-chip package. The top layer denotes the die which consists of some logic circuits, I/O pins and I/O buffers. The middle layer denotes the package substrate. Then, the bottom layer denotes the printed circuit board. There are some important connecting devices including PCB components or connectors, etc. on the board. By the way, this diagram shows the visible package substrate of the real industrial case.

Figure 2.3 shows the simplified cross-section of a flip-chip package which is mounted on PCB board. The solder bumps are considered as a bridge that is used to connect the die and the substrate, and the solder balls are exploited to connect the substrate and the PCB board. Based on experienced method, the bumps which are beneath the die and located close to die edge will be routed signal nets through package top layer. On the contrary, the bumps which are located around the core of die will be routed signals through vias and fanned out nets on package bottom layer. For package pins, the solder balls are routed signal nets in the same rule to share finite routing resource.

Figure 2.3: The cross-section of a flip-chip package which is mounted on PCB board [1].

For routability, the routing issues should be considered including the net width, spac-ing, the distance between the pad pitches and so on. Thus, these factors will influent the excess row number used for placing signal pins. By demonstrating in [1], the space between two pads can only be penetrated by two nets. That means only 3 signal nets can be fanned out on PCB top layer. Another 3 signal nets on the same column can be routed through vias and fanned out on PCB bottom layer. In addition, the outer pins include power and ground pins which are routed through vias to the second and third layer of PCB board, besides the signal pins. So, the average row number of outer pins is 8.

As for signal integrity, return path inductance should be considered as well. The unfa-vorable placement and number of return path pin, power or ground, will maximize current return loops and increase return path inductance. This will dramatically degrade signal integrity and exacerbate radiated emissions. The optimal pin designation is to place signal pin and power or ground pin proximally close to each other, so that each signal pin can be tightly coupled to a return path pin. This will minimize the effect of the return path inductance. However, this optimal design will create such signal-pin blocks which have fewer signal pins within a large block area. [1] addresses six proposed signal-pin patterns for user to make decision that which pattern is most properly exploited for placing signal pins. There exists tradeoff between signal performance and package cost.

Figure 2.4: A complete pin block includes signal-pin block and its related power-pin block. It is located on the region close to corresponding component on PCB [1].

pins for individual signal configuration. While the signal-pin block is constructed, the proposed automation process will create the power-pin block then place it adjacent to the related signal-pin block. The signal-pin block and the power-pin block will be formed into a complete pin block, as shown in Figure 2.4.

2.1.2

Pin-Out Designation Automation by Pin-Block Construction and

Floorplanning

In the stage of pin-block construction, designers should determine pin configuration chart, shown in Figure 2.5. The pin configuration chart include all critical parameters defined for placing signal pins, including signal-pin name, selected signal-pin pattern (pattern), the own specific bus (group), the distribution region (side), placement sequence (order), power-pin name and the number of power pins.

Figure 2.5: An example of pin configuration chart. In this pin configuration we can define specific information as inputs of our proposed automated approach [1].

Figure 2.6: A minimum package size can be obtained after we designate and floorplan all pin blocks [1].

tion will be obtained, shown in Figure 2.6. A_ij denote the specific bus, where i and j are to represent side and order that blocks are located on and defined in pin configuration by designer. Furthermore designer can acquire parameters w_ij and h_ij (w and h represent the width and height of each block respectively). At the same time, parameters E₁ to

E₄ can be evaluated from this rough pin designation (E₁ to E₄ represent the width or height of the empty or excess area in each side of minimum package model). The next step is to minimize package size by mathematical programming and acquire a feasible pin designation. The problem is formulated as follows:

M inimize f =
j=1,3 (
i w_ji+ E_j)h_j+
j=2,4 (
i h_ji+ E_j)w_j + F subject to W = w₄+
i w_1i+ E₁ = w₂ +
i w_3i+ E₃ (2.1) H = h₁+
i h_2i+ E₂ = h₃ +
i h_4i+ E₄ (2.2) W = H (2.3) E₁+ E₂ + E₃+ E₄
0 (2.4)

where w_1i, h₁, w₂, w_3i, h₃, h_4i, w₄ can be evaluated in the previous step, E₁ to E₄ represent the width or height of the empty or excess area in each side of minimum package model, and F represent the area of core region, shown in Figure 2.6. Equation (2.1) to (2.3) will restrict the shape of package to be square. The purpose of Equation (2.4) is to insure that the minimum package size can accommodate all pin blocks with almost no void pin positions.

The final step of proposed methodology is to floorplan pin blocks, that is, to fine-tune the location of pins in the excess area and fill them into the adjacent empty area. Figure 2.6 shows an example to represent how the rough floorplan can be translated to a square one.

Figure 2.7: The design flow of automation process.

2.2

Designation Automation Flow

At the beginning of this procedure, we show the design flow of automation process below (as in Figure 3.1).There are two critical parts in this design flow, Part I and Part II, respectively. There are three steps in Part I, evaluate pin block, construct pin block and evaluate minimum package size, respectively. We should consider several constraints among Part I. Constraints 1-1: considered the location of the components on PCB. The longer wire length of signal net has been pulled, the larger parasitic instance is cre-ated. The parasitic instance will cause package pins to exacerbate simultaneous switching noise (SSN). Thus, the signal pins should be placed according to the position of relative components and connectors on print circuit board. Constraints 1-2: package size vs. ball number. Because of the routability on PCB top layer, the space between two pads can only be penetrated by two nets. That means the locations of PCB pad near PCB edge can only allow three signal pins on one column. Other symmetrical four signal pins closed to the core of die can place solder balls through vias. As a result, the average of row number of outer-pin (power-pin, ground-pin and signal-pin) will be predefined as eight. Constraints 1-3: pin patterns about the top and bottom layer routing. Making a decision

between these six patterns is based on experience of engineers. According to the charac-teristics of signal-pin patterns, engineers can select an adaptable pattern for designating pins.

There are two steps in Part II, fill pin block in minimum package model to create

rough pin-out and shift pin block to obtain final pin-out. User defines the signal pins

in which side and in which group. Then, our program constructs the signal-pin blocks with chosen patterns and also builds the specific power-pin blocks for related interface. After previous procedure, it will group the signal-pin blocks and the power-pin blocks into modules such as pin blocks and fill pin blocks in the minimum package model to create the rough pin-out floorplan. In next step, we propose an algorithm to regulate the exceeding region of the rough pin-out flooplan into a square one which is accommodated all pin blocks.

2.3

Pin-Block Floorplanning

At present, we just get a rough floorplan which owns the property described previously with the minimum core size and the minimum package size. However, this rough floorplan still has pin block in excess area and is not consistent with the size of minimum package floorplan. So, we proposed an simple algorithm to make the rough floorplan into a square one. This algorithm does not destroy the position of pin block enormously and make the location of pin block as near to the corresponding side of the chip as possible. The algorithm is shown as follows:

Algorithm:

1. i← 1 //start from side 1

2. i− 1 ← 4, iff i = 1 ; i + 1 ← 1, iff i = 4 3. while (E_i < 0) do, for i{1, 2, 3, 4}

4. if (E_i = 0&&E_i < 0)

6. shift pins clockwise //fill the pin block into empty area in last side until the current E_i value is zero

7. E_i ← 0, E_i−1 ← E_i−1+ E_i

8. else

9. shift pins anticlockwise //split the pin block in excess area then group it into next side

10. E_i ← 0, E_i+1 ← E_i+1+ E_i 11. i← i + 1 //check next side

12. until all E_i values are large than or equal to zero

The algorithm starts form the side1 of the rough floorplan. It will check whether this side have excess pin block. If this side has excess blocks, the algorithm will check the empty space of the previous side and the next side. If the space of the previous side is greater than the other, the algorithm will shift pins in the clockwise direction and fill the pin blocks which are in the excess area into the empty area in the previous side until the current value of E_i is zero. Otherwise, it will shift pins in the anticlockwise direction and split the pin blocks in excess area into one module, then it will group it into the next side. Every iteration of this procedure will check the value of E_i in each side whether it is greater than zero. While all values of E_i in every side are greater than zero, then the algorithm will stop and represent the final square floorplan. Next, We will implement two real cases in practice, that will be more clearly about describing this automation process. The program will gather statistics about the columns of pins in each side by means of feeding the program with the pin-lists. Afterwards, the program solves the linear problem to computer the minimum core size and the minimum package size. Figure 2.8 describes the columns of pins in each side, the minimum core size, the minimum package size, the columns in excess region of the package and the sum of all values of E_i.

The rough floorplans of this two cases are showed as in Figure 2.9 and Figure 2.10 respectively. In Figure 2.9, we can observe that the side1 has columns in the excess area (E₁ = −3), the side2 has empty space (E₂ = 2), the side3 has excess space (E₃ = −6)

Figure 2.8: (a) Result in Case I. (b) Result in Case II.

and the side4 has columns in empty area (E₄ = 7) in case I. In Figure 2.10, we find that the side1 has excess space (E₁ = −5), the side2 has columns in excess area (E₂ = −1), the side3 has columns in excess area (E₃ =−3) and the side4 has empty space (E₄ = 12) in case II. Next, our program will implement the simple algorithm described above. The rough floorplan will be shifted pins and will be made as a square one.

Figure 2.11 and Figure 2.12 describe the proceedings of carrying out the algorithm which makes the rough floorplan as a square one. In Figure 2.11 (a), the side1 has three columns of pin blocks in excess area (E₁ = −3) and, thus, the algorithm will check the empty space of the previous side (E₄) and the next side (E₂). The space of the previous side is greater than the other (i.e. E₄ = 7 > E₂ = 2), the algorithm will shift pins in the clockwise direction and fill the pin blocks which are in the excess area into the empty area in the previous side until the current value of E_i (E₁) is zero. The E₁ will be set to 0, E₄ is equal to 4 (i.e. 7− 3) and E₂ E₃ are the same, as shown in Figure 2.11 (b). Next step, we check the side2 (in Figure 2.11 (b)). Because the values of E₂ is greater than zero (E₂ = 2), so it is kept in the original status. Then, the side3 (in Figure 2.11 (b)) has six columns of pin blocks in excess area (E₃ = −6). The space of the next side is

Figure 2.9: Rough floorplan in Case I. (uppercase P denotes the minimum package size, uppercase C denotes the minimum core size, uppercase N denotes nothing and pin-block groups are denoted in shaded blocks.)

Figure 2.10: Rough floorplan in Case II. (uppercase P denotes the minimum package size, uppercase C denotes the minimum core size, uppercase N denotes nothing and pin-block groups are denoted in shaded blocks.)

Figure 2.11: Diagrams for interpretation of carrying out the algorithm from the rough floorplan to the final floorplan in Case I.

Figure 2.12: Diagrams for interpretation of carrying out the algorithm from the rough floorplan to the final floorplan in Case II.

greater than the other (E₄ = 4 > E₂ = 2) and, thus, the algorithm will fill the pin blocks which are in excess area into empty area in next side (E₄). The E₃ will be set to 0, E₄ is equal to−2 (i.e. 4 − 6) and E₁ E₂ are the same, as shown in Figure 2.11 (c). Next step, we check the side4 (in Figure 2.11 (c)) and side4 has two columns of pin blocks in excess area (E₄ =−2). The space of the previous side is equal to the other (E₃ = E₁ = 0) and, thus, the algorithm will fill the pin blocks which are in excess area into the next side (E₁). Then (E₄) will be set to 0, (E₁) is equal to −2 (i.e. 0 − 2), as showed in Figure 2.11 (d). At present, it is just implemented in one cycle. In fact, the algorithm is iterative and will implement repeatedly until the value of E_i in each side is greater than zero. Otherwise, it will never stop. Figure 2.13 shows the final floorplan of case I and is accurate at the corresponding Figure 2.11 (e). Case II is a more general case about this algorithm, as shown similarly in Figure 2.12 and Figure 2.14.

Figure 2.13: Final floorplan in Case I. (uppercase P denotes the minimum package size, uppercase C denotes the minimum core size, uppercase N denotes nothing and pin-block groups are denoted in shaded blocks.)

Figure 2.14: Final floorplan in Case II. (uppercase P denotes the minimum package size, uppercase C denotes the minimum core size, uppercase N denotes nothing and pin-block groups are denoted in shaded blocks.)

Chapter 3

Improved Pin-Block Floorplanner

Chapter 2 shows the detail of implementing the automation process in [1]. The floorplan-ner in [1] exists some problems which have been described before. That is, the method in [1] is less flexible in determining pin configuration chart and the non-well positions generated from [1] will cause another cost as well. In this chapter, our target is trying to solve those problems and we improve the floopplanner in [1] by range constraint to place pin-blocks. Meanwhile, improved pin-block floorplanner is implemented by using the simulated annealing algorithm.

3.1

Problem Definition

The minimum package size has been evaluated from Chapter 2 and we use the minimum package size directly as a graphic frame of our problem. In our problem, the final packing is consisted of core block and several pin blocks around core block. The core block of the packing is just denoted as a module which is restricted by pre-placed constraint and the pin blocks around the core block are considered as modules that are restricted by range constraint [8]. Figure 3.1 briefly describes the placement of the core block and shows how the pin blocks without range constraint are placed around the core block.

Figure 3.1: Final packing is consisted of core block and pin blocks without range constraint around the core block.

considered as a hard module with fixed orientation and the height of module C is denoted as h_core and the width of it is denoted as w_core. The core block must be placed with its lower left corner at (w₄, h₁) in the final packing. Because the pre-placed constraint is a special case of range constraint in which the module has no freedom of movement, so module C can be specified by a range constraint requiring the module to be placed within the rectangular region R_core={(x, y)|w₄  x  w₄+w_core, h₁  y  h₁+h_core}. Then, pin blocks without range constraint are placed around the core block. For side1, the height of pin blocks is defined as h₁. Pin blocks are placed with fixed orientation and are assigned with its lower left corner at (w₄, 0). Pin blocks are also placed toward the increasing

direction of the x coordinate. Analogically, the height of pin blocks placed in side2 is defined as w₂ and pin blocks are assigned with its lower left corner at (w₄+ w_core+ w₂, h₁) toward the increasing direction of the y coordinate. And pin blocks placed in side3 with its height as h₃ are assigned with its lower left corner at (w₄+ w_core, h₁+ h_core+ h₃) toward

Figure 3.2: Pin blocks with the range constraint which must be placed within the given rectangular region.

the decreasing direction of the x coordinate. At last, pin blocks placed in side4 with its height as w₄ are assigned with its lower left corner at (0, h₁+ h_core) toward the decreasing direction of the y coordinate. This manner of placing pin blocks is equally like the rough floorplanning which is described before in Chapter 2. However, our problem defines the range constraint to floorplan pin blocks which is placed around the core block.

Figure 3.2 briefly shows an example about the definition of the range constraint for side1. We specify the rectangular region called rangeSide1 and pin blocks with range constraint must be placed within rangeSide1. Range constraints are listed below and shown in Figure 3.3:

• rangeSide1 = {(x, y)|0  x  w4+ wcore+ w2, 0 y  h1+ hcore/2}.

• rangeSide2 = {(x, y)|w4+ wcore/2 x  w4+ wcore+ w2, 0 y  h1+ hcore+ h3}.

• rangeSide4 = {(x, y)|0  x  w4+ wcore/2, 0 y  h1+ hcore+ h3}.

A feasible packing must satisfy all placement constraints (including the pre-placed constraint and the range constraint). A feasible packing is a nonoverlap placement of all pin blocks in it, and all pin blocks can be accommodated within the feasible packing. Our target is to improve the floorplanner in [1] by using the range constraint and place pin blocks into better positions on package. And our objective function is formulated as W+ρP, where W is the sum total wire length which is calculated the Manhattan distance between pins and the edge of each side which the pins belong to, P is a penalty term which is an estimation of the square distance between pins and their desired positions in each side, and ρ is a user-defined balance constant which controls the relative importance of wire length and penalty term in the objective function. Meanwhile, improved pin-block floorplanner is implemented by using simulated annealing algorithm.

3.2

Range Constrained Pin-Block Sequence Pair (RCPBSP)

We propose a novel sequence-pair representation to construct a scheme of our problem. This representation describes all varieties of perturbations in placing the pin blocks around the core block. For case I, the representation is resulted in s = (123456, I1 II1 II2 III1 III2 IV1). The first sequence denotes groups (i.e. group1, group2,. . ., group6). The second sequence means the range constraint. They are I, II, III and IV, that is, rangeSide1,

rangeSide2, rangeSide3 and rangeSide4, respectively. The number behind the rangeSide

means the order of groups which are placed in the same range constraint. Figure 3.4 shows some examples of the representation in our problem.

In Figure 3.4, all floorplans are feasible packings which satisfy the range constraint in each side and the representation is showed under each graph. In Figure 3.4 (a), the placement of pin blocks is started from group1 with rangeSide1 and the sequence of groups is showed as (123456) in the anticlockwise direction. In Figure 3.4 (b), the placement is

Figure 3.3: For the other sides, pin blocks with the range constraint must be placed within

have done pair-interchanged exchanging in this stage. Similarly, the representations of Figure 3.4 (c) and Figure 3.4 (d) are showed in the same way. And later we will describe the perturbations of this representation in detail.

3.3

Floorplanning with Range Constraint

In the aforementioned description, we know that all groups must be placed within a given rectangular region. Figure 3.5 illustrates an example where five groups with range constraint are restricted in rangeSide1. (group a, b, c, d and e, respectively). Because of hard modules, each group has the same height as eight. The width of each group is depended on the amount of signal pins and the pattern selected by user. So, the only thing that we care about is the total width of groups which must be placed within rangeSide1, where w_a, w_b , w_c, w_d and w_e denotes the width of group a, b, c, d and e, respectively. The total width of groups in rangeSide1 is w_s1 = w_a + w_b + w_c + w_d + w_e. And the definition of rangeSide1 is shown as follows and illustrated in Figure 3.5 (b):

• Rs: The start point of rangeSide1, Rs = 0.

• Re: The end point of rangeSide1, Re= Rs+ hcore/2 + h1+ wcore+ w2+ hcore/2.

• Cs: The check start point of groups restricted by rangeSide1, Cs= Rs+ rda.

• Ce: The check end point of groups restricted by rangeSide1, Ce= Cs+ ws1.

The minimum core size (C) of the chip is evaluated as h_core ∗ w_core. And rd_a means random selected start-point of group a where group a should be placed from. Firstly, we consider the allowed range of all groups. For group a, the allowed range of module a can be denoted as ar_a = R_e−w_a, as shown in Figure 3.5 (c). The random selected start point (i.e. rd_a) should satisfy the restricted range R_s  rd_a  ar_a. Similarly, other groups are all obeying this rule of randomly selecting start point. A feasible solution of the floorplan

• Random selected start-point should be within the restricted range: Rs rda ara.

• Total width of groups restricted by rangeSide1 should be within the spreading

length of the given rectangular region: C_s
R_s and C_e  R_e.

In addition, the start point of groups in rangeSide2 is carried on the checked end-point (C_s) of groups in rangeSide1. Groups in rangeSide2 are placed from the start point at (C_s + 1) and the order of groups is following the representation mentioned before. Analogously, the aforementioned rules are proper for other range constraints in each side. Consequently, we will acquire a feasible solution as long as the range constraints of the four sides are all satisfied and non-overlapping modules appear in the final packing.

3.4

RCPBSP Packing by Simulated Annealing

3.4.1

Solution Perturbation and Cost Function

Firstly, our problem is basically implemented on simulated annealing algorithm. We briefly describe perturbations in our representation.

• In the first step, we randomly select which rangeSide should be perturbed.

• In the second step, we randomly select any two groups of rangeSide selected in first

step and do pair-interchanged exchanging. If selected rangeSide has more than two groups, then the two groups selected in first step have done pair-interchanged exchanging. Otherwise, the sequence of our representation is still the same.

• In the final step, we randomly select the start point of the group with the first order

in selected rangeSide and rearrange other groups by following the sequence of the representation until all rangeSides have been considered.

Figure 3.6: An estimation of wire length between signal pins belonged to rangeSide1 and the edge of side1.

signal pins belong to. P is a penalty term which is an estimation of the square distance between pins and their desired positions in each side, and ρ is a user-defined balance constant which controls the relative importance of wire length and penalty term in the objective function.

For rangeSide1, Figure 3.6 describes an estimation of wire length between signal pins belonged to rangeSide1 and the edge of side1. There are three parts of the estimation of the wire length. They are signal pins with rangSide1 placed in side4, signal pins with rangSide1 placed in side1 and signal pins with rangSide1 placed in side2. And the computation is translated as following form:

• Length = |x − (−1)| + |y − (−1)|,

0 x  w₄, 0 y  (h₁+ h_core/2) • Length = |y|,

Figure 3.7: An estimation of the penalty term which is the distance between pins and their desired positions in rangeSide1.

• Length = |x − (w4+ wcore+ w2+ 1)| + |y − (−1)|,

(x₄+ w_core) x  (w₄+ w_core+ w₂), h₁  y  (h₁+ h_core/2)

And other rangeSides are also following the manner of estimating the wire length. Another estimation term of cost function is the penalty term and the evaluation of penalty term is also formulated as following form. But just for rangeSide1, as shown in Figure 3.7. • P enalty = [|y| + |(w4− Xl)|]2, 0 x  w₄, 0 y  (h₁+ h_core/2) • P enalty = [|(x − Xl)|]2, w4  x  Xl, 0 y  h1 • P enalty = 0, Xl  x  Xr, 0 y  h1 • P enalty = [|(x − Xr)|]2,  x  (w  y  h

• P enalty = [|Xr− (w4+ wcore+ w2)| + |(y − (h1))|]2,

(w₄+ w_core) x  (w₄+ w_core+ w₂), h₁  y  (h₁+ h_core/2)

Where X_ldenotes the left edge of the given desired position in the side1 and X_rrepresents the right edge of the given desired position in the side1. RangeSide2, rangeSide3 and

rangeSide4 are also following this manner of estimating the penalty term.

Figure 3.8 reveals the desired positions in other three rangeSides and the purpose of this specification is hopefully floorplanning the pins to the center of each side approxi-mately. Besides the desired position assigned weight centrally, as shown in Figure 3.9 (a). There are two weight behaviors including left-position and right-position in order to make the final floorplan have rotating ability. Figure 3.9 (b) and Figure 3.9 (c) show the ro-tating ability of the final floorplan in clockwise direction and in anticlockwise direction, respectively.

3.4.2

Annealing Schedule

Our problem is implemented by using range constraint based on simulated annealing algorithm [16] and our annealing schedule is shown as follows:

Simulated Annealing Schedule(S₀, T₀, α, β, M , M axtime): 1. begin 2. T = T₀; 3. S = S₀; 4. T ime = 0; 5. repeat 6. repeat

7. N ewS = range constraint(S);

8. H = (Cost(N ewS)− Cost(S));

Figure 3.8: Reveals the desired positions in other three rangeSides and the purpose of this specification is hopefully floorplanning the pins to the center of each side approximately.

Figure 3.9: Weight behavior : let the whole floorplan have rotate ability. (a) Center. (b) Clockwise. (c) Anticlockwise.

10. accept the solution; 11. M = M − 1; 12. until (M = 0) 13. T ime = T ime + M ; 14. T = α∗ T ; 15. M = β∗ M;

16. until (T ime
MaxT ime);

17. Output Best solution found;

18.End. (* of Simulated Annealing Schedule*)

Where S₀ is the initial solution, T₀ is the initial Temperature(defined as 100), α is the cooling rate(a typical value for α is 0.9), β is a constant(defined as 2), M axtime is the total allowed time for the annealing process(defined as 500), M represents the time until the next parameter update(defined as 5),h is difference in costs, and T is the temperature.

Range constraint function generates N ewS of any given solution S and Cost function evaluates the cost values of N ewS and S. In our annealing schedule, the initial solution is generated by several steps which are described as follows:

• In the first step, we randomly select a rangeSide and randomly select a group in

that selected rangeSide.

• In the second step, we randomly select the start point of the selected group and

place it, then we rearrange other groups which belong to the selected rangeSide in order.

• In final step, we rearrange other groups by following the original order which is

specified by user until all rangeSides have been considered.

The annealing process is implemented iteratively to get a feasible solution with minimum cost and terminates when the total allowed time is less then the accumulative time.

Chapter 4

Experimental Results

We implemented our approach in the C++ Programming language and the platform is on intel(R) Pentium(R) M CPU 1.7GHz work station with 512 MB memory. We used four industrial cases as our benchmarks (case I, case II, case III, case IV). Table 4.1 shows the summary of pin configuration charts about these four cases.

We carried out two sets of experiments. For the first set, we compared SA-random floorplanner and our improved pin-block floorplanner with the method in [1] by consider-ing wire length as cost function. The experiment results and improvement are shown in Table 4.2, Figure 4.1 and Figure 4.2. Here we propose another method called SA-random floorplanner to implement these four cases. The main difference between SA-random method and our method is the order of placing groups. In SA-random method, although the generation of initial solution is the same with our method, but the perturbation is still using the manner of generating the initial solution and it place groups by following the original order which is specified by user. However, our method places groups by following RCPBSP and has more flexibility than SA-random method. In Figure 4.1 and Figure 4.2, Case I and Case II have the same amount of groups and the improvement of our method is equally like that of SA-random method. But, there are obvious improvements of our method in Case III and Case IV while the amount of groups increases gradually. In Fig-ure 4.2, we can see that our improved pin-block floorplanner has improved over [1] in wire

Table 4.1: The summary of these four industrial cases

Group Signal Power Total

NO. -pin -pin pin

NO. NO.

CaseI 6 254 80 334

CaseII 6 346 48 394

CaseIII 20 510 168 678

CaseIV 25 504 216 720

length and there is a incremental trend of the improvement in wire length while the size of case increases gradually.

In the second set of experiments, we consider wire length and the penalty term si-multaneously in cost function. And the penalty term has three different desired positions, including Left, Center and Right. The purposes of Left, Center and Right are hopefully floorplanning the pin-blocks to the left, center and right of each side approximately, re-spectively. The results and the improvement are shown in Table 4.3, Table 4.4, Table 4.5, Figure 4.3 and Figure 4.4. Our improved pin-block floorplanner has improved over [1] in three different desired positions. In order to comparing with [1], pin-blocks are hopefully placed in the center of each side approximately and Center becomes the most important desired position that we care. For Center, there is the improvement at least more than a 32 percent over [1] and Table 4.5 clearly shows that wire length and penalty term are both improved in CaseII, CaseIII and CseIV. In addition, we also use the results of the method in [1] to be our initial solutions. Then, we get the same results by implement-ing our improved pin-block floorplanner. Because, our method is implemented by usimplement-ing simulated annealing algorithm to place pin-blocks. Our method will be implemented it-eratively until the global solution is found.

Table 4.2: Experimental results of the method in [1] and our improved pin-block floor-planner by considering wire length as cost function

SA-random Our improved

[1] floorplanner pin-block Improvement(%)

floorplanner

Data n Wire length SA Our

CaseI 6 1199 1149 1149 +4.17 +4.17

CaseII 6 1712 1640 1639 +4.21 +4.26

CaseIII 20 2406 2226 2225 +7.48 +7.52

CaseIV 25 2442 2240 2170 +8.27 +11.14

Figure 4.1: Shows the improvement of wire length in four industrial cases ([1] vs. SA-random floorplanner).

Figure 4.2: Shows the improvement of wire length in four industrial cases ([1] vs. our improved pin-block floorplanner).

Figure 4.3: Illustrates the improvement of SA-random floorplanner by considering wire length and penalty term simultaneously in four industrial cases with ρ=5 ([1] vs. SA-random floorplanner).

Table 4.3: Shows experimental results of the method in [1] and SA-random floorplanner. Wire length and penalty term are considered simultaneously in cost function

SA-random

[1] floorplanner

Data n Sum=wLength+ ρ *penalty(ρ =5)

Left Center Right Left Center Right

Penalty 12832 6200 3958 3156 2619 3156 CaseI 6 wL 1199 1199 1199 1361 1216 1158 Sum 65359 32199 20989 17141 14311 16938 Penalty 13668 8708 10838 6605 5802 7808 CaseII 6 wL 1712 1712 1712 1994 1650 1750 Sum 70052 45252 55902 35019 30660 40790 Penalty 60665 27048 29744 19936 20853 21377 CaseIII 20 wL 2406 2406 2406 3294 2336 2765 Sum 305731 137646 151126 102974 106601 109650 Penalty 73239 31590 28750 21264 20348 25117 CaseIV 25 wL 2442 2442 2442 2761 2263 2998 Sum 368637 160392 146192 109081 104003 128583

Table 4.4: Shows experimental results of our improved pin-block floorplanner. Wire length and penalty term are considered simultaneously in cost function

Our improved pin-block floorplanner

Data n Sum=W+ ρ *P(ρ =5)

Left Center Right

Penalty 3156 2619 3156 CaseI 6 wL 1361 1216 1158 Sum 17141 14311 16938 Penalty 6605 5802 7808 CaseII 6 wL 1994 1650 1750 Sum 35019 30660 40790 Penalty 13786 15579 18331 CaseIII 20 wL 2890 2236 2723 Sum 71820 80131 94378 Penalty 18018 16976 18645 CaseIV 25 wL 2917 2201 2447 Sum 93007 87081 95672

Table 4.5: Shows the improvement of SA-random floorplanner and our improved pin-block floorplanner by considering wire length and penalty term simultaneously

Improvement(%)

SA-random Our improved

floorplanner pin-block

floorplanner

Data n Left Center Right Left Center Right

Penalty + + + + + + CaseI 6 wL - - + - - + Sum +73.77 +55.55 +19.3 +73.77 +55.55 +19.3 Penalty + + + + + + CaseII 6 wL - + - - + -Sum +50.01 +32.25 +27.03 +50.01 +32.25 +27.03 Penalty + + + + + + CaseIII 20 wL - + - - + -Sum +66.32 +22.55 +27.44 +76.51 +41.78 +37.55 Penalty + + + + + + CaseIV 25 wL - + - - + -Sum +70.41 +35.16 +12.05 +74.77 +45.71 +34.56

Figure 4.4: Illustrates the improvement of our improved pin-block floorplanner by consid-ering wire length and penalty term simultaneously in four industrial cases with ρ=5 ([1] vs. our improved pin-block floorplanner).

length and penalty term in Center, where group 1 and 2 are constrained to be placed within rangeSide1 which is formed as a dotted line rectangle in Figure 4.5. Similarly, group 3 is within rangeSide2, group 4 is within rangeSide3, group 5 and 6 are within

rangeSide4. By the way, the dotted line rectangles of other three rangeSide are not

shown in Figure 4.5. Comparing with the final floorplan of CaseII which is shown in Fig-ure 2.14, our packing avoids the empty positions appearing in non-well positions which will cause extra cost on wire length. And our packing also owns flexibility on the order of placing groups.

Figure 4.5: Our result packing of CaseII. The cost function considers wire length and penalty term in Center simultaneously.

Chapter 5

Conclusion and Future Work

We have proposed an improved pin-block floorplanner with range constraints in pin-out designation automation in flip-chip BGA package-board codesign. Our approach not only owns more flexible capability on placing groups, but also can avoid the non-well positions appearing in result packing. Furthermore, our approach can rotate the floorplan in final packing by exploiting the penalty term. It provides three different desired positions for user to select which floorplan is the most proper one in final packing. Experimental results reveal that our approach is better and more flexible than the method in [1].

About the future works, timing constraints is a critical issue of influencing the per-formance of our chip. The timing delay is accumulated outward form die to board and it could be considered in die-package-board codesign simultaneously. We should take the timing constraints into account to define our performance objectives. At the same time, we should extend our research inward in die-package codesign and try to place logic closer together so shorter routing resources can be used. In addition, the direction of placing pin blocks in four corners of result packing is pre-defined. Maybe, we can make the direction flexible and depend on which way can cause the lower cost.

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