無電鍍鈷鎢磷薄膜對銲錫之擴散阻障特性研究

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國立交通大學

材料科學與工程學系

博士論文

無電鍍鈷鎢磷薄膜對銲錫之擴散阻障特性研究

A Study on the Diffusion Barrier Characteristics of

Electroless Co(W,P) Thin Films to Solders

學生：潘虹君（Hung-Chun Pan）

指導教授：謝宗雍博士（Dr. Tsung-Eong Hsieh）

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無電鍍鈷鎢磷薄膜對銲錫之擴散阻障特性研究

學生：潘虹君指導教授：謝宗雍博士國立交通大學材料科學與工程學系

摘要

本論文研究以無電鍍（Electroless Plating）技術製備非晶態（Amorphous）與複晶態（Polycrystalline）之鈷鎢磷（Co(W,P)）薄膜，探討其對銲錫的擴散阻障（Diffusion Barrier）特性。研究的銲錫種類包括共晶錫鉛（Eutectic PbSn）、錫鉍（SnBi）與錫銀

銅（SnAgCu，SAC），試片經液態時效（Liquid-state Aging）與固態時效（Solid-state

Aging）後，分析 Co(W,P)與銲錫的合金反應及擴散阻擋能力。PbSn 與 SAC 系統並計算其介金屬化合物（Intermetallic Compound，IMC）成長之活化能（Activation

Energy，Ea），並以推球試驗（Ball Shear Test）評估界面接合強度與破壞模式。

時效測試結果顯示，經液態時效之非晶態 Co(W,P)與銲錫反應生成之 IMC，在

PbSn 與 SnBi 系統中 IMC 主要為 CoSn2 及 CoSn3 相，SAC 系統中 IMC 則為

CoSn3+(Co,Cu)Sn3 相；隨著時效時間的增加，IMC 會因球化（Spallation）而進入銲

錫中，同時反應界面生成一由奈米尺度之 IMC 晶粒組成的複晶態富磷層（P-rich

Layer），未反應的 Co(W,P)則有再結晶且析出 Co2P 相等現象。固態時效試驗則觀察

到層狀 IMC 生成於富磷層之上，且無球化行為，且未反應之 Co(W,P)薄膜仍維持非晶態。

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態之富鎢層（Amorphous W-rich Layer）上，且無球化行為；此一非晶態富鎢層無法阻擋銲錫與 Co(W,P)後續的合金反應，故阻障之能力應肇因於原子鍵結之特性，材料之結晶結構為何不宜做為擴散阻障機制的分類依據。

擴散阻障特性之研究結果顯示，非晶態 Co(W,P)為複合式擴散阻障層，即犧牲型擴散阻障層（Sacrificial-type Barrier）與填塞型阻障層（Stuffed-type Barrier）之組

合；複晶態 Co(W,P)則主要為犧牲型擴散阻障層。IMC 成長之 Ea計算顯示，PbSn/非

晶態 Co(W,P)系統之 Ea = 338.6kJ/mole，PbSn/複晶態 Co(W,P)系統之 Ea = 167.5

kJ/mole；SAC/非晶態 Co(W,P)系統之 Ea = 110.7 kJ/mole，SAC/複晶態 Co(W,P)系統之

Ea = 81.8 kJ/mol。

推球測試結果顯示 PbSn 系統及 SAC/poly-Co(W,P)試片之破壞模式以延性破壞

（Ductile Mode）為主，而 SAC/-Co(W,P)試片在短時間熱處理下主要是界面破斷

（Interfacial Break Mode），若經長時間熱處理則轉為銲墊舉離模式（Pad Lift Mode）。

分析結果顯示銲墊舉離模式肇因於高磷成分的非晶態 Co(W,P) 有礙於銲錫之潤濕性

（Wettability）而降低界面接合強度，且 Co2P 相析出及非晶態 Co(W,P)再結晶現象將

導致未反應之 Co(W,P)脆化及熱膨脹係數改變進而產生熱應力。故無電鍍 Co(W,P)薄膜之磷含量不僅影響界面合金反應之行為，也是影響其擴散阻障能力與銲錫接點可靠度的重要因素。

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A Study on the Diffusion Barrier Characteristics of Electroless Co(W,P)

Thin Films to Solders

Student: Hung-Chun Pan Advisor: Dr. Tsung-Eong Hsieh

Department of Materials Science and Engineering National Chiao Tung University

Abstract

Diffusion barrier characteristics of electroless amorphous and polycrystalline Co(W,P) (termed -Co(W,P) and poly-Co(W,P) hereafter) to eutectic PbSn, SnBi and SnAgCu (SAC) solders are investigated in this study. The samples were treated by liquid- and solid-state aging tests and the alloy reactions and diffusion barrier capabilities were evaluated. For PbSn and SAC systems, the activation energy of intermetallic compound (IMC) growth (Ea), interfacial bonding strength and failure modes were also analyzed.

In all solder/-Co(W,P) samples subjected to liquid-state aging, spallation of IMC into solder, formation of a nano-crystalline P-rich layer at reacting interface, and the recrystallization of Co(W,P) containing Co2P precipitates were observed. The IMCs

observed in PbSn and SnBi samples were mainly CoSn2 and CoSn3, whereas that in SAC

sample were mixture of CoSn3 and (Co,Cu)Sn3. As to solders/-Co(W,P) samples

subjected to solid-state aging, IMCs resided on the P-rich layer without spallation.

In the samples containing poly-Co(W,P), thick IMC neighboring to an amorphous W-rich layer was seen regardless of the solder and aging types. It was found that the amorphous W-rich layers could not inhibit subsequent alloy reactions. Hence, diffusion barrier capability should be correlated to the nature of chemical bonds, rather than the

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amorphism of microstructure. Moreover, -Co(W,P) was a composite-type barrier, i.e., sacrificial- plus stuffed-type barrier, while poly-Co(W,P) is mainly a sacrificial-type barrier. Analytical results indicated that the P content in Co(W,P) is a crucial factor affecting the structural evolution at the solder/electroless Co(W,P) interface.

The values of Ea’s for IMC growth in PbSn/-Co(W,P) and PbSn/poly-Co(W,P)

samples were separately equal to 338.6 and 167.5 kJ/mol, whereas the Ea’s of IMC growth

were 110.7 and 81.8 kJ/mol for SAC/-Co(W,P) and SAC/poly-Co(W,P) samples, respectively.

Ball shear test revealed the ductile mode dominates the failure in PbSn/-Co(W,P), PbSn/poly-Co(W,P) and SAC/poly-Co(W,P) samples in most aging conditions, whereas interfacial break dominates at short-time aged samples and pad lift dominates when aging time was long in SAC/-Co(W,P) case. Analytical results indicated that the decrement of bonding strength due to pad lift failure was ascribed to the deterioration of adhesion due to high P content, loss of toughness due to the formation of Co2P precipitates and the thermal

stress induced by the change of CTE due to the recrystallization in aged Co(W,P) layer although high P content might enhance barrier capability. The P content of electroless plating layer affects not only the alloy reactions at solder/Co(W,P) interface, but also the diffusion barrier characteristics and reliability of solder joints.

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Figure Captions

Figure 2-1. The contributions to RC delay from interconnect and gate in Al-

and Cu-ICs [13]. ... 4

Figure 2-2. Single and dual damascene processes [17]. ... 6

Figure 2-3. The first three levels of electronics packaging [1]. ... 9

Figure 2-4. C4 technology proposed by IBM [1]. ... 9

Figure 2-5. Schematic illustrations of (a) WB, (b) TAB, and (c) FC bonding [27]. ... 10

Figure 2-6. Typical process flow of FC bonding [1]. ... 12

Figure 2-7. Solder bump structure [28]. ... 13

Figure 2-8. Classification of diffusion barrier layers: (a) sacrificial-type, (b) stuffed-type, (c) passive-type, and (d) amorphous-type diffusion barrier layers [29]. ... 15

Figure 2-9. Illustrations of the structures of diffusion barrier layers [31]. ... 17

Figure 2-10. Cu-Sn binary phase diagram [39]. ... 19

Figure 2-11. Ni-Sn binary phase diagram [39]. ... 23

Figure 2-12. Cross-sectional SEM view of PbSn/Ni(P) sample subjected to 220ºC annealing for 30 sec [79]. ... 25

Figure 2-13. (a) TEM view of SAC/Ni(P) interface after reaction. (b) TEM view of the IMC and P-rich region and the diffraction pattern taken from the NiSnP layer [63]... 27

Figure 2-14. Co-Sn binary phase diagram [88]. ... 29

Figure 2-15. Co-P binary phase diagram [94]. ... 31

Figure 2-16. Co-W binary phase diagram [94]. ... 32

Figure 3-1. Structure of samples prepared in this study. ... 42 Figure 4-1. Cross-sectional SEM micrographs of PbSn/α-Co(W,P) samples

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subjected to liquid-state aging at 250C for (a) 1 min, (b) 20 min, (c) 30 min, (d) 1 hr, (e) 3 hrs and (f) 5 hrs. (SEI mode; accelerating voltage = 10 kV) ... 53 Figure 4-2. Cross-sectional SEM micrograph of PbSn/α-Co(W,P) sample

subjected to 250C/30-min liquid-state aging followed by 150C/200-hr solid-state aging. (SEI mode; accelerating voltage = 15 kV) ... 54 Figure 4-3. (a) Cross-sectional SEM micrograph of PbSn/poly-Co(W,P) sample

subjected to 250C /1-hr liquid-state aging and (b) corresponding EDS line scanning profiles. (SEI mode; accelerating voltage = 15 kV). (c) XTEM micrograph of the PbSn/poly-Co(W,P) sample subjected to 250C/1-hr liquid-state aging. The dotted circle denotes the area where the selected area electron diffraction (SAED) pattern was taken. (d) TEM/EDS spectrum of CoSn3 in (c). (e) TEM/EDS spectrum of

W-rich layer in (c). ... 57 Figure 4-4. (a) Cross-sectional SEM micrograph of PbSn/poly-Co(W,P) sample

subjected to 150C/1000-hr solid-state aging and (b) corresponding EDS line scanning profiles. (SEI mode, accelerating voltage = 15 kV) .... 59 Figure 4-5. (a) XTEM micrograph of PbSn/poly-Co(W,P) sample subjected to

150ºC/1000-hr solid-state aging. (b) Enlarged picture of W-rich layer and corresponding SAED pattern. ... 60 Figure 4-6. Consumption of Co(W,P) layer as a function of square root of aging

time in the samples containing various electroless Co(W,P) layers. ... 61 Figure 4-7. (a) IMC thickness against the square root of aging time for various

PbSn/Co samples subjected to solid-state aging at 130-170°C up to 500 hrs. (b) Plots of lnK versus 1/T for the determination of the values

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of Ea for IMC growth. ... 63

Figure 4-8. Shear stresses of PbSn/α-Co(W,P) and PbSn/poly-Co(W,P) samples subjected to liquid-stage aging for various times. ... 65 Figure 4-9. Summary of failure modes for (a) PbSn/α-Co(W,P) samples and (b)

PbSn/poly-Co(W,P) samples... 66 Figure 4-10. (a) Ductile failure in a PbSn/poly-Co(W,P) sample, (b)

interfacial break in an as-reflow PbSn/poly-Co(W,P) sample, (c) ductile failure in PbSn/α-Co(W,P) sample subjected to 20-min aging and (d) pad lift in a PbSn/α-Co(W,P) sample subjected to 30-min aging. The arrow in each micrograph indicates the shear direction. (SEI mode; accelerating voltage = 15 kV) ... 67 Figure 4-11. SEM micrographs of SnBi/α-Co(W,P) samples subjected to

liquid-state aging for (a) 1 min, (b) 20 min, (c) 30 min and (d) 1 hr. (e) SEM/EDS spectrum of IMC, and (f) SEM/EDS spectrum of P-rich layer. (g) EDS line scan profiles corresponding to the sample shown in (d). (BEI mode; accelerating voltage = 15 kV) ... 72 Figure 4-12. Cross-sectional SEM images of SnBi/α-Co(W,P) sample subjected to

liquid-state aging for (a) 2 hrs and (b) 5 hrs. (c) Plot of thicknesses of the P-rich layer and the consumed Co(W,P) film versus square root of aging time. (BEI mode; accelerating voltage = 15 kV) ... 74 Figure 4-13. XTEM image of SnBi/α-Co(W,P) subjected to liquid-state aging for

1 hr. SAED patterns taken from P-rich layer and unreacted Co(W,P) (indicated by broken circles) are attached at right-hand side of micrograph. ... 75 Figure 4-14. (a) Cross-sectional SEM micrograph of SnBi/α-Co(W,P) sample

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EDS line scan profiles. (BEI mode; accelerating voltage = 15 kV) ... 77 Figure 4-15. XTEM images taken from (a) reaction interface and (b) unreacted

Co(W,P) in SnBi/α-Co(W,P) sample subjected to solid-state aging for 1000 hrs. The regions subjected by SAED analysis were indicated by broken circles. ... 78 Figure 4-16. (a) Cross-sectional SEM images of SnBi/poly-Co(W,P) samples

subjected to liquid-state aging for (a) 1 hr, (b) 2 hrs and (c) 5 hrs. (d) EDS line scan profiles corresponding to the sample subjected to 1-hr liquid-state aging. (BEI mode; accelerating voltage = 15 kV) ... 79 Figure 4-17. Plot of consumption of Co(W,P) layer and W-rich layer thickness

versus square root of aging time in SnBi/poly-Co(W,P) samples subjected to liquid-state aging. ... 80 Figure 4-18. XTEM micrograph of reaction layer in SnBi/poly-Co(W,P) subjected

to liquid-state aging for 1 hr. Attached SAED pattern was taken from the region in vicinity of reaction layer. ... 83 Figure 4-19. (a) Cross-sectional SEM image of SnBi/poly-Co(W,P) subjected to

solid-state aging for 1000 hrs and (b) the corresponding EDS line scan profiles. (BEI mode; accelerating voltage = 15 kV) ... 84 Figure 4-20. Thickness consumption of (a) α-Co(W,P) and EN and (b)

poly-Co(W,P) and EN versus the square root of time. ... 85 Figure 4-21. Variation of IMC thickness with the square root of time for (a)

α-Co(W,P) and EN and (b) poly-Co(W,P) and EN. ... 86 Figure 4-22. Cross-sectional SEM micrographs of (a) as-reflowed SAC/α-Co(W,P)

sample and those subjected to liquid-state aging at 250°C for (b) 20 min, (c) 1 hr, (d) 3 hrs and (e) 5 hrs. EDS line scan profiles corresponding to (c) is shown in (f). (SEI mode; accelerating voltage

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= 15 kV) ... 89 Figure 4-23. EDS spectra of (a) Ag3Sn in Fig. 4-22 (a) and (b) the spalled IMCs in

Fig. 4-22 (b). ... 89 Figure 4-24. A plot of P-rich layer thickness as a function of the square root of

aging time for SAC/α-Co(W,P) samples subjected to liquid-state aging test at 250°C. ... 91 Figure 4-25. XTEM micrograph of SAC/α-Co(W,P) sample subjected to 1-hr

liquid-state aging. ... 92 Figure 4-26. (a) SEM image (SEI mode; accelerating voltage = 15 kV), (b) EDS

line scan profiles and (c) XTEM micrograph of SAC/-Co(W,P) sample subjected to solid-state aging at 150°C for 1000 hrs. ... 94 Figure 4-27. (a) SEM image (SEI mode; accelerating voltage = 15 kV), (b) EDS

line scan profiles. (c) XTEM micrograph, and (d) TEM/EDS spectrum of SAC/poly-Co(W,P) sample subjected to liquid-state aging at 250°C for 1 hr. ... 96 Figure 4-28. A plot of IMC thickness against the square root of aging time for

SAC/poly-Co(W,P) samples subjected to liquid-state aging at 250°C. ... 97 Figure 4-29. (a) SEM image (SEI mode; accelerating voltage = 15 kV), (b) EDS

line scan profiles and (c) XTEM micrograph of SAC/poly-Co(W,P) sample subjected to solid-state aging at 150°C for 1000 hrs. ... 99 Figure 4-30. (a) IMC thickness against the square root of time for various

SAC/Co samples subjected to solid-state aging at 130-170°C up to 500 hrs. (b) Plots of lnK versus 1/T for the determination of the values of Ea for IMC growth. ... 101

Figure 4-31 Shear strengths of SAC/Co(W,P) samples as a function of liquid-stage aging time. The results obtained by the studies

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[112,130,131] regarding of Ni barrier layers are also added for comparison. ... 103 Figure 4-32. Summary of failure modes of (a) SAC/α-Co(W,P) and (b)

SAC/poly-Co(W,P) samples in terms of the SEM observations on facture surfaces and JESD22-B117A Standard [93]. ... 105 Figure 4-33. Fracture surfaces of (a) as-reflow SAC/poly-Co(W,P) sample, (b)

SAC/poly-Co(W,P) sample subjected to 20-min aging, (c) SAC/-Co(W,P) sample subjected to 20-min aging and (d) crack of Co(W,P) layer in SAC/-Co(W,P) sample subjected to 30-min aging. The arrow in each micrograph indicates the shear direction. .. 106

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Table Captions

Table 3-1. Chemicals and processing conditions of pretreatment. ... 43 Table 3-2. Chemicals and processing conditions of electroless Co(W,P) plating. ... 44 Table 3-3. High-temperature storage test conditions [106]. ... 46

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Chapter 1 Introduction

With the progress of scale-down of electronic products, the peripheral-array

interconnection technologies such as wire bonding (WB) and tape automated bonding

(TAB) were gradually replaced by the area-array technologies such as the flip-chip

(FC) bonding in first level package. The advantages of FC bonding include high

packaging efficiency, good electrical performance, high input/output (I/O) counts and

compactness of electronic products. The FC bonding connects the integrated circuit

(IC) chip and substrate with the bump joints which can be built up by solders, metallic

posts, conductive polymer, anisotropic conductive adhesives, polymeric composites,

pressure contact, etc [1]. Among these, solder alloys are the most common materials

for the body of bump joint. However, the usage of solders require the under bump

metallurgy (UBM) to prevent the interdiffusion in between solder and IC bond pad so

as to ensure a reliable operation of electronic devices. UBM is a multi-layered

thin-film structure comprised of the adhesion layer, diffusion barrier layer and

passivation layer. Diffusion barrier layer is the most important component of UBM

and refractory metal layers such as tungsten (W), molybdenum (Mo) and their alloys

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and sputtering are commonly adopted as the diffusion barrier layers of UBM.

Recently, electroless plating technology, e.g. electroless nickel (EN), becomes a

competitive diffusion barrier materials for the advantages of low cost, high throughput,

good step coverage, etc. In addition, it was found that the stress status in EN is

comparatively lower than that in the sputtered Ni [2] and the amorphous feature in EN

provides no grain boundary for short-circuit diffusion and satisfactory barrier

properties [3-6].

On the other hand, suppression of RC delay and electromigration (EM) are

important issues in the trend of IC scale-down. As a result, new low-k dielectric

materials (for low capacitance) and copper (Cu) (for low resistance) are separately

brought in to replace traditional SiO2 interlayer dielectric (ILD) and aluminum (Al)

interconnects. However, Cu is a rather active element that its diffusivity in Si is as

high as 104 to 105 cm2/sec. A diffusion barrier layer must be inserted in between Cu

interconnects and Si to avoid the degradations caused by interdiffusion. Similarly, an

effective diffusion barrier layer must be implanted in the UBM when FC bonding is

applied to Cu-ICs.

Electroless cobalt-phosphorus (Co(P)) may serve as the diffusion barrier material

for Cu metallization and a superior barrier capability to inhibit the interdiffusion

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barrier layer of Cu and PbSn solder was also demonstrated [8]. Previous studies [9-11]

reported the enhancement of thermal stability and diffusion barrier capability to Cu

metallization by adding the tungsten (W) element in electroless Co(P). In addition, it

has been illustrated that the amorphous electroless Co(W,P) is a mixed-type barrier,

i.e., a combination of sacrificial- and stuffed-type barrier, to PbSn solder and Cu [12].

Since electroless Co(W,P) exhibited a promising capability as a diffusion barrier, a

further study is hence required in order to realize its applications as the diffusion

barrier to present solder types.

This thesis studies the barrier characteristics of electroless Co(W,P) to solders

including eutectic PbSn, SnBi and SnAgCu (SAC). Both amorphous and

polycrystalline Co(W,P) layers were prepared, the alloy reactions and morphology

evolution at the reacting interfaces in the samples subjected to liquid-state aging at

250C and solid-state aging at 120 to 150C were investigated so as to deduce the

diffusion barrier characteristics of Co(W,P) to solders. The activation energy of IMC

growth (Ea) and the bonding strength of Co(W,P)/PbSn and Co(W,P)/SAC systems

were also evaluated so as to gain an in-depth understanding on the applicability of

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Chapter 2 Literature Review

2.1. Trends of IC Interconnection Technologies

In recent years, the very large scale integrated circuit (VLSI)/ultra large scale

integrated circuit (ULSI) technology has profoundly advanced. With the continuous

scale-down of VLSI/ULSI, multi-layer interconnect structure becomes an important

Figure 2-1. The contributions to RC delay from interconnect and gate in Al- and

Cu-ICs [13].

issue in IC design. Though the IC scale-down effectively reduces the gate delay, it

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conventional ICs within Al as the conducting line and SiO2 as the ILD as illustrated in

Fig. 2-1. The shrinkage of conducting line width also escalates the current density and

consequently leads to the electromigration (EM) failure, resulting in the reliability

concerns of electronic products. In order to overcome the difficulties caused by IC

scale-down, new low-k dielectric material (for low capacitance) and Cu (for low

resistance) are hence brought in present IC manufacture to replace traditional SiO2

ILD and Al interconnects.

2.1.1. Cu Metallization

Cu metallization is a key breakthrough in contemporary IC manufacture when

IBM announced the Cu-IC technology in early years of 90 [14-16]. The Cu

metallization is also termed as the damascene technology (see illustration in Fig. 2-2

[17]) which is accomplished by a series of processes including photolithography to

define the via position, PVD or electroless plating to fill the Cu in via holes, and

chemical mechanical polishing (CMP) to polish off the unnecessary Cu. The

advantages of Cu metallization for Si ICs include low resistivity and high EM

resistance. In addition, the higher melting point and better mechanical property of Cu

than those of Al lead to a higher sustainable current density, a lower failure rate of

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of Cu metallization and the solutions are listed as below:

Figure 2-2. Single and dual damascene processes [17].

(1) High surface corrosion: Cu oxidizes rapidly at high temperature in air. Unlike the

protective oxide formed on Al alloys to improve the corrosion resistance, Cu

oxidizes even in relatively high vacuum with the slightest amount of water vapor.

Hence, there are methods for preventing Cu from oxidization, e.g., surface

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copper alloying (adding a small amount of magnesium (Mg), Al, or boron (B)

[19-22] in Cu), etc.

(2) Chemical etching method: Cu is extremely difficult to be etched. When dry

etching a specific pattern, the by-products are hard to evaporate away because of

the lower vapor pressure of Cu halogenide. As illustrated in Fig. 2-2, dual

damascene in conjunction with the CMP technology is used to overcome this

manufacture difficulty [23-24].

(3) Poor adhesion: The adhesion between Cu and ILD is poor so that an adhesion

layer has to be added to improve the adhesion strength.

(4) High diffusion rate: Cu diffuses into SiO2 and Si in a relatively fast rate (the

diffusivity of Cu in Si is about 104 to105 cm2/sec) and results in device failures.

For instance, Cu might induce stacking faults in SiO2, leading to the high leakage

current and low breakdown voltage in ILD. The Cu impurity in Si generates the

deep defect levels in the bandgap of Si which, consequently, becomes the

recombination centers to trap the electrons and decreases the life time of electrons

in conduction band [25]. The life time decrement of charge carriers will prolong

(25)

2.2. Introduction to Electronic Packaging

The IC chips are rarely used in bare form; they have to be “packaged” for

subsequent shipping/handling processes so that they can be assembled with other

active/passive components to accomplish a specific operational function. Electronic

packaging starts from the interconnection and encapsulation of monolithic IC chips,

subsystem/system assembly to product finish as illustrated in Fig. 2-3 [1]. It provides

four basic functions, i.e., power distribution, signal propagation, heat dissipation, and

mechanical support/protection. In the trend of device scale-down, packaging

technology becomes a bottleneck for further upgrading the performance of electronic

products. In recent years, many new packaging concepts, e.g., ball grid array (BGA),

chip scale package (CSP), direct chip attach (DCA), wafer-level packaging (WLP),

etc., have been introduced in order to overcome the limitations resulted from

traditional technologies. As to the interconnect technology, FC bonding resumes its

active role in the market even though it is in fact an old concept originated from the

controlled collapse chip connection (C4 or C4) for solid logic technology (SLT)

proposed by IBM in early 1960s [26] as shown in Fig. 2-4 [1]. The trend of

performance upgrading, miniaturization and versatile functionality has driven FC

bonding as a popular interconnect method for advanced electronic products. Presently,

(26)

bonding and its market share is expected to grow drastically in near future.

Figure 2-3. The first three levels of electronics packaging [1].

Figure 2-4. C4 technology proposed by IBM [1].

(27)

There are three main interconnect technologies for first level packaging, i.e., WB,

TAB, and FC bonding as described in Fig. 2-5 [27]. Both WB and TAB are

peripheral-type interconnection technologies so that they have limited I/O counts and

packaging efficiencies. On the contrary, FC bonding is area-type interconnect method

which allows a comparatively high I/O counts (> 104) and packaging efficiency (>

90%). Presently, WB dominates the market due to its technical simplicity and

maturity whereas the application of TAB is limited to some specific products, for

instance, the packaging of driver IC for liquid-crystal display (LCD). In comparison

with WB, FC bonding is in fact a relatively complicated and expensive interconnect

method so that in early years its utilization was only seen in some sophisticated

electronic products such as supercomputers and work stations.

(28)

Since the announcement by IBM in early 1960s, FC bonding has been

recognized as an interconnect technology which bonds the IC chips in face-down

manner on substrate by using a specific conducting material or interconnect concept.

In typical FC bonding flow, die bumping and substrate metallization are separately

accomplished and then the bumped die is attached to the substrate via appropriate

thermal treatment. In most cases, polymeric resin will be injected into the gap in

between the die and substrate after the completion of bonding. It forms the adhesive

bonds so as to alleviate the thermal stress induced by the difference of thermal

expansion coefficients (CTEs) of die and substrate. The bumps are not only the

power/signal conducting paths in between the chip to substrate, but also the heat

dissipation paths and mechanical support of the packaging structure. The FC

manufacturing process flow is illustrated in Fig. 2-6 [1].

2.2.2. Structure of Solder Bump Joints

As stated previously, the bumps for FC bonding can be accomplished by various

materials and fabrication processes. PbSn solders are the most common material for

bump body. IBM used the high-temperature solder containing 97 wt.% of Pb for C4

technology whereas eutectic PbSn is the most common solder type compatible with

(29)

formulations have been developed and, with the call for environmental protection,

Pb-free solders are flourishing in recent years. Though still not a complete drop-in

solution for conventional PbSn solder, SnAg, SnCu, SnBi, and SnZn are promising

Pb-free solders. The SnAg alloy doped with a moderate amount of Cu, SnAgCu

(SAC), is well recognized for bumping fabrication due to its suitable physical and

mechanical properties.

Figure 2-6. Typical process flow of FC bonding [1].

(30)

it comprises of the adhesion layer, diffusion barrier layer and passivation layer

commonly prepared by PVD methods. The functions of each layer in UBM are

described as follows.

Figure 2-7. Solder bump structure [28].

(1) Adhesion layer is to ensure reliable adhesive strength in between IC bond pad

and subsequent metal layer. Materials such as titanium (Ti), chromium (Cr), and

tantalum (Ta) are common adhesion layers.

(2) Diffusion barrier layer is to impede the interdiffusion in between IC bond pad and

bump body materials. Such a barrier layer plays a key role in maintaining the

integrity of bump joint and the most common materials are refractory metals such

as W, Mo and their alloys. In addition, EN layer is also a popular material for

barrier purpose in presented days.

(3) Passivation layer is also called the protective or anti-oxidation layer. In some cases,

a wetting layer is added in between the passivation layer and underlying diffusion

Chip IC Adhesion layer Protective layer Diffusion barrier Glass Pb Sn Solder As-deposited PbSn layer

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barrier layer to ensure good wettability of solder when the bump joints are

formed. Cu is the common wetting layer material whereas noble metals such as

gold (Au) and palladium (Pd) are frequently adopted as the passivation layer.

2.2.3. Classifications of Diffusion Barrier Layers

As mentioned above, a diffusion barrier layers impede the interdiffusion in

between the IC bond pad and bump body materials. It is possible to have the diffusion

barrier layer chemically inert to the bond pad materials; nevertheless, this means that

there is no alloy reaction in between these two layers and, hence, their bonding

strength would be too poor to form the sustainable bump joint. In practice, alloy

reactions are expected to occur in between the barrier layer and bond pad material,

however, the extent of reactions must be minimized to avoid a dramatic alternation on

structural integrity. The performance of diffusion barrier layer is hence correlated to

its sustenance to various annealing environments. An ideal diffusion barrier layer for

UBM applications must be thermodynamically stable, low contact resistance, high

adhesion property, high tolerance to thermal and mechanical stresses, and high

electrical conductivity.

According to N.A. Nicolet [29], diffusion barrier layers can be divided into four

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barrier, stuffed-type barrier, passive-type barrier and amorphous-type barrier. The

features of each kind of diffusion barrier layer are briefly described as follows.

Figure 2-8. Classification of diffusion barrier layers: (a) sacrificial-type, (b)

stuffed-type, (c) passive-type, and (d) amorphous-type diffusion barrier

layers [29].

(1) Sacrificial-type barrier layer reacts with the bump body material until it is totally

exhausted as illustrated in Fig. 2-8(a).

(2) Stuffed-type barrier layer prevents the diffusion by forming obstacles in

fast-diffusion paths such as grain boundaries. Insertion of impurity atoms or

formation of precipitates in grain boundaries is a common method to induce the

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(3) Passive-type barrier layer prevents the alloy reactions in between the diffusion

barrier layer and bond pad material by inserting a material which is

thermodynamically stable and chemically inert to the bump body and bond pad

materials as illustrated in Fig. 2-8(c).

(4) Amorphous-type barrier layer eliminates the grain boundary diffusion since such

fast diffusion paths are absent due to the structure irregularity as illustrated in Fig.

2-8(d). Surely grain boundaries are also absent in single crystalline materials,

however, single crystalline diffusion barriers are impractical since their

preparation is relatively complicated. An amorphous substance with high

recrystallization temperature may serve as the amorphous-type barrier.

Except for the material characteristics of diffusion barrier itself, the

manufacturing process affects the diffusion barrier capability as well. The common

diffusion barriers for Cu metallization are Ta, TaN, TiN, etc. However, the step

coverage property of above thin films made by PVD is poor. Recently, EN, electroless

Co(P) and Co(W,P) layers are benefit on good step coverage, uniform film quality,

selective deposition [30], low-temperature process, lower resistivity than other

refractory materials and lower manufacturing cost so that they are popular barrier

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Taking the crystal structure into consideration, the diffusion barrier layers were

also classified as single crystal, void-columnar poly-crystal, equiaxed columnar

poly-crystal, nanocrystalline and amorphous barriers as illustrated in Fig. 2-9 [31].

Figure 2-9. Illustrations of the structures of diffusion barrier layers [31].

It is well-known that grain boundaries are the fast diffusion paths, hence, the

equiaxed columnar poly-crystal could hardly provide the satisfied diffusion barrier

capability whereas the single-crystal and amorphous layer do. It is difficult to grow

single crystal layer, but it is rather easier to obtain an amorphous film by PVD or

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prepare thin films, it is not under a thermodynamic equilibrium state so that

amorphous structure is easy to form.

2.3. Reactions between Solder and Underlying Metals

It is well-known that alloy reactions occur when solder contacts with conductor

metals (i.e. UBM, boards surface finishes, etc) directly during soldering. Intermetallic

compounds (IMCs) will form and grow at the reacting interfaces, providing a good

metallurgical bonding. However, excessive IMCs might affect the mechanical

reliability of the joints for the inherent brittle feature and the tendency to generate

structural defects such as Kirkendall voids. Hence, the materials selected as diffusion

barrier should have lower reaction rate when soldering [32-38]. In principle, the IMC

layers are formed in three consecutive stages: the dissolution of contact metal into the

molten solder until solder is supersaturated with the dissolved metal throughout the

interface, chemical reactions and solidification of IMCs [38]. During storage or in-use

of the assemblies, the initial formed IMCs during soldering grow thicker or increase

in number. Therefore, both solid/liquid and solid/solid systems must be studied to as

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2.3.1. Reactions of Solders with Cu-based Metals

For Cu-based conductor metal reacting with Sn-based solder, IMCs such as

Cu3Sn (ε) and Cu6Sn5 (η) phases could form as indicated by the Cu-Sn binary phase

diagram in Fig. 2-10 [39]. The Cu6Sn5 has two types of phases. The η’ phase, the

ordered long-period superlattice (LPS) based on the NiAs-type structure, is stable at

room temperature [40-42]. Another phase type is the high-temperature η phase, also

possessing NiAs structure. The equilibrium transformation temperature of η into η’

phase is 186C. During soldering and subsequent cooling, the time for the

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transformation from η into η’ is in general not sufficient so that the η remains as the

metastable phase [39] and the differential scanning calorimeter (DSC) measurements

found that the transformation starts after 6-min thermal annealing at 175C [43]. As to

the ε phase, it was also reported possessing a long-period superstructure [43], but the

ordering temperature is not as well defined as that of the η-phase. When Cu reacts

with molten Sn, it dissolves rapidly and locally supersaturated in the vicinity of

interface. At the metastable composition regions, Cu6Sn5 precipitates vary fast by the

heterogeneous nucleation and growth at the Cu/liquid solder interface [38]. The

thickness and the morphology of the IMCs is firstly determined by the Cu dissolution

rate in liquid and the chemical reaction between Sn and Cu, and secondarily, by the

diffusion of Cu into the liquid [38]. Notably, each of the Cu6Sn5 crystallites grows

independently from the adjacent ones, and the roughness of interface was found to

have an effect on the formation of the Cu6Sn5 crystallites. The rougher the surface is,

the more crystallites will form per unit area [44]. Afterward, the IMC growth rate

gradually slows down for the decrease of the dissolution of Cu to the molten Sn when

IMCs formed. After extending the contact times, a thinner Cu3Sn layer forms between

Cu and Cu6Sn5 layer. The formation mechanism of the Cu3Sn phase is diffusion and

reaction type growth, in contrast to the mainly dissolution and reaction controlled

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main diffusion species rather than Cu [45-47]. The grain boundary and interstitial

diffusion mechanisms dominate over vacancy-mediated diffusion at relatively low

temperatures with respect to the melting points of the corresponding materials (with

metals 0.3-0.5Tm) [38,48-49]. In addition, the activation energy (Ea) for the

interdiffusion in Cu3Sn phase appears to be higher than that of Cu6Sn5 phase [46,50].

Therefore, the growth rate of the Cu3Sn layer should require somewhat higher

temperatures than the growth of the Cu6Sn5 layer. Cu3Sn phase is reported to grow at

the expense of the Cu6Sn5 phase and mainly consists of the columnar grains parallel to

the diffusion direction, indicating either grain boundary diffusion is controlling the

phase formation or that there is strong anisotropy in the growth of the Cu3Sn phase in

solid-state aging [51].

2.3.2. Reactions of Solders with Ni-based Metals

Owing to the high reaction rate of Cu and molten Sn, Ni is often used as a

diffusion barrier layer in between Cu and Sn to obtain a thinner IMC layers in the

Sn-Ni system. It has been reported that there are three IMCs stable below 260C, i.e.,

Ni3Sn, Ni3Sn2, and Ni3Sn4 phases as shown by the Ni-Sn binary phase diagram in Fig.

(39)

high-temperature cubic form) [39]. Ni3Sn2, has more than one structures. As indicated

by the Ni-Sn binary phase diagram [39], Ni3Sn2 has a hexagonal closed-packed Ni-As

structure at low temperatures (LT) and a hexagonal or orthorhombic symmetry at high

temperatures (HT). Other researches described a hexagonal structure with partially

filled InNi2 structure for the Ni3Sn2 HT-phase [52-58], whereas the Ni3Sn2 LT-phase

has one orthorhombic structure [54] or three different LT-phases two of which have

incommensurate structure [52,56-58]. The transition temperature has been identified

as 600C [39], 477C [56] or 517C [58] or in a range of 295C to 508C [52]. Ni3Sn4

possesses only the monoclinic structure [39]. During soldering, Ni3Sn4 phase, rather

than the Ni3Sn or Ni3Sn2, forms at interface, even though Ni3Sn4 is the least

thermodynamically stable compound and it possesses the most complicated structure

among all Ni-Sn IMCs [38-39]. The reaction starts by the dissolution of Ni to molten

Sn, with subsequent diffusion of Ni inside the liquid and chemical reactions to form

Ni3Sn4. The dissolution of Ni is essentially stopped after the formation of the Ni3Sn4,

and further growth of Ni3Sn4 occurs by diffusion of Sn through the IMC layer when

Ni3Sn4 continuously forms at the interface [38]. Bader et al. [59] reported that Ni3Sn4

has three different morphologies simultaneously when Ni/molten Sn reaction starts: a

fine-grained and planar layer at the Ni interface, long, thin, idiomorphic whiskers, and

(40)

and transform to the large crystals, and the Ni3Sn is the latest phase to form. Bader et

al. [59] also pointed out that grain boundary diffusion of Ni dominates the phase

growth at 240-300C. As to the case solid Ni reacts with solid Sn, the growth rates of

the stable Ni-Sn IMCs are quite slow and out of them only Ni3Sn4 can be detected

[38,51,60], and the growth kinetics of the Ni3Sn4 phase appears to be parabolic and

thus diffusion controlled [51]. Oh [51] found that Sn is the only diffusing species

during the formation of Ni3Sn4, and the plausible reasons for the absence of Ni3Sn and

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Ni3Sn2 phases are difficult nucleation and/or slow diffusion behavior in the missing

phases. Only the micro-scale roughness promotes the nucleation of Ni3Sn and Ni3Sn2

at temperatures as low as 100C. However, Haimovich [60] pointed out the existence

of platelet morphology of the metastable NiSn3 compound and found that Pb

effectively decreases the growth of the metastable phase when annealing in the

temperature range of 75-232C.

Notably, when using PbSn solder or pure Sn to react with Ni, the Ni3Sn4 phase is

the first phase to form at the Sn/Ni interface. However, when using Pb-free solders

that include even small amounts of Cu, the first phase to form is (Cu,Ni)6Sn5

[38,61-63]. Some Cu atoms in the Cu sublattice of the metastable (Cu,Ni)6Sn5 can be

replaced by Ni [63]. This is owing to the fact that the dissolution of Ni to molten

solder is much faster than the diffusion of Cu or Sn into solid Ni.

2.3.3. Electroless Ni(P) Applied on Conductor Metals

Electroless plating is promising for FC application due to its lower reaction rate

and lower cost of the bumping process, hence, there are numerous researches on the

reactions between EN UBM and solders in recent years [63-76]. There are about 7-9

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used as the reducing agent during electroless plating. During aging, Ni reacts with

solder to form Ni3Sn4 IMCs [77], hence, the deposition layer should be thick enough,

generally about 5-6 m in thickness [78], to retard the further diffusion. Consequently,

the EN layer is enriched by P and formation of P-rich region or a Ni3P layer with

columnar grain structure [69,79]. It is reported that Ni3P grows by the grain-boundary

diffusion of Ni atoms or an interstitial diffusion of the P through the Ni3P layer [69],

and the Ni3P layer embrittles the joint and results in the mechanical failures. Some

researches pointed out that the Ni3P layer is caused by the solder assisted

crystallization of the amorphous EN layer [70,79-80] as shown in Fig. 2-12 [79].

Figure 2-12. Cross-sectional SEM view of PbSn/Ni(P) sample subjected to 220ºC

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Liu et al. [70] reported that the P-rich region was the mix of Ni3P and Ni after

reflow (15 min at 130-160C followed by 5 min at 215C) using as-deposited,

approximately 12.5 at.% (about 6.5 wt.%) P, and amorphous or nano-crystalline EN

film. The mixture of Ni3P and Ni indicates that the Ni(P) layer has partially

crystallized, and the unreacted EN remains amorphous or nanocrystalline. The

solubility of P in crystalline EN was much smaller than that in the amorphous phase

so that the extra P was rejected from the crystallized layer, followed by reaction with

available Ni to form Ni3P. This phenomenon is the so-called solder assisted

crystallization. After the aging at 170C for 15 days, Ni3P-plus-Ni layer transformed

to Ni3P because of the more P diffusion in Ni3P-plus-Ni layer, and Ni3Sn4 layer grew

considerably in thickness (from 0.7 to 4 mm). However, when the aging was extended

to 30 days, complex structures consisting of Ni3Sn4, Ni3Sn2, Ni12P5, and Ni12P5 plus

Ni3P appeared, and the Ni(P) layer was fully consumed. The formation of Ni3Sn2 and

Ni12P5 was attributed to Sn diffusion through the Ni3Sn4 layer and following reaction

with Ni3P. Matsuki et al. [71] reported four distinct IMCs, i.e., Ni3Sn4, orthorhombic

Ni48Sn52 (also been previously proposed by Bhargava and Schubert [74]), Ni2SnP, and

Ni-P can be seen after the reflow using EN containing 14 at.% P. Vuorinen et al. [63]

studied the interfacial reactions between SAC solder and amorphous (16 at.% P)

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Ni3P layer between the EN and Ni55Sn35P10 and (Cu,Ni)6Sn5 IMCs formed at the

interface, which was observed by transmission electron microscopy (TEM).

Figure 2-13. (a) TEM view of SAC/Ni(P) interface after reaction. (b) TEM view of the

IMC and P-rich region and the diffraction pattern taken from the NiSnP

layer [63].

In addition, the diffraction pattern taken from the NiSnP layer showed that it is

not amorphous but nano-crystalline (see Fig. 2-13(b)). Vuorinen et al. [63] further

reported that when P is high enough, Ni3P seemed to be suppressed by NiSnP layer.

(a)

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This phenomenon is resulted from the formation of a new liquid (L2) consisting of

supersaturated P in between solid Ni(P) and the bulk liquid solder (L1) [38,63] due to

the presence of metastable liquid miscibility gap in the Sn-P system [39]. During

cooling, the nanocrystalline NiSnP layer solidified and transformed into more stable

crystalline compound Ni3P with columnar structure gradually. Other researchers

[81-83] proposed that the NiSnP layer should result from the Sn diffusion into Ni3P

layer and cause the IMCs spallation.

It has been mentioned that when Ni-based conduct metal reacts with molten

solder, Ni3Sn4 IMCs form at the interface, however, when solders contain Cu,

(Cu,Ni)6Sn5 would form at the interface [38,61-63]. (Ni,Cu)3Sn4 and (Ni,Cu)3Sn2

IMCs were reported as well [75,81-84]. The formation mechanism of the complex

reaction layer structure requires further investigation.

2.3.4. The IMC Phase Types in Co-Sn Phase Diagram

It is essential to understand the IMC types formed by the reactions of Co and Sn

in order to realize the applications of electroless Co-based thin films as the diffusion

barrier layers in UBM [3,8,12,31,85-87]. As illustrated by the Co-Sn binary phase

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may stably exist at temperature below 260C. TheCo3Sn2 has two modifications

below 500C: the Co3Sn2 HT-phase () with hexagonal NiAs structure and the Co3Sn2

LT-phase () with orthorhombic Ni3Sn2 structure which is stable. Calculation of Jiang

et al. indicated that the order-disorder transition of -Co3Sn2 and -Co3Sn2 phases

occur at 563 to 568C [89]. As to the CoSn, it possesses the hexagonal structure and is

stable up to the peritectic temperature of 936C. The CoSn2 possesses tetragonal

Al2Cu structure and is stable below 525C. The solid solubility of Co in tetragonal Sn

solid solution is negligible, whereas that of Sn in -Co is about 2 at.% Sn at 1033C

and about 1.67 at.% Sn in -Co at 536C.

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Lang and Jeitschko reported the presence of - and -CoSn3 [88]. The HT -phase

formed via the peritectical reaction of CoSn2 with the Sn-rich melt at 345±2C,

whereas the LT -phase is stable below 275±5C and possesses the PdSn3 structure.

Jiang et al. calculated the formation enthalpy of solid Co-Sn at 298K and found that

the CoSn phase is the most thermodynamically stable IMC [89]. However, CoSn

phase is rarely observed when metallic Co reacts with solders. Zhu et al. pointed out

that CoSn emerges at 873K while CoSn2 forms at 673 and 773K in the Sn/Co

diffusion couples [90]. Zhu et al. also reported the presence of CoSn3 at 573K [91].

Wang and Chen found that CoSn3 is the main product in the Sn/Co couples annealed

at temperatures ranging from 150 to 200ºC and the meta-stable CoSn4 phase forms at

the corner [92,93]. In addition, Sn is the primary diffusion element while Co is

essentially immobile [92].

2.3.5. Electroless Co(P) and Co(W,P) Applied to Conductor Metals

Ferromagnetic behaviors of electroless Co(P) films have been widely studied for

serving as the magnetic recording materials in past years and the Co-P binary phase

diagram is shown in Fig. 2-15 [94]. Chi and Cargill reported the average Co-Co

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pointed out that Co(P) film is mainly amorphous when P contents of electroless Co(P)

film are higher than 12 at.% [96]. Paunovic et al. investigated the feasibility of

electroless Co(P) film, which is amorphous and with low resistance, to diffusion

barrier of Cu metallization [97]. Hono and Laughlin [98] pointed out the solubility of

P in Co is extremely low so that the P atoms would segregate at grain boundaries, thus

providing the stuffed-type barrier capability. O’Sullivan et al [7] reported that the

50-nm thick Co(P) is an effective diffusion barrier to Cu up to 400C. Above studies

also indicated the P contents affects the crystallinity of electroless Co(P) films and the

films transform to nanocrystalline or even to amorphous structure with supersaturated

P content. This enables the stuffed-type diffusion barrier capability to Cu up to 400C

when P elements segregate to the grain boundaries of Co(P).

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Figure 2-16 depicted the Co-W binary phase diagram [94]. The Co-W phase

diagram consists of: (1) the liquidus passes through a maximum at 1505C and 10

at.% W; (2) an eutectic point at 1471C and 21 at.% W; (3) a peritectic horizontal at

1689C, with terminal compositions of 32 and 99.1 at.% W; (4) Co7W6 with

rhombohedral structure forms peritectically at 48.5 at.% W; (5) the face-centered

cubic (FCC) solid solution, -Co, with a maximum solid solubility of 17.5 at.% W; (6)

Co3W with hexagonal Ni3Sn structure forms as a result of the peritectoid reaction at

1093C and 25.3 at.% W; and (7) the solid solution W, with a maximum solid

solubility of 0.9 at.% Co at 1689C. According to Takayama et al., the solubility limit

of W in -Co decreases from 17.5 at.% at 1471C to 0.5 at.% at 750C [99].

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Neumeier et al. found the solubility of Co in W is about 0.9 at.% at the peritectic

temperature and is about 0.7 at.% at 700C [100]. Inspired by previous study about

the thermal enhancements and the increase of corrosion resistance by adding W atom

in Ni(P) thin film, Kohn et al. [9-11] investigated the addition of W in Co(P) thin film

to improve the diffusion barrier capability. After the 400C-annealing for 8 hrs, the

diffusion barrier capabilities of sputtered Co, electroless Co(P) and electroless

Co(W,P) thin films were analyzed by secondary ion mass spectrometer (SIMS) and

the results indicated that the electroless Co(W,P) thin film is the best diffusion barrier

layer to retarded Cu atom diffusion. In addition, Kohn et al. [9] reported that the P

and W impurities stabilize the hexagonal closed-packed (HCP) phase, delaying the

transition to the FCC phase by more than 80°C in comparison with pure Co in bulk

form. It is also reported that 30-nm-thick Co(W,P) films may effectively inhibit the

Cu diffusion after thermal treatments up to 500°C [10]. In brief, electroless Co(W,P)

should be a better diffusion barrier layer than electroless Co(P) does.

2.4. Electroless Deposition

2.4.1. Theory of Electroless Deposition

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is a method of depositing a metal on a substrate using a process of chemical reduction

in an aqueous solution containing a chemical reducing agent without the electrical

energy. The driving force for the reduction of metal ions and their deposition is

supplied by the chemical reducing agent in solution, and the driving potential is

essentially constant at all points of the surface of the component [101]. The

subsequent deposition of metal also serves as the catalytic surface and involves

several simultaneous reactions such as oxidation and reduction in an aqueous solution

so that the electroless plating is also known as chemical or auto-catalytic plating. The

oxidation is characterized as the loss of electrons whereas the reduction is that the

gain of electrons. The reaction equations are expressed as follows [102]:

R + H2O  Ox + H+ + e (2-1)

Mn+ + ne M0 (2-2a)

2H+ +2e H2(g) (2-2b)

where R is the reducing agent, Mn+ is the plating metal ion.

At the initial stage of electroless plating, the metal ions (Mn+) are selectively reduced only at the surface of a catalytic substrate immersed into an aqueous solution

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reaction equations are described as:   _  1n ne 0 1 M M (2-3) 0 2 2 M Mn ne  (2-4)

With continuous deposition, the deposit catalyzes the reduction reaction and

deposits itself on the substrate through the catalytic action, which is the so-called

autocatalytic plating [6].

In an electroless plating bath, there are some compositions listed below

[6,102,103]:

(1) Metallic salt: the main plating source that provides the metal ions when plating.

NiSO4 and CoSO4 are the common metallic salt for the electroless plating in FC

technology.

(2) Reducing agent: a substance that brings about the reduction in other substances by

itself oxidization. A reducing agent is also called a reductant or reducer. Strong

reducing agents easily lose (or donate) electrons. The composition of plating layer

could be controlled by using appropriate reducing agent. HCOH, (CH3)2HN．

BH3(DMAB), NaBH4, and NaH2PO2 are widely used as the reducing agents.

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another material in solution to control the concentration of metal ions in plating

bath and to prevent the insoluble precipitation. Citric acid, sodium citrate, succinic

acid, and sodium acetate are common complex agents.

(4) Accelerator: a substance such as sulfide compounds and fluoride compounds that

may increase the reaction rate. It also restrains the formation of hydrogen.

(5) Stabilizer: a substance that tends to maintain the chemical properties of the

deposition bath, where some catalytic particles are suspended in the bath during

electroless plating. The addition of stabilizers in plating bath may cause the

absorption of the catalytic particles and stabilize the plating bath. The common

stabilizers are sulfide compounds, chloride compounds, thiourea, and heavy metal

salts.

(6) Buffer agent: a solution selected or prepared to minimize changes in hydrogen ion

concentration of the plating bath so that the stability of plating bath and plating

conditions will be maintained.

(7) Brightener: any of the agents which minimizes the deposited particle sizes and

level the roughness of the deposition surface to yield smoother or brighter

coatings.

(8) pH value conditioner: an agent capable of adjusting the pH values to keep the

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2.4.2. Electroless Co(W,P)

When depositing Co on a catalytic surface in an aqueous solution with

appropriate reacting temperature and pH value by electroless plating using

hypophosphite as the reducing agent, electrochemical mechanism, both oxidation and

reduction (redox), occurs simultaneously. The oxidation (here is the oxidation of



2 2PO

H on the catalytic surface) indicates an anodic process, and can be described as

[104]:     _ _ _ _ e (ads) 3 2 (ads) (ads) 2 2PO OH H PO H H (2-5)

The electrons and adsorbed hydrogen atoms that are the products of electroless

Co deposition in weak alkaline media can react with hydrogen ion from the water

) ( 2 (ads) (ads) H H H e    _g (2-6)

At the same time, the released electrons take part in the cathodic reactions, which

include reductions of Co ions, phosphorus (P), and the co-deposition of W. The

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2 3 2 0 (ads) 2 2 2 H PO H Co 2OH PO 2H Co         (2-7)    _ _ __ 2OH P PO H2 2_(ads) e (2-8)

It is known that refractory metal, e.g., Mo and W, can be deposited neither

electrochemically nor chemically, but it can be co-deposited with an iron (Fe) group

metals such as Fe, Co, and Ni. It exists in the anionic form of MoO24 or



2 4

WO in

a deposition bath and could form an intermediate complex compound with the main

metal and complex agent. This complex compound is adsorbed on the electrode

surface, and the iron group metal acts as a catalyst for the reduction of W. This

co-deposition process may go in parallel with the reduction reaction of the iron group

metal in the electrochemical deposition [104]. It has been suggested that intermediate

tungsten-citrate complex at the substrate surface dissociates with the formation of



2 2

WO and this ion, in turn, is reduced to W [96]. Taking into account all above

considerations, the overall W co-deposition reaction can be presented as [104]

    _ _ _ _ _ _ 2H 3H PO 6H W O 4H PO 6H WO2₂ ₂ ₂ ₂ ₂ ₃ ₂ (2-9)

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the components and pH value of plating bath. The concentration of ions affects the

proportion of all the depositing elements in the deposit, e.g., the proportion of P

affects the structure of deposited film directly. Moreover, the pH value affects the

reaction rate, element proportions, and structure of film. The forming products are

mainly H2PO3 and hydrogen ions, which lower the pH value, thus, pH value

conditioner is essential to maintain the structure and elements in the deposited film.

2.5. Motivations

UBM is commonly manufactured by PVD methods such as e-beam evaporation

or sputtering method. Recently, EN layer is applied on UBM manufacture. As

mentioned above, electroless plating possesses the advantages such as simple

equipments and low material cost, and is benefited by its selective and uniform

deposition. Electroless plating hence becomes one of the competitive processes for

UBM manufacture in FC-related technologies.

O’Sullivan et al. [7] reported a superior barrier capability of Co(P) to inhibit the interdiffusion between Cu and ILD in Cu-IC in comparison with EN. Our previous

work confirmed that the electroless Co(P) film might also inhibit interdiffusion

between eutectic PbSn solder and Cu [8]. In addition, enhancement of thermal

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reported previously [9-11]. This thesis work hence investigated the feasibility of

electroless Co(W,P) layer, both amorphous and polycrystalline, as the diffusion

barriers to various solders including eutectic PbSn, SnBi, and SAC. The samples were

treated by liquid-state aging at 250C up to 5 hrs and the solid-state aging at 120C or

150C for 1000 hrs. Afterward, microstructure and composition characterizations

were performed in order to analyze the alloy reactions and morphology evolution at

the solder/Co(W,P) interfaces. The values of Ea for IMC growth and shear strength of

the PbSn/Co(W,P) and SAC/Co(W,P) systems were also investigated. Analytical

results illustrated the good diffusion barrier characteristics of electroless Co(W,P) to

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Chapter 3 Experimental Methods

This work presents a study on the diffusion barrier characteristics of electroless

Co(W,P) to PbSn, SnBi and SAC solders. Ea’s of IMC growth and bonding strengths

are investigated in PbSn/Co(W,P) and SAC/Co(W,P) systems regardless of

crystallinities of Co(W,P) layers. Si wafers sequentially coated with 50-nm thick Ti

and 100 nm-thick Cu were chosen as the substrate to simulate the Cu interconnects.

After pretreatments, about 6-8 m electroless Co(W,P) layers with various

crystallinities were deposited on Cu/Ti/Si substrates. The structure of samples

prepared in this study is schematically illustrated in Fig. 3-1. The methods of sample

preparation, thermal treatments and microstructure/composition characterizations are

described in the following sections.

3.1. Sample Preparation

3.1.1. Substrate Preparation

First, Si wafers were cleaned by RCA process. After forming a thin SiO2 layer on

Si by wet oxidation, the wafers were coated with Ti (50 nm)/Cu (100 nm) layer by

無電鍍鈷鎢磷薄膜對銲錫之擴散阻障特性研究

國立交通大學

材料科學與工程學系

博士論文

無電鍍鈷鎢磷薄膜對銲錫之擴散阻障特性研究

A Study on the Diffusion Barrier Characteristics of

Electroless Co(W,P) Thin Films to Solders

學生：潘虹君（Hung-Chun Pan）

指導教授：謝宗雍 博士（Dr. Tsung-Eong Hsieh）

無電鍍鈷鎢磷薄膜對銲錫之擴散阻障特性研究

摘 要

A Study on the Diffusion Barrier Characteristics of Electroless Co(W,P)

Thin Films to Solders

Abstract

誌 謝

Contents

Figure Captions

Table Captions

Chapter 1

Introduction

Chapter 2

Literature Review

(a)

Chapter 3

Experimental Methods

指導教授：謝宗雍博士（Dr. Tsung-Eong Hsieh）

摘要

誌謝