A 10GBASE-LX4 RECEIVER FRONT END
TRANSIMPEDANCE AMPLIFIER AND LIMITING AMPLIFIER
Hung-Chieh Tsai, Jyh-Yih Yeh, Wei-Hsuan Tu, Tai-Cheng Lee, Chorng-Kuang Wang
Graduate Institute of Electronics Engineering and Department of Electrical Engineering,
National Taiwan University, Taipei, Taiwan
ABSTRACT
A 10 Gbase-LX4 receiver front end including an inductor feedback transimpedance amplifier and a modified Cherry-Hooper cell limiting amplifier realized in a 0.18µm CMOS process is described. The receiver front end covers 34.8 dB input dynamic range and provides 66 dBȍ differential gain with 1.7 GHz bandwidth. All the building blocks achieve a high data rate with low power dissipation. The receiver front end can meet the BER requirement under all corner simulations with 113 ps(pp) data jitter at 3.125 Gb/s. The chip area is 1.1 x 2.2 mm2 and consumes 54mW using 1.8 V supply voltage. The overall performance is verified by the measured results.
1. INTRODUCTION
The demand for large services and increased information, together with the trends of low power, low cost from the market, have accelerated the development of telecommunications which has resulted in the 10 Gigabit Ethernet standard for optical communication. Benefiting from the properties such as high integration, low cost and low power, the scaled CMOS technology is a potential solution for implementing high-speed communication systems that employ parallelism. Key building blocks in this high capacity network consist of a multiplexer (MUX), a retiming flip-flop, and a laser driver in the transmitter and a transimpedance amplifier, a limiting amplifier, a clock and data recovery and a demultiplexer as shown in the receiver. (Fig. 1.) At the receiving end, the signal current is converted into voltage by a low noise, high-speed transimpedance amplifier (TIA). Due to the large input capacitance from the photodiode, the transimpedance amplifier must deal with a wide dynamic input signal current and convert it to a voltage signal with a low contamination from self-noise. The limiting amplifier (LA) is essentially a high speed and high
This work was financially supported by NSC Taiwan, R.O.C. under Grant NSC91-2218-E-002-022
sensitivity hard limiter that quantizes the analog signal coming from the transimpedance amplifier. In general, the TIA is a linear circuit with its output carrying both the signal and noise of the detection subsystem.
Consequently, a decision circuit is therefore needed to regenerate a well-defined digital ones or zeros binary data stream. For a limiting amplifier, the signal is quantized and the output from the limiting amplifier is always at a well-defined level. When designing a transimpedance amplifier, the noise, group delay variation and bandwidth are always practical design issues. And as to the limiting amplifier, bandwidth, input sensitivity, and AM to PM noise also affect the overall system bit error rate (BER) and the data jitter which are associated with the clock and data recovery (CDR).
When designing the circuit near the limitation of the given technology, some circuit techniques such as active peaking [1] [2], zero peaking [3] Cherry-Hooper [4], and ft-doubler[5] can be used to enhance circuit performances. In addition to the circuit techniques, a huge power can also achieve a high data rate operation due to the property of maximum oscillation frequency (fMAX) for a given
technology. In this paper, we describe the design, and successful test of the front-end chip for 10GBase–LX4 receiver using CMOS 0.18µm process. This paper is organized as follows. In Section 2, the design of
Fig. 1. Fibre optical transceiver
MUX Clock Multiplying Unit D FF Q Buffer Power Control Laser Driver SMF / MMF DMUX 1:10 CDR Input Data ( 10 B ) TIA LA I V MB810 DEC 10 10 10 10 32 ,9 ;,((( ,6&$6
transimpedance amplifier is discussed. The proposed gain cell for the limiting amplifier is depicted in Section 3. Lastly, in Section 4, experimental results under on-wafer and board conditions are presented. Finally, a conclusion is drawn in Section 5.
2. CIRCUIT DESIGN OF TIA
The TIA in front of the receiver dominants the overall system noise performance and suffers from the large capacitance at the interface between electrical and optical signals. The inductor feedback architecture of the TIA is shown in Fig. 2(a). The equivalent small signal model of TIA is shown in Fig. 2(b), and we can derive the transfer function as: ) 1 ( Gm Cin) L S(C CinR L C 2 S CinL L C 3 S SL) Gm(R TIA Z |
From equation 1, the added zero from the feedback inductor can reduce the parasitic effect between the TIA and limiting amplifier. The value of inductor is chosen such that it provides enough gain peaking and does not create a large phase distortion for the received data. The single ended output is converted to differential ones by a wide band buffer and the DC extracting RC network is implemented by the MOS in deep n-well. The RC network must maintain similar behavior under the system dynamic range. The transimpedance gain is 56 dBȍ under 0.5 pF photodiode capacitor, and bandwidth is about 0.7 times data rate. The overall power dissipation under 1.8 V power supply is 10 mW.
3. CIRCUIT DESIGN OF LIMITING AMPLIFIER
The limiting amplifier usually deals with the wide dynamic range signal and saturates it to a detectable level for the data recovery. The sensitivity of the LA is nearly twelve times the input rms noise voltage and has an influence on the system BER. When designing the limiting amplifier, the number of gain cells must be determined firstly. Assume that As and wp1 in Eq. (2) represent the gain and -3dB cut-off frequency of each gain cell respectively, and the second pole -3dB cut-off frequency, wp2, is added to model the transfer function as:
) 2 ( N ] ) wp2 s )(1 wp1 s (1 As [ (s) T A
where N is the number of stage in LA. The overall gain can be expressed asΚ
(3) N
(As) t A
and the bandwidth of the LA can be shown asΚ (4) 2N 1 2 ) 2 ) fp2 3dB f ( )(1 2 ) fp1 3dB f ( (1
Assume the second pole, fp2, is m times of the first pole, fp1, namely fp2 = m fp1, thus the fp1 can be found asΚ
(5) 2 ) 2 m (1 1 1) N 1 N (2 2 2m 4 m 3dB f p1 f
The smaller the m, the larger the cell bandwidth is required to meet the overall bandwidth. Assume the required gain is 30 dB and the bandwidth is 2.5 GHz, the gain bandwidth product shows that the appropriate stage number is 5 and requirements for each stage are shown in Fig. 3. It shows that the bandwidth difference between m
= 1.25 and m = 2.5 is 1.5 GHz, and under the worst case one must design a gain stage with 8.5G bandwidth. In order to achieve wideband amplification, the Cherry-Hooper typed wideband amplifier (Fig.4.) is adopted and ˖˟ ˩̂ ˚̀˩˺̆ ˖˼́ ˥ ˟ ˩˺̆ ʾ ˀ ˜ ˩˗˗ ˩̂ ʻ˴ʼ ʻ˵ʼ ˥ ˟
Fig. 2. (a) Transimpedance amplifier (b) Small signal model
Fig. 3. Requirements of (a) gain and (b) bandwidth per stage
(a) (b)
modified to enhance the bandwidth. The pole of the Cherry-Hooper amplifier is reduced to [6]
(6) gd2 C 2 R 2 gm o C 2 C 2 2gm p w
with respect to that without feedback. To avoid the gain-headroom trade-off in the Cherry-Hooper amplifier, the
additional load can be applied at the drain of transistor M1 and provides part of the bias current of the input differential pair. The modified Cherry-Hooper gain cell is shown in Fig. 5, and its small signal model including Co is shown. From the node equation, the relation between Vg2 and Vo can be found as:
) 7 ( SL) (Rf m2 g Rf m3 g ) m3 Lg f R o S(C o LC 2 S o V g2 V If LCoCdRd << 1, then Rf m3 g Rd) 2 RfC m3 g Rf o C m3 S(Lg ) d R 2 C m2 Lg RfRd 2 C o C o (LC 2 S SL) Rd(Rf m2 g m1 g Vin o V |
The equation shown above indicates an additional zero to cancel the high frequency pole and therefore the bandwidth is enlarged. In addition, it does not need a large tail current to make unity-gain frequency (ft) large. Thus
the power can be smaller than conventional circuits in this band. Due to the cascaded structure, the peaking must be taken into consideration. Taking 30 dB gain with 1 dB peaking for example, the demanded quality factor per stage must be less than 0.8 corresponding to 0.7 dB peaking (Fig. 6). The differential mode stability of the limiting amplifier is verified with the stability condition parameters, k and Ϧ . The common mode stability depends on the performance of the offset cancellation-loop, and this design is unconditionally stable and provides an offset cancellation-range ̈́ 200mVpp. The stability of the overall front-end circuits is shown in Fig. 7.
4. EXPERIMENTAL RESULTS
The receiver chip is fabricated using 0.18Ӵm CMOS technology. The chip photo shown in Fig.8 covers an active area 1.9 x 0.9 mm2. The external components in the testing board include a feedback cancellation capacitor, and some decoupling capacitors. The frequency response is under on-wafer testing and the eye diagram is on board testing. The sigle-ended transimpedance gain is 60 dBӨ with 1.72 GHz bandwidth which is sufficient for 10GBASE-LX4. (Fig. 9.) Since the random data gene-rator can only provide a 250mVpp data sequence, which is not small enough for sensitivity testing, an additional 30 dB wideband attenuator is used to achieve the
require-C2 Co Vout Vin M1 M2 Cgd2 R2
Fig. 4 Cherry-Hooper amplifier
vout Vin-Vin+ L Rf Rd M1 M2 M3 Vin gm1Vin Vg2 gm2Vg2 Rd//SC21 SL Rf Vo o SC 3 gm 1 ( a ) ( b )
Fig. 5.(a) Gain cell for LA (b) Small signal model
Fig. 6. Peaking of the LA
K > 1
Ӕ< 1
Fig. 7. Stability of the front-end circuits
ment. The testing random pattern with 231 -1 pseudo-random bit sequence (PRBS) is applied to the chip input and the eye diagrams under the minimum and maximum inputs at the data rate from 1.25 Gb/s to 3.125 Gb/s are shown in Fig. 10 (a)(b)(c) respectively. An important parameter of the receiver is the data jitter. The data jitters for 1.25 Gb/s, 2.5 Gb/s and 3.125 Gb/s under 29 -1 PRBS are 42 ps (pp), 108 ps, and 113 ps respectively. The large jitter under -18 dBm input signal is due to the random jitter resulting from thermal noise, variation of the supply voltage and the finite chip bandwidth. The performance is summarized in TABLE1.
5. CONCLUSION
The receiver front end including transimpedance amplifier and fully differential limiting amplifier for 10GBASE-LX4 is presented. The modified Cherry-Hooper gain cells are proposed to lower the power dissipation in the limiting amplifier. The sensitivity of the chip at 3.125Gb/s is -16dBm and delivers 250mVpp to the next stage. This receiver active size is 1.9 x 0.9 mm2 and it consumes 54mW from a 1.8 V power supply.
Technology CMOS 0.18Ӵm , 1.8 V
Bandwidth 1.7 GHz
AC Gain 60 dBӨ
Rise / Fall Time (10 % - 90 %) 68 ps
Output swing 250 mVpp
Data jitter @ 3.125 Gb/s 113 ps (p-p)
Input sensitivity -16 dBm
Input Return Loss < -8 dB
Power Dissipation 54 mW
6. REFERENCES
[1] Helen Kim, Jonathan Bauman, “A 12 GHz 30 dB Modular BiCMOS Limiting Amplifier for 10 Gb SONET Receiver,”
ISSCC Dig. Tech. Papers, 2000.
[2] Helen H. Kim, S. Chandrasekhar, Charles A. Burrus Jr., Life Fellow and Jon Bauman, “A Si BiCMOS Transimpedance Amplifier for 10 Gb/s SONET Receiver,” IEEE J. Solid-State
Circuits, May, 2001.
[3] Kenichi Ohhata, Toru Masuda, Ryoji Takeyari, and Katsuyoshi Washio, “A Wide Dynamic Range, High Transimpedance Si Bipolar Preamplifier IC for 10 Gb/s Optical Fiber Links,” IEEE J. Solid-State Circuits, Jan., 1999.
[4] L.Ingmar Andersson, P.Thomas Lewin, Sylvia M. Planer, and Sam L. Sundaram, “Silicon Bipolar Chipset for SONET/SDH 10Gb/s Fiber Optic Communi- cation Links,”
IEEE J. Solid-State Circuits, 1995.
[5] Richard C.Walker, Kuo-Chiang Hsieh, Thomas A.Knotts and Chu-Sun Yen, “A 10Gb/s Si-Bipolar TX/RX Chipset for Computer Data Transmission,” ISSCC Dig. Tech. Papers, 1998. [6] Behzad Razavi, Design of Integrated Circuits for Optical
Communications, 2003.
TABLE1 Performance summary of receiver front-end transimpedance amplifier and limiting amplifier
Fig. 8 Chip photo of the receiver front-end circuits
Fig. 9. Frequency response of the receiver front end
.1 1 10 Frequency (GHz) Graph 2 -20 0 20 40 60 80 1.72 GHz 57 0.156 GHz 60 DB(|Z[2,1]|) power_n5_0_S Pin = -24 dBm Pin = -20 dBm Pin = -16 dBm Pin = 4 dBm Pin = 4 dBm Pin = 4 dBm (a) (b) (c)
Fig. 10. Eye diagrams at (a) 1.25 Gb/s (b) 2.5 Gb/s (c) 3.125 Gb/s
