Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process

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Low-capacitance ESD protection design for high-speed I/O interfaces

in a 130-nm CMOS process

Yuan-Wen Hsiao

a,*

, Ming-Dou Ker

a,b

a

Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung University, No. 1001, Ta-Hsueh Rd., Hsinchu City, Taiwan

b_{Department of Electronic Engineering, I-Shou University, No. 1, Sec. 1, Syuecheng Rd., Dashu Township, Kaohsiung County, Taiwan}

a r t i c l e

i n f o

Article history:

Received 18 November 2008

Received in revised form 19 February 2009 Available online 22 April 2009

a b s t r a c t

Electrostatic discharge (ESD) protection design for high-speed input/output (I/O) interface circuits in a 130-nm CMOS process is presented in this paper. First, the ESD protection diodes with different dimen-sions were designed and fabricated to evaluate their ESD levels and parasitic effects in gigahertz fre-quency band. With the knowledge of the dependence of device dimensions on ESD robustness and the parasitic capacitance, whole-chip ESD protection scheme were designed for the general receiver and transmitter interface circuits. Besides, an ESD protection scheme is proposed to improve the ESD robust-ness under the positive-to-VSS(PS-mode) ESD test, which is the most critical ESD-test pin combination.

With a silicon-controlled rectiﬁer (SCR) between the I/O pad and VSS, the clamping voltage along the

PS-mode ESD current path can be reduced, so the PS-mode ESD level can be improved. Besides, the par-asitic P-well/N-well diode in the SCR can provide the NS-mode ESD current path. Thus, SCR is the most promising ESD protection device in ESD protection design with low-capacitance consideration. The ESD protection scheme presented in this paper has been practically applied to an IC product with 2.5-Gb/s high-speed front-end interface.

1. Introduction

With the advantage of low cost and high integration capability, more and more integrated circuits (ICs) have been fabricated in CMOS processes, including the high-speed input/output (I/O) inter-face circuits. Electrostatic discharge (ESD), which has been one of the most important reliability issues for CMOS ICs, must be taken into consideration during the design phase[1]. To achieve satisfac-tory high-speed circuit performance, high-speed I/O interface cir-cuits have been fabricated in nanoscale CMOS processes due to the advantage of superior high-frequency device characteristics. With the reduced gate-oxide thickness and lower gate-oxide breakdown voltage, nanoscale MOS transistors are very vulnerable to ESD, because ESD does not shrink with CMOS processes. Re-cently, several ESD protection designs for high-speed I/O applica-tions have been reported[2–6], and the negative impacts of ESD protection circuits on high-speed I/O interfaces have been studied

[7,8]. Diodes have been used to protect the dual-channel optical transceiver array [2]. To lower the overall capacitive load at the I/O pad, the ESD protection scheme with the T-coil and negative impedance converter has been reported [3]. In the silicon-con-trolled rectiﬁer (SCR)-based ESD protection scheme, an RC-based ESD detection circuit and an NMOS have been used to draw the trigger current from the base terminal of the PNP BJT in the SCR

un-der ESD stresses[4]. Besides, a modiﬁed SCR with a low trigger voltage has been used to protect the DRAM with DDR3 interface

[5]. Another design with the darlington-based SCR structure has been proposed to reduce the ﬁrst breakdown voltage of SCR[6].

There are two major considerations in ESD protection design for speed I/O interfaces. First, ESD protection circuits for high-speed I/O interfaces must sustain high enough ESD robustness to effectively protect the thin gate oxide of the MOS transistor in the internal circuits against ESD stresses. Second, the high-speed circuit performance degradation due to the parasitic effects of the ESD protection devices needs to be minimized[9].

Traditional ESD protection devices with large dimensions, which have large parasitic capacitance, would signiﬁcantly de-grade the high-speed circuit performance. Therefore, traditional ESD protection designs with large ESD protection devices are no longer suitable for high-speed I/O applications because of the intol-erable large parasitic effects. With proper design, the double-diode ESD protection scheme in cooperation with the active power-rail ESD clamp circuit can be used to realize the whole-chip ESD pro-tection scheme for high-speed I/O applications with minimum degradation on the circuit performance.

In order to minimize the parasitic capacitance caused by the ESD protection devices and to achieve satisfactory ESD robustness, the high-frequency characteristics and the ESD levels of the ESD protection diodes in a 130-nm CMOS process were evaluated in this work to obtain the dependence of device size on ESD 0026-2714/$ - see front matter Ó 2009 Elsevier Ltd. All rights reserved.

doi:10.1016/j.microrel.2009.03.011

*Corresponding author. Tel.: +886 3 5131573; fax: +886 3 5715412. E-mail address:[email protected](M.-D. Ker).

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Microelectronics Reliability

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robustness and parasitic capacitance. After determining the dimen-sions of ESD protection diodes, whole-chip ESD protection scheme can be realized with the active power-rail ESD clamp circuit[10]. To investigate the ESD robustness of the general receiver and transmitter interface circuits with the proposed whole-chip ESD protection scheme, the receiver NMOS emulator and transmitter NMOS emulator were fabricated in a 130-nm CMOS process. In the receiver NMOS emulator and transmitter NMOS emulator, the I/O pad is connected to the gate terminal and drain terminal of the NMOS transistor, respectively. After investigating the ESD robustness of the receiver NMOS emulator and transmitter NMOS emulator, the positive-to-VSS(PS-mode) ESD test was found to be

the most critical ESD-test pin combination. Another ESD protection scheme using the substrate-triggered SCR between the I/O pad and VSSis proposed in this work to improve the PS-mode ESD

robust-ness. The proposed ESD protection schemes have been applied to a 2.5-Gb/s high-speed I/O interface circuit in a 130-nm CMOS process. Experimental results have shown that good high-speed circuit performance and high ESD robustness can be achieved simultaneously.

2. ESD protection diodes

The most popular ESD protection devices at the I/O pad are the shallow-trench-isolation (STI) diodes[11,12]. The device charac-teristics of the STI diodes in a 0.18-

l

m CMOS process have been

investigated[13]. There are three diodes available in the 130-nm CMOS process, which are the P+/N-well diode, N+/P-well diode, and N-well/P-substrate diode. The P+/N-well diode is placed be-tween the I/O pad and VDD, because the N-well is often connected

to VDD. The layout top view and cross-sectional view of P+/N-well

diode are shown inFig. 1a and b, respectively. In a P+/N-well diode, the P+ diffusion is connected to the I/O pad, and the parasitic ef-fects between the P+/N-well junction is contributed to the I/O pad. The size of the P+/N-well diode is referred to the size of the P+ diffusion. On the contrary, the N+/P-well diode is connected be-tween the I/O pad and VSS, because the P-well must be connected

to VSS. The layout top view and cross-sectional view of N+/P-well

diode are shown inFig. 2a and b, respectively. Since the N+ diffu-sion is connected to the I/O pad, the size of an N+/P-well diode is referred to the size of the N+ diffusion. Another ESD protection diode which can be used between the I/O pad and VSSis the

N-well/P-substrate diode, whose layout top view and cross-sectional view are shown inFig. 3a and b, respectively. In the N-well/P-sub-strate diode, the N-well is connected to the I/O pad through the N+ diffusion. Thus, the size of the N-well region is the design param-eter of the N-well/P-substrate diode. The dependence of ESD robustness on parasitic capacitance in a 130-nm CMOS process was investigated in this work to solve the trade-off between the ESD protection capability and the high-speed performance degra-dation. These three kinds of diodes with junction perimeters of 20, 40, and 80

l

m have been designed and fabricated in a 130-nm CMOS process.

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For high-speed I/O applications, the parasitic capacitance of the ESD protection diode is a key factor because it directly affects the high-speed circuit performance. To evaluate the parasitic capaci-tance of the ESD protection diodes, the two-port S-parameters of the fabricated ESD protection diodes were measured with the net-work analyzer. In the S-parameter measurement, port 1 and port 2 of the network analyzer were connected to the two terminals of the diode. Port 1 is connected to the terminal which is connected to the I/O pad when the ESD protection diode is applied to the high-speed I/O interface circuits. Port 2 is connected to the termi-nal which is connected to the AC ground node (VDDor VSS) when

the ESD protection diode is applied to the high-speed I/O interface circuits. With the measured two-port S-parameters, the Y11

-parameter can be obtained with the conversions between two-port S-parameters and two-port Y-parameters, which is given by[14] Y11¼

ð1 S11Þð1 þ S22Þ þ S12S21

Z0½ð1 þ S11Þð1 þ S22Þ S12S21 ð1Þ

where Z0is the termination resistance and is 50X in this work.

After obtaining the Y11-parameter, the parasitic capacitance (Cdiode)

of the ESD protection diode was extracted by

Cdiode¼

ImðY11Þ

x

¼

ImðY11Þ

2

p

f ð2Þ

where Y11-parameter is the admittance seen from port 1 with port 2

grounded, Im(Y11) denotes the imaginary part of the Y11-parameter,

and f is the operating frequency. The extracted parasitic capaci-tances of the P+/N-well ESD protection diodes at 2.5 GHz are listed inTable 1. At 2.5 GHz, the extracted parasitic capacitances of P+/N-well diode with 20-, 40-, and 80-

l

m junction perimeters are 27.9, 51.1, and 77.7 fF, respectively.Tables 2 and 3list the parameters of the N+/P-well and N-well/P-substrate ESD protection diodes, respectively. For the N+/P-well diode (N-well/P-substrate) diode, the extracted parasitic capacitances at 2.5 GHz under 20-, 40-, and 80-

l

m junction perimeters are 37.9 (40.5), 66.3 (69.3), and 89.7 fF (81.9 fF), respectively. The parasitic capacitance of the ESD protec-Fig. 3. (a) Layout top view and (b) cross-sectional view of N-well/P-substrate diode.

Table 1

Characteristics of P+/N-well ESD protection diodes in a 130-nm CMOS process. Junction perimeter (lm) Junction area (lm2

) Cdiodeat DC (fF) Cdiodeat 2.5 GHz (fF) It2 (A) HBM ESD level (kV)

P+/N-well diode

20 25 25.9 27.9 0.62 1

40 75 75.7 51.1 1.47 3

80 150 151.4 77.7 4.18 6

Table 2

Characteristics of N+/P-well ESD protection diodes in a 130-nm CMOS process. Junction perimeter (lm) Junction area (lm2

N+/P-well diode

20 25 20 37.9 0.55 1

40 75 58.1 66.3 1.56 3

80 150 116.2 89.7 3.75 6

Table 3

Characteristics of N-well/P-substrate ESD protection diodes in a 130-nm CMOS process. Junction perimeter (lm) Junction area (lm2

N-well/P-sub diode

20 25 24.1 40.5 0.61 1

40 75 52.1 69.3 1.84 3

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tion diode becomes larger when the diode size increases. Larger junction area and larger junction perimeter in the diode lead to lar-ger junction capacitance. Besides, the zero-bias DC junction capac-itance (Cdiode_DC) can be calculated by using the SPICE model

provided by the foundry, which is given by

Cdiode DC¼ ðTotal Junction AreaÞ Cj

þ ðTotal Junction PerimeterÞ Cjsw ð3Þ

where Cjand Cjsware the zero-bias bottom-plate capacitance per

unit junction area and the zero-bias side-wall capacitance per unit junction perimeter, respectively. The values of Cjand Cjsware

pro-vided in the SPICE model. As listed inTable 1, the calculated DC junction capacitances of the P+/N-well diode with 20-, 40-, and 80-

l

m junction perimeters are 25.9, 75.7, and 151.4 fF, respectively. FromTables 2 and 3, the calculated DC junction capacitances of N+/ P-well (N-well/P-substrate) diodes under 20-, 40-, and 80-

l

m junc-tion perimeters are 20 (24.1), 58.1 (52.1), and 116.2 fF (104.2 fF), respectively. Since Cj and Cjsw are different in N+/P-well and

N-well/P-substrate diodes, the relationships between their DC junc-tion capacitances under different dimensions are different. The dif-ference between the extracted parasitic capacitance and the calculated junction capacitance is attributed to the parasitic series resistance in the well or substrate region, and the parasitic effects of metal routing.

Tables 1–3also list the ESD levels of the P+/N-well, N+/P-well, and N-well/P-substrate ESD protection diodes, respectively. The characteristics of the fabricated ESD protection diodes in high-cur-rent regions were characterized by the transmission line pulsing (TLP) system with 10-ns rise time and 100-ns pulse width[15]. Moreover, the secondary breakdown current (It2) can be obtained in the TLP-measured I–V curve. It2 is the highest current that the device can handle under ESD stresses, which denotes the current at the failure point. The TLP-measured I–V curves of the stand-alone P+/N-well, N+/P-well, and N-well/P-substrate diodes with different dimensions under forward-biased condition are shown in Fig. 4. The It2 values of the P+/N-well diodes with 20-, 40-, and 80-

l

m junction perimeters are 0.62, 1.47, and 4.18 A, respec-tively. The It2 of the N+/P-well diodes with the junction perimeters of 20-, 40-, and 80-

l

m are 0.55, 1.56, and 3.75 A, respectively. As compared with the N+/P-well diodes, the N-well/P-substrate diodes have slightly higher It2 values. The It2 values of the N-well/P-substrate diodes with 20-, 40-, and 80-

l

m junction perim-eters are 0.61, 1.84, and 3.9, respectively.Fig. 5compares the It2 values of the ESD protection diodes with different device dimen-sions. As shown inFig. 6, these three kinds of diodes exhibit

iden-tical human-body-model (HBM)[16]ESD levels under the same

device. The HBM ESD levels are 1, 3, and 6 kV with the junction

perimeters of 20, 40, and 80

l

m, respectively. The measured

HBM ESD levels are proportional to the device size, which demon-strates that good turn-on uniformity is achieved. Experimental re-sults have shown that diodes with larger dimensions have higher ESD robustness, but larger diodes exhibit larger parasitic capacitance.

3. Whole-chip ESD protection design

To investigate ESD robustness of the typical receiver and trans-mitter interface with the ESD protection diodes and the power-rail ESD clamp circuit, the test circuits with the receiver NMOS emula-tor and transmitter NMOS emulaemula-tor were implemented in a 130-nm CMOS process. In the receiver NMOS emulator and transmitter NMOS emulator, the I/O pad is connected to the gate terminal and drain terminal of the NMOS transistor, respectively. With the typ-ical connection between the I/O pad and the MOS transistor, the ESD robustness of the ESD-protected receiver and transmitter

interface circuits can be estimated by the ESD robustness of the

re-ceiver NMOS emulator and transmitter NMOS emulator,

respectively.

3.1. Power-rail ESD clamp circuit

The power-rail ESD clamp circuit is an essential block in the whole-chip ESD protection design[17]. With the ESD current path between VDDand VSSprovided by the power-rail ESD clamp circuit,

the ESD protection diodes at the I/O pad can be ensured to be oper-ated in the forward-biased condition under all ESD-test pin combi-nations to achieve high ESD robustness.

In this work, the ESD clamp device in the power-rail ESD clamp circuit is realized by the P-type substrate-triggered SCR (P-STSCR), Fig. 4. TLP-measured I–V curves of (a) P+/N-well diodes, (b) N+/P-well diodes, and (c) N-well/P-substrate diodes with different dimensions.

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because SCR has been demonstrated to have high ESD robustness under a small layout area[18,19]. The cross-sectional view and equivalent circuit of the P-STSCR are shown inFig. 7. The SCR path exists among the P+ diffusion (anode), N-well, P-well, and N+ dif-fusion (cathode). The equivalent circuit of the P-STSCR consists of a parasitic vertical PNP BJT and a parasitic lateral NPN BJT. The PNP BJT QPNPis formed by the P+ diffusion (anode), N-well, and

P-well. The NPN BJT QNPNis formed by the N-well, P-well, and N+

diffusion (cathode). In the power-rail ESD clamp circuit, the anode and N-well of the P-STSCR are connected to VDD, while the cathode

and P-well of the P-STSCR are connected to VSS. To quickly turn on

the STSCR under ESD stresses, the P+ trigger diffusion (in the P-well region) was added between the anode and cathode. An extra ESD detection circuit was designed to inject trigger current to the P-trigger node under ESD stresses. After the voltage drop across the P-well resistance (RP-well) is larger than the cut-in voltage of

the base-emitter junction of QNPN, QNPNis turned on to conduct it

collector current, which leads to voltage drop across the N-well resistance (RN-well). When the voltage drop across RN-wellis larger

than the cut-in voltage of the base-emitter junction of QPNP, QPNP

is also turned on to conduct ESD current, which causes more col-lector current of QNPNdue to the current gain of BJT. The

regener-ative positive-feedback mechanism[20]results in the great current handing capability of SCR, and makes SCR very robust against ESD stresses.

The power-rail ESD clamp circuit is shown inFig. 8, which in-cludes the P-STSCR and the ESD detection circuit. The ESD detec-tion circuit consists of an RC timer and an inverter. The RC timer is designed to distinguish the ESD transients from the normal cir-cuit operating conditions. Under normal circir-cuit operating condi-tions, the node between R and C is charged to high potential (VDD). Since NMOS MNis turned on and PMOS MPis turned off,

the P-trigger node is tied to VSSand no trigger current is injected.

Consequently, the P-STSCR is kept off under normal circuit operat-ing conditions. Under ESD stresses, the ESD energy is coupled to VDD quickly. With the RC delay provided by the resistor R and

the capacitor C, the gate voltages of MPand MNare initially biased

at low potential (0 V). Therefore, MPis turned on to inject trigger

current into the P-trigger node. As a result, the P-STSCR is turned on to provide ESD current path between VDDand VSS under ESD

stresses.

Since the power-rail ESD clamp circuit is placed between VDD

and VSS, it does not contribute any parasitic capacitance to the

in-put nor outin-put pads of the high-speed I/O interface circuits. Thus, the size of the P-STSCR in the power-rail ESD clamp circuit is not limited by the speciﬁcation of parasitic capacitance at the high-speed I/O pad.

3.2. ESD protection design with receiver NMOS emulator

Fig. 9shows the schematic of the receiver NMOS emulator. In the receiver NMOS emulator, the gate terminal of the NMOS MRX

was connected to the I/O pad, whereas the drain, source, and bulk terminals are grounded. The ESD protection diode (DP) between

the I/O pad and VDDwas realized by the P+/N-well diode, whereas

the ESD protection diode (DN) between the I/O pad and VSS was

realized by the N-well/P-substrate diode. According to the mea-sured results in Section2, the stand-alone ESD protection diodes with more than 40-

l

m junction perimeter can sustain over 2-kV Fig. 6. HBM ESD levels of ESD protection diodes under different dimensions in a

130-nm CMOS process. The ESD protection diodes have identical HBM ESD robustness under the same size.

Fig. 7. Cross-sectional view and equivalent circuit of P-STSCR. Fig. 5. TLP-measured It2 values of ESD protection diodes under different dimen-sions in a 130-nm CMOS process.

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HBM ESD level, which is the speciﬁcation for general commercial IC products. To increase the margin of ESD robustness, namely, to reduce the voltage drop across the internal circuits under ESD stresses and to lower the turn-on resistance of the ESD protection devices, the ESD protection diodes were realized with 45- and

55-l

m junction perimeters to compare their ESD levels. The P-STSCR in the power-rail ESD clamp circuit was implemented with

59.6-l

m width. When the I/O pad of receiver NMOS emulator is stressed by ESD, the voltage across the I/O pad and VSSis across the gate

oxide, which is the worst case for the gate oxide of NMOS under ESD stresses. Since the gate terminal of the MOS transistor is often

connected to the input pad of the receiver, the ESD robustness of receiver NMOS emulator can be used to estimate the ESD robust-ness of the practical receiver interface circuit with this ESD protec-tion scheme.

3.3. ESD protection design with transmitter NMOS emulator

Fig. 10shows the schematic of the transmitter NMOS emulator. In the transmitter NMOS emulator, the drain terminal of the NMOS MTXwas connected to the I/O pad, whereas the gate, source, and

bulk terminals are grounded. Similarly, the ESD protection diode (DP) between the I/O pad and VDDwas realized by the P+/N-well

diode, and the ESD protection diode (DN) between the I/O pad

and VSSwas realized by N-well/P-substrate diode. DPand DNwith

45- and 55-

l

m junction perimeters were used in the ESD protec-tion scheme for the transmitter NMOS emulator. The P-STSCR in the power-rail ESD clamp circuit was implemented with 59.6-

l

m width. When the I/O pad is stressed by ESD, the voltage between the I/O pad and VSSis across the drain terminal and the other three

terminals of the NMOS transistor. Since the drain terminal of the MOS transistor is often connected to the output pad of the trans-mitter, the ESD robustness of the transmitter NMOS emulator can be used to estimate the ESD robustness of the practical trans-mitter interface circuit protected by this ESD protection scheme. 3.4. ESD levels of receiver NMOS emulator and transmitter NMOS emulator

The calculated DC junction capacitances of DPwith 45- and

55-l

m junction perimeters are 88.1 and 118 fF, whereas the calcu-lated DC junction capacitances of DNwith 45- and 55-

l

m junction

perimeters are 59.1 and 73.1 fF. The HBM and machine-model (MM)[21]ESD levels of the receiver NMOS emulator and transmit-ter NMOS emulator with different diode junction perimetransmit-ters are listed in Tables 4 and 5, respectively. The step voltages in the HBM and MM ESD tests are 500 V and 50 V, respectively. With the active power-rail ESD clamp circuit, the ESD protection diodes are assured to be operated in the forward-biased condition rather than the reverse-biased condition under all ESD-test pin combina-tions. Therefore, high enough ESD robustness can be achieved in the receiver NMOS emulator and transmitter NMOS emulator. The receiver NMOS emulator with 45-

l

m diode junction perimeter has 2.5-kV HBM and 100-V MM ESD robustness. By using the ESD protection diodes with 55-

l

m junction perimeter in the receiver NMOS emulator, the HBM and MM ESD levels are improved to 3 kV and 150 V, respectively. In the transmitter NMOS emulator Fig. 10. Transmitter NMOS emulator used as a test circuit to verify the effectiveness

of the proposed ESD protection scheme in a transmitter (double diodes and active power-rail ESD clamp circuit).

Fig. 9. Receiver NMOS emulator used as a test circuit to verify the effectiveness of the proposed ESD protection scheme in a receiver (double diodes and active power-rail ESD clamp circuit).

Table 4

ESD Robustness of receiver NMOS emulator with different dimensions of ESD protection diodes. Junction area (lm2

) Junction perimeter (lm) PS-mode NS-mode PD-mode ND-mode

DP DN DP DN HBM (kV) MM (V) HBM (kV) MM (V) HBM (kV) MM (V) HBM (kV) MM (V)

Receiver NMOS emulator

87.5 87.5 45 45 2.5 100 3 200 3 150 3.5 200

112.5 112.5 55 55 3 150 4 200 4 200 4 250

Table 5

ESD robustness of transmitter NMOS emulator with different dimensions of ESD protection diodes. Junction area (lm2

) Junction perimeter (lm) PS-mode NS-mode PD-mode ND-mode

DP DN DP DN HBM (kV) MM (V) HBM (kV) MM (V) HBM (kV) MM (V) HBM (kV) MM (V)

Transmitter NMOS emulator

87.5 87.5 45 45 3 300 6 450 3.5 400 5 300

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with 45-

l

m diode junction perimeter, the HBM and MM ESD levels are 3 kV and 300 V, respectively. With 55-

l

m diode junction perimeter, the HBM ESD level is improved to 3.5 kV with the MM ESD level unchanged. The transmitter NMOS emulator has higher negative-to-VSS (NS-mode) and negative-to-VDD (ND-mode) ESD

levels as compared with those of the receiver NMOS emulator, be-cause the parasitic P-well/N+ junction diode between the bulk and drain of the transmitter NMOS emulator discharges some ESD cur-rent. Moreover, it is found that the PS-mode ESD test is the most critical ESD-test pin combination for both receiver NMOS emulator and transmitter NMOS emulator. Under the PS-mode ESD stress, the ESD current path consists of the diode DPand the power-rail

ESD clamp circuit. In this situation, the voltage drop along the whole ESD current path is across the gate oxide of the receiver

NMOS emulator and transmitter NMOS emulator. Under the ND-mode ESD stress, the ESD current path consists of the power-rail ESD clamp circuit and the diode DN. However, the voltage across

the gate oxide of the receiver NMOS emulator and transmitter NMOS emulator is only the voltage across DN. With the highest

voltage across the gate oxide, the PS-mode ESD test becomes the most critical ESD-test pin combination. In the following section, a modiﬁed design to improve the PS-mode ESD level is proposed. 4. ESD-protected high-speed I/O interface circuit

After investigating the ESD robustness of receiver NMOS emula-tor and transmitter NMOS emulaemula-tor, this whole-chip ESD protec-tion scheme was applied to a 2.5-Gb/s high-speed receiver Fig. 11. The ﬁrst whole-chip ESD protection scheme for 2.5-Gb/s high-speed receiver interface circuit (Receiver_1–Receiver_2).

Table 6

Dimensions of ESD Protection Devices in High-speed receiver interface circuits without and with double-diode ESD protection scheme.

ESD protection device between I/O pad and VDD ESD protection device between I/O pad and VSS Total CESD

Device CESO(fF) Device CESO(fF)

Receiver_0 None 0 None 0 0

Receiver_1 DP(PJ = 35lm) 63.2 DN(PJ = 35lm) 45.1 108.3

Receiver_2 DP(PJ = 55lm) 117.9 DN(PJ = 55lm) 73.1 191

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interface circuit in a 130-nm CMOS process.Fig. 11shows the ESD protection scheme for a 2.5-Gb/s high-speed receiver interface cir-cuit. The receiver interface circuit has the differential input stage realized by PMOS transistors. In the power-rail ESD clamp circuit, the ESD clamp device of P-STSCR was realized with 59.6-

l

m width. Two diode junction perimeters of 35 and 55

l

m were implemented in the ESD protection scheme shown inFig. 11. According toTable 4, the ESD protection diodes with 45-

l

m junction perimeter can sustain 2.5-kV HBM ESD robustness. In this high-speed receiver interface circuit, the ESD protection diodes with 35-

l

m junction perimeter are implemented to investigate its ESD robustness be-cause lower parasitic capacitance from the ESD protection devices is preferred.Table 6lists the dimensions of the ESD protection de-vices and the corresponding DC junction capacitance (by calcula-tion) in the high-speed receiver interface circuit without and with the double-diode ESD protection scheme. In Receiver_1 (Re-ceiver_2) with the diode junction perimeter of 35

l

m (55

l

m), the calculated capacitance from the ESD protection devices at the I/O pad is 108.3 fF (191 fF).

It was mentioned that the PS-mode ESD test is the most critical ESD-test pin combination for the ESD protection scheme shown in

Fig. 11. A modiﬁed design is proposed to improve the PS-mode ESD robustness, as shown inFig. 12. In the proposed ESD protection scheme, the ESD protection diode between the I/O pad and VSSis

replaced with the P-STSCR. The device dimensions in the power-rail ESD clamp circuit inFig. 12are identical to those inFig. 11. Since the P-STSCR is already used in the power-rail ESD clamp cir-cuit, the ESD detection circuit in the power-rail ESD clamp circuit can also be used to inject trigger current into the P-STSCRs (P-STSCR1 and P-STSCR2) at the I/O pads under ESD stresses. Under

PS-mode ESD stresses, the ESD voltage is coupled from the I/O pad to VDDthrough DP, and the P-STSCR devices can be turned on

by the ESD detection circuit. When the P-STSCR at the I/O pad is turned on, it provides an ESD current path directly from the I/O pad to VSS. As a result, ESD current will ﬂow through only the

P-STSCR at the I/O pad instead of through DPand the power-rail

ESD clamp circuit. With fewer ESD protection devices and lower voltage drop along the ESD current path under PS-mode ESD tests, higher ESD robustness can be achieved. In the proposed design, the P-STSCR at the I/O pad was implemented with 20-, 30-, and 50-

l

m widths to investigate the ESD levels with different parasitic capac-itances at the I/O pad. The dimensions of the ESD protection

de-vices in the proposed ESD protection scheme and the

corresponding DC junction capacitances (by calculation) are listed inTable 7. In Receiver_3 (Receiver_4) with 20-

l

m wide P-STSCR between the I/O pad and VSS, the calculated parasitic capacitance

at each I/O pad is 127.9 fF (182.6 fF) when DPis realized with

35-l

m (55-

l

m) junction perimeter. When the width of the P-STSCR between the I/O pad and VSSis increased to 30

l

m, the calculated

parasitic capacitances at each I/O pad is 153.3 fF (208 fF) in Recei-ver_5 (Receiver_6) with 35-

l

m (55-

l

m) DPperimeter. With 50-

l

m

wide P-STSCR between the I/O pad and VSS, Receiver_7 (Receiver_8)

with 35-

l

m (55-

l

m) DPperimeter has the parasitic capacitance of

204.1 fF (258.8 fF) at each I/O pad. To verify the effectiveness of the

ESD protection schemes, the high-speed receiver interface circuit (Receiver_0) without ESD protection was also fabricated in the same process.

To save the chip area of the ESD-protected high-speed receiver interface circuit, the ESD protection devices at the input node, MP,

MN, and the P-STSCR in the power-rail ESD clamp circuit were

placed under the I/O pad[22].Fig. 13shows the layout top view of the ESD protection devices under the bond pad in Receiver_1 and Receiver_2. The cross-sectional view of the ESD protection de-vices under the bond pad is shown inFig. 14. By putting DPand MP

together, only an N-well is needed. DNand MNare put together in

the layout. The P-STSCR in the power-rail ESD clamp circuit is real-ized between the N-well and P-well regions. In Receiver_3 to Re-ceiver_8, the P-STSCR between the I/O pad and VSSis also placed

under the I/O pad. Besides saving the chip area, placing the ESD protection devices under the I/O pad reduces some parasitic capac-itance at the I/O pad because the bond-pad capaccapac-itance and the parasitic capacitance of the ESD protection devices are series con-nected between the I/O pad and the substrate.

The nine high-speed receiver interface circuits were fabricated in a 130-nm CMOS process. The HBM ESD levels of the high-speed receiver interface circuits without and with the double-diode ESD protection scheme are listed inTable 8. Without ESD protection, Reveiver_0 is very vulnerable to ESD, which fails at 0.5-kV HBM ESD test. With the double-diode ESD protection scheme, Recei-ver_1 and Receiver_2 have 2- and 3-kV HBM ESD levels,

respec-tively. Table 9 lists the HBM ESD levels of the high-speed

receiver interface circuits with the proposed ESD protection scheme. By using the P-STSCR between the I/O pad and VSS, the

PS-mode ESD robustness is improved. With 20-, 30-, and 50-

l

m

wide P-STSCR between the I/O pad and VSS, the PS-mode HBM

Table 7

Dimensions of ESD protection devices in High-speed receiver interface circuits with proposed ESD protection scheme.

, ESD protection device between I/O pad and VDD ESD protection device between I/O pad and VSS Total CESD(fF)

Device CESD(fF) Device CESD(fF)

Receiver_3 DP(PJ = 35lm) 63.2 P-STSCR(W = 20lm) 64.7 127.9 Receiver_4 DP(PJ = 55lm) 117.9 P-STSCR(W = 20lm) 64.7 182.6 Receiver_5 DP(PJ = 35lm) 63.2 P-STSCR(W = 30lm) 90.1 153.3 Receiver_6 DP(PJ = 55lm) 117.9 P-STSCR(W = 30lm) 90.1 208 Receiver_7 DP(PJ = 35lm) 63.2 P-STSCR(W = 50lm) 140.9 204.1 Receiver_8 DP(PJ = 55lm) 117.9 P-STSCR(W = 50lm) 140.9 258.8

(9)

ESD level is improved to 4, 5, and 6.5 kV, respectively. Since the ESD protection device between the I/O pad and VDDis not changed

in the proposed ESD protection scheme, the positive-to-VDD

(PD-mode) ESD level does not have signiﬁcant difference under the same DPsize. In the interface circuit with the PMOS input stage,

the ND-mode may become another critical ESD-test pin combina-tion. The concept of using SCR to improve the PS-mode ESD robust-ness can be used to improve the ND-mode ESD robustrobust-ness. The ESD protection diode between VDDand the input pad can be replaced by

the SCR. In such an ESD protection scheme, the ND-mode ESD cur-rent path consists of only the SCR between VDDand the I/O pad.

Thus, the ND-mode ESD robustness is expected to be improved be-cause the voltage drop along the ND-mode ESD current path is reduced.

The double-diode ESD protection scheme has been applied to an IC product with a 2.5-Gb/s high-speed front-end interface fabri-cated in a 130-nm CMOS process. In this high-speed front-end chip, two P+/N-well diodes with 24.36-

l

m width and 2.74-

l

m length were used between the I/O pad and VDD, whereas two N+/

P-well diodes with 26.46-

l

m width and 4.84-

l

m length were used between the I/O pad and VSS. The total calculated parasitic

capaci-tance of the ESD protection diodes is 336 fF. This 2.5-Gb/s high-speed front-end interface passes 2-kV HBM and 200-V MM ESD tests, respectively. The measured eye diagram of this 2.5-Gb/s high-speed front-end interface circuit is shown inFig. 15. After the ESD protection devices are applied at the I/O pad, the measured eye diagram can be still satisfactory if the parasitic capacitance from the ESD protection devices is within the design budget. Fig. 14. Cross-sectional view of the ESD protection devices under the bond pad.

Table 8

HBM ESD robustness of the high-speed receiver interface circuits without and with double-diode ESD protection scheme.

PS-mode (kV) NS-mode (kV) PD-mode (kV) ND-mode (kV) Receive r_0 <0.5 <0.5 <0.5 <0.5

Receive r_1 2.5 2 2.5 2.5

Receive r_2 3 3 3.5 3

Table 9

HBM ESD robustness of the High-speed receiver interface circuits with proposed ESD protection scheme.

PS-mode (kV) NS-mode (kV) PD-mode (kV) ND-mode (kV)

Receiver_3 2.5 2.5 2.5 1.5 Receive r_4 4 2 4.5 2 Receive r_5 4 2.5 2.5 2.5 Receive r_6 5 3.5 4.5 2.5 Receive r_7 6 3.5 2.5 3 Receive r_8 6.5 3.5 4.5 3.5

(10)

5. Conclusion

In this work, the ESD protection design for high-speed I/O inter-face circuits in a 130-nm CMOS process is presented in detail. The parasitic capacitances and the ESD levels of the stand-alone ESD protection diodes were investigated in the beginning. To estimate the ESD robustness of general receiver and transmitter interface circuits with ESD protection, the receiver NMOS emulator and transmitter NMOS emulator with different ESD protection device dimensions were fabricated and their ESD levels were measured. Then, the double-diode ESD protection scheme was applied to a high-speed receiver interface circuit. To improve the ESD robust-ness under PS-mode ESD test, which is the most critical ESD-test pin combination for the double-diode ESD protection scheme, the ESD protection diode between the I/O pad and VSS was replaced

by the P-STSCR in the proposed design to reduce the clamping volt-age along the mode ESD current path can be reduced, so the PS-mode ESD level can be improved. Besides, the parasitic P-well/N-well diode in the SCR can provide the NS-mode ESD current path. Thus, SCR is the most promising ESD protection device in ESD pro-tection design with low-capacitance consideration. ESD test results have shown that the PS-mode ESD level is improved by using the proposed ESD protection scheme. With the ESD protection design methodology proposed in this work, the two most important requirements of ESD protection design for high-speed I/O interface circuits, which are high ESD robustness and low parasitic capaci-tance, can be met simultaneously.

Acknowledgments

The authors would like to thank Dr. Y.-K. Tseng and Mr. C. Huang of Faraday Technology Corporation, Hsinchu, Taiwan for their support to this study, and thank Mr. C.-Y. Lin for his technical discussion. The authors would also like to thank the Editor and his reviewers for their valuable suggestions to improve this paper. This work was supported in part by National Science Council (NSC), Tai-wan, under Contract of NSC 97-2221-E-009-170, and in part by Faraday Technology Corporation, Hsinchu, Taiwan.

References

[1] Voldman S. ESD circuits and devices. New York: Wiley; 2006.

[2] Han J, Choi B, Park K, Oh W, Park S. A 2.5 Gb/s ESD-protected dual-channel optical transceiver array. In: Proceedings of the IEEE Asian solid-state circuits conference; 2007. p. 156–9.

[3] Galal S, Razavi B. 40-Gb/s ampliﬁer and ESD protection circuit in 0.18-lm CMOS technology. IEEE J Solid-State Circ 2004;39(12):2389–96.

[4] Morishita Y. A PNP-triggered SCR with improved trigger techniques for high-speed I/O ESD protection in deep sub-micron CMOS LSIs. In: Proceedings of the EOS/ESD symposium; 2005. p. 400–6.

[5] Kang M, Song KW, Chung H, Kim J, Lee YT, Kim C. SCR-based ESD protection for high bandwidth DRAMs. In: Proceedings of the IEEE asian solid-state circuits conference; 2007. p. 208–11.

[6] Sarbishaei H, Lubana S, Semenov O, Sachdev M. A darlington-based SCR ESD protection device for high speed applications. In: Proceedings of the IEEE international reliability physics symposium; 2008. p. 633–4.

[7] Chun J-H, Murmann B. Analysis and measurement of signal distortion due to ESD protection circuits. IEEE J Solid-State Circ 2006;41(10):2354–8. [8] Sarbishaei H, Semenov O, Sachdev M. Optimizing circuit performance and ESD

protection for high-speed differential I/Os. In: Proceedings of the IEEE custom integrated circuits conference; 2007. p. 149–52.

[9] Ker M-D, Chen T-Y, Wu C-Y, Chang H-H. ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications. IEEE J Solid-State Circ 2000;35(8):1194–9.

[10] Hsiao YW, Ker MD, Chiu PY, Huang C, Tseng YK. ESD protection design for giga-Hz high-speed I/O interfaces in a 130-nm CMOS process. In: Proceedings of the IEEE international SOC conference; 2007. p. 277–80.

[11] Voldman S, Gross V, Hargrove M, Never J, Slinkman J, O’Boyle M, Scott T, Delecki J. A shallow trench isolation double-diode electrostatic discharge circuit and interaction with DRAM output circuitry. In: Proceedings of the EOS/ ESD symposium; 1992. p. 277–88.

[12] Voldman S, Gross V. Scaling, optimization, and design considerations of electrostatic discharge protection circuits in CMOS technology. In: Proceedings of the EOS/ESD symposium; 1993. p. 251–60.

[13] Bhatia K, Rosenbaum E. Layout guidelines for optimized ESD protection diodes. In: Proceedings of the EOS/ESD symposium; 2007. p. 19–27.

[14] Pozar D. Microwave engineering. 2nd ed. New York: Wiley; 1998.

[15] Maloney T, Khurana N. Transmission line pulsing techniques for circuit modeling of ESD phenomena, In: Proceedings of the EOS/ESD symposium; 1985. p. 49–54.

[16] ESD Association Standard Test Method ESD STM5.1-2001. Electrostatic discharge sensitivity testing—human body model (HBM)—component level, ESD Assoc; 2001.

[17] Ker MD. Whole-chip ESD protection design with efﬁcient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI. IEEE Trans Electron Dev 1999;46(1):173–83.

[18] Ker MD, Hsu KC. Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits. IEEE Trans Dev Mater Reliab 2005;5(2):235–49.

[19] Ker M-D, Hsu K-C. Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-lm CMOS process. IEEE Trans Electron Dev 2003;50(2):397–405.

[20] Ker M-D, Wu C-Y. Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method–Part I: theoretical derivation. IEEE Trans Electron Dev 1995;42(6):1141–8.

[21] ESD Association Standard Test Method ESD STM5.2-1999, for Electrostatic Discharge Sensitivity Testing—Machine Model (MM)—Component Level, ESD Assoc; 1999.

[22] Ker M-D, Peng J-J. Investigation on device characteristics of MOSFET transistor placed under bond pad for high-pin-count SOC applications. IEEE Trans Compon Packag Technol 2004;27(3):452–60. Sep.