Charge trapping induced drain-induced-barrier-lowering in HfO2/TiN p-channel
metal-oxide-semiconductor-field-effect-transistors under hot carrier stress
Wen-Hung Lo, Ting-Chang Chang, Jyun-Yu Tsai, Chih-Hao Dai, Ching-En Chen, Szu-Han Ho, Hua-Mao Chen,
Osbert Cheng, and Cheng-Tung Huang
Citation: Applied Physics Letters 100, 152102 (2012); doi: 10.1063/1.3697644 View online: http://dx.doi.org/10.1063/1.3697644
View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/100/15?ver=pdfcov
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This letter studies the channel hot carrier stress (CHCS) behaviors on high dielectric constant insulator and metal gate HfO2/TiN p-channel metal-oxide-semiconductor field effect transistors. It
can be found that the degradation is associated with electron trapping, resulting in Gmdecrease and
positive Vthshift. However, Vthunder saturation region shows an insignificant degradation during
stress. To compare that, the CHC-induced electron trapping induced DIBL is proposed to demonstrate the different behavior of Vthbetween linear and saturation region. The devices with
different channel length are used to evidence the trapping-induced DIBL behavior. VC 2012
American Institute of Physics. [http://dx.doi.org/10.1063/1.3697644]
The physical limitation of the silicon dioxide (SiO2) as
gate insulator has achieved the point where its thickness is approaching to a few atomic layers thick.1,2Below the physi-cal thickness 12 A˚ , the significant gate leakage current results in a volume active power consumption, leading a worse reli-ability of metal-oxide semiconductor field effect transistors (MOSFETs). To avoid this serious issue, high-k dielectrics have been introduced as hafnium (Hf)-base, zirconium, alu-minum oxides3–6and heavily investigated as a replacement for conventional SiO2gate insulator. However, high-k/metal
gate stack has to face many critical issues such as defects in high-k material which can lead to undesired transport through the dielectrics and trapping-induced instabilities.7–10 As MOSFETs scaling down, not only the BTI reliability at gate terminal but also hot carrier effect (HCE) which is asso-ciated with lateral electric field is important issue in MOS-FETs. Therefore, hot carrier effect in high-k/metal gate n-MOSFETs was still one of major device reliability con-cern. As is well known, under hot carrier injection, a high lateral electric field in pinch-off region accelerates the elec-trons sufficiently to gain enough energy to damage the drain side, resulting in the degradation of I-V characteristics. How-ever, most of the studies were concentrated on n-MOSFETs.11–14The degradation due to hot carrier effect in p-MOSFETs with high-k/metal gate stacks has not received as much attention. Therefore, the aim of this letter is to investigate the effects of channel hot carrier stress (CHCS) on HfO2/TiN p-MOSFETs. It was found that the
CHC-induced electron trapping dominates the degradation during stress, instead of interface states (Nit) creation, including Vth
shift and Gmdecrease. As the drain voltage (VD) was applied
at saturation region, there is no significant Vth shift during
stress. This behavior was doubted to result from trapping-induced drain-trapping-induced-barrier-lowering (DIBL). To explain this phenomenon, the device with different channel length (L) was introduced to support our model in this work.
The HfO2/TiN p-MOSFETs were studied in this paper
based on the high-performance 28-nm CMOS technology. Both devices were fabricated using a conventional self-aligned transistor flow through the gate first process. For the gate first process devices, 10 A˚ and 30 A˚ of high quality ther-mal oxide were, respectively, grown on a (100) Si substrate as buffer oxide layers. After standard cleaning procedures, 30 A˚ of HfO2 films were sequentially deposited by atomic layer
deposition. Next, 10 nm of TiN films were deposited by radio frequency physical vapor deposition, followed by poly-Si dep-osition as a low resistance gate electrode. The source/drain and poly-Si gate activation were performed at 1025C. In this study, the dimensions of the selected devices were 10 lm and 1 lm in width and length, respectively. The device with buffer thickness of 10 A˚ was subjected to the maximum substrate current of CHCS conditions with3.6 V drain voltage (VD).
The stress was briefly interrupted to measure the drain current-gate voltage (ID-VG) and substrate current-gate
volt-age (IB-VG) transfer characteristics. The gate induced drain
leakage (GIDL) current was defined under the VG¼ 0.5 V and
VD¼ 2.4 V. All experimental curves were measured using
an Agilient B1500 semiconductor parameter analyzer. Figure1shows the drain current (ID) curve versus gate
voltage (VG) and corresponding transconductance (Gm) of
HfO2/TiN p-MOSFETs under CHCS. The stress condition
VGwas selected at the maximum substrate current (IBmax) of
CHCS conditions while VD¼ 3.6 V. As the result, the
deg-radations on device during CHCS show decrease and posi-tive shift in transconductance (Gm) and threshold voltage
a)Author to whom correspondence should be addressed. Electronic mail: [email protected].
0003-6951/2012/100(15)/152102/4/$30.00 100, 152102-1 VC2012 American Institute of Physics
(Vth), respectively. And ID seems to be invariant at
VG¼ 1.6 V. Generally, the behavior of CHC effect on
n-MOSFETs has a cruel degradation at drain side due to impact ionization, decreasing in ID and Gm, but Vthshift is
insignificant unless Nitgeneration due to higher lateral
elec-tric field during CHCS, respectively.15 However, the Vth
shift toward positive direction is obtained under CHCS for high-k/Metal gate p-MOSFETs as shown in Fig.1. We sug-gest that Vthshift and decrease in Gmcould result from
elec-tron trapping in high-k layer during stress. When elecelec-tron- electron-hole pairs are produced by impact ionization, the stressing potential difference between gate and drain (VGD) makes
electron tend to inject to gate side, resulting in Vth shift.
Simultaneously, the field-effect mobility (Gm) is also
influ-enced by charge trapping, enhancing the channel scattering.16–18 However, Vth shift due to electron trapping
should make ID increasing, but the scattering reduces the
channel-mobility and decreases ID. Because those two causes
are antagonistic in IDthen resulting an invariant in ID.
Addi-tionally, the inset of Fig. 1 shows the ID-VG curve under
semi-logarithmic scale before and after CHCS. It can be found that the degradation of subthreshold slope (SS) is in-significant, illustrating the Nit is less. Therefore, this result
supports our assumption that the degradation of Vth is
induced by electron trapping in high-k layer located at drain side, instead of CHC-induced Nit. In order to solid the claim,
the effect of CHCS on the characteristics of IB-VG and
ID-VGmeasured at VD¼ 2.4 V are shown in Figure2(a). It
can be seen that the GIDL current and/or IB current at
VG > 0.5 V gradually increased during CHCS. This result implies that electrons are trapped in HfO2layer within drain
side to bend the band upward, therefore elongating the path of band to band tunneling during CHCS. Consequently, it can decrease the GIDL current and/or IB current at
VG> 0.5 V as I-V measurement. The corresponding energy
diagram is shown in the inset of Fig.2(a). Additionally, the C-V curve shows the occurrence of electron trapping near drain side as shown in Figure2(b). It can be seen that the ca-pacitance of gate terminal to drain terminal versus gate volt-age (CGD-VG) curve shifts in positive direction after CHCS,
which is consistent with the linear ID-VG result in Fig. 1.
However, the capacitance of gate terminal to source terminal versus gate voltage (CGS-VG) curve has on significant change
before and after stress, demonstrating the degradation is located at drain side. As well as, those experimental data are consistent with the suggestion of degradation which is domi-nated by CHC-induced electron trapping within drain side we declared. However, the occurrence of electron trapping at drain side still has insufficient justification to vary Vthwith
insignificant Nit generation. In order to comprehend how
comes the Vth shift under CHCS, we extract the degraded
tendency of Vth versus stress time in linear and saturation
region, which are defined Lin-Vthand Sat-Vth, respectively.
Figure 3shows the CHCS degradation of Lin-Vth and
Sat-Vth versus stress time. The Lin-Vth was extracted from
Gmmax and corresponding gate voltage at ID¼ 105 A is
selected for Sat-Vth. It can be observed that an obvious shift
on Lin-Vth, but Sat-Vth seem almost to be invariant under
CHCS. As the result, the mechanism is deduced by trapping-induced DIBL. As electron-hole pairs are created by CHC impact ionization, CHC-induced electrons could be trapped into HfO2layer within drain side, which has been evidenced
previously. As electron trapping occurs, it could bend chan-nel potential upward to help the linear VD (Lin-VD) to
FIG. 1. ID-VGand corresponding Gm-VG transfer characteristic curves of HfO2/TiN p-MOSFETs before and after stress. The inset shows the compari-son of subthreshold slope in log ID-VGunder CHCS and the energy diagram of CHC-induced trapping.
FIG. 2. (a) ID-VG and corresponding IB-VG transfer characteristic curves under VD¼ 2.4 V as a function of stress time during CHCS for devices. The inset shows the energy diagram of GIDL behavior under CHCS. (b) Normalized CGD-VG curve before and after CHCS and its measurement method. The inset shows Normalized CGS-VGcurve before and after CHCS and its measurement method.
152102-2 Lo et al. Appl. Phys. Lett. 100, 152102 (2012)
deplete channel, therefore lowering the source barrier as the illustration shown in the inset of Fig.3. Nevertheless, under saturation region, higher VD could deplete the
trapping-induced potential variation to dominate the lateral electric field in channel, expressing an invariant in Sat-Vthas shown
in the inset of Fig.3. This is because the original ID-VG
char-acteristic before stress has a conventional DIBL, resulting in a shift between Lin-Vthand Sat-Vthabout 30 mV (not shown
on here). If the Sat-Vthwill be changed, the more significant
trapping behavior which is greater than the influence of Sat-VDshould be required. According to our argument, the
devi-ces with long channel length were selected to prove the mechanism. Figure 4shows the Lin-Vth shift versus stress
time on HfO2/TiN p-MOSFETs under CHCS with different
L, including 1 lm and 10 lm. In order to keep the equivalent probability of trapping, the close impact ionization rate is considered by choosing similar IBmax to control the same
amount of electron-hole pairs. Due to the 10 mA IBmax, the
long channel devices L¼ 10 and 2 lm have a corresponding VDare4.5 V and 3.8 V, respectively. Figure4shows the
Lin-Vth shift under CHCS for HfO2/TiN p-MOSFETs with
different channel length L. It can be found that the Lin-Vth
has a positive shift on all the devices, regardless of different channel length. However, the Lin-Vth shift has a negative
related to channel length L. The device with the longest channel corresponds to the most insignificant shift under CHCS, since the behavior of trapping-induced DIBL is sup-pressed by long channel device. This is because the potential variation due to electron trapping is growingly hard to extend to source side as channel length increases under Lin-VD.
Therefore, the Lin-Vthon long channel device has an
insig-nificant degradation which is consistent with the model we supported. Consequently, the Lin-Vthshift on HfO2/TiN
p-channel MOSFETs under CHCS results from electron trap-ping has been generalized in this work.
This letter studies the CHCS behaviors on HfO2/TiN
p-channel MOSFETs. We found that the degradations result from electron trapping, leading Gm decrease and positive
Lin-Vthshift, but Sat-Vthshows an insignificant degradation
during stress. This dissimilar behavior of Vthis attributed to
CHC-induced electron trapping induced DIBL. The devices with different channel length are introduced into evidence of trapping-induced DIBL behavior. As the result, the slightest Lin-Vth shift is corresponding to the HfO2/TiN p-channe
MOSFET with the longest channel length.
Part of this work was performed at United Microelec-tronics. The work was supported by the National Science Council under Contract Corporation NSC100-2120-M110-003.
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FIG. 3. The CHCS-induced Lin-Vth and Sat-Vth shift for HfO2/TiN p-MOSFETs with L¼ 1 lm. The inset shows the trapping-induced DIBL mechanism due to CHC-induced electron-trapping under linear and satura-tion region.
FIG. 4. The relation of Lin-Vthshift versus channel length for HfO2/TiN p-MOSFETs under CHCS. The inset shows the Lin-Vthshift versus stress time for HfO2/TiN p-MOSFETs with L¼ 1 lm, 2 lm and 10 lm under CHCS and the illustration of trapping-induced DIBL behavior for long channel devices.
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