返馳式轉換器之數位式初級側感測控制

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國立交通大學

電控工程研究所

碩士論文

返馳式轉換器之數位式初級側感測控制

Digital Primary-Side Sensing Control for Flyback

Converters

研究生：張哲瑋

指導教授：鄒應嶼博士

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返馳式轉換器之數位式初級側感測控制

Digital Primary-Side Sensing Control for Flyback

Converters

研究生：張哲瑋 Student: Che-Wei Chang

指導教授：鄒應嶼博士 Advisor: Dr. Ying-Yu Tzou

國立交通大學

電控工程研究所

碩士論文

A Thesis

Submitted to Institute of Electrical and Control Engineering College of Electrical Engineering

National Chiao-Tung University in Partial Fulfillment of the Requirements

for the Degree of Master in

Electrical and Control Engineering October 2009

Hsinchu, Taiwan, Republic of China

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返馳式轉換器之數位式初級側感測控制

研究生：張哲瑋指導教授：鄒應嶼博士國立交通大學電控工程研究所 中文摘要 本論文針對返馳式轉換器之數位式初級側感測控制方法進行設計，可用於不連續導通模式之直流返馳式轉換器以及不連續導通模式、具功率因數修正之返馳式整流器。初級側感測方法可藉由輔助線圈來達到輸出電壓或電流的控制。然而，根據初級側感測誤差的分析，感測電壓會受到漏電感、線阻及次級側二極體壓降影響，因此，感測電壓只能達到有限的精準度。在不連續導通模式之直流返馳式轉換器的應用中，感測誤差可以藉由取樣時間調變來加以改善。透過取樣時間調變的方法，當負載大小從 20%變化至 100%時，輸出電壓在穩態時僅有 1%的誤差且電壓壓降於切載時亦可控制在額定輸出電壓的 4.7%。此外，將初級側感測方法用於不連續導通模式、具功率因數修正之返馳式整流器時，感測電壓在整流後輸入電壓接近零交越點時，因可供取樣的時間很短，不易取得正確的輸出電壓回授訊號。因此，採用多模式的控制演算法來克服此問題。當系統在整流後輸入電壓接近零交越點時，採用開迴路控制，而在其餘時間則採用預設的閉迴路控制。藉由此方法，輸入電流的總諧波失真在額定負載時僅有 4.5%。在本論文中，利用一顆德州儀器公司的數位訊號處理晶片 TMS320F2812 來實現初級側感測控制方法。

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Digital Primary-Side Sensing Control for Flyback Converters

Student: Che-Wei Chang Advisor: Dr. Ying-Yu Tzou

Institute of Electrical and Control Engineering National Chiao Tung University

Abstract

This thesis presents the design and realization of primary-side sensing (PSS) technique for discontinuous-conduction-mode (DCM) DC-DC flyback converters or flyback rectifiers with power factor correction (PFC). PSS technique can be used for the output voltage or current regulation by employing an auxiliary winding. However, by analyzing the primary-side sensing error, the sensed voltage from the auxiliary winding may be corrupted by switching noise due to leakage inductance, winding resistance, and the voltage drop of the secondary diode, therefore the sensed voltage can only achieve limited accuracy. The sensing error can be improved by sampling instant modulation for DCM DC-DC flyback converters. The voltage regulation has only 1% deviation and the voltage drop is only 4.7% of the nominal output voltage when the load power is from 20% to 100%. When utilizing PSS technique for DCM PFC flyback rectifiers, the sensed voltage is difficult to be obtained at the neighborhood of zero crossing of the rectified input voltage. Therefore, a multimode control algorithm is implemented to overcome this problem. The system is under open-loop control at the neighborhood of zero crossing and closed-loop control when the correct sensed voltage is able to be obtained. By this method, the total harmonic distortion (THD) of the ac line current is only 4.5% at the rated output power. In this thesis, PSS technique is realized by a digital signal processor (DSP), TMS320F2812 from Texas Instrument (TI).

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誌謝

首先我要特別感謝我的老師鄒應嶼教授這兩年來的細心指導，提供了良好的研究環境及實驗器材，讓我在攻讀研究所期間培養解決問題之能力。此外，亦感謝老師讓我參與研究計畫，藉由和業界工程師的互動而更深刻地清楚自己所欠缺的態度以及企圖心。感謝口試委員潘晴財教授及曾仲熙教授在口試時所給予的寶貴建議與鼓勵。感謝育宗學長的帶領與指教，幫助我解決研究上碰到的問題，無論在於理論或實務方面都獲益良多。感謝同學茗皓、煒超、宗翰在學習過程中互相鼓勵打氣，分享日常生活的點點滴滴。感謝學弟彥勳、(康)哲瑋、甫尊、智偉、政江及建成，總是在我情緒低落時給予關懷，尤其感謝彥勳協助我解決研究上的問題。另外，亦要感謝袈瀚時常以不同的觀點分享工作經驗與生活體驗。祝各位在研究領域中都能有所成就，也歡迎在我畢業後找我討論切磋。感謝月貴細心地協助處理瑣碎的行政工作。特別感謝我的父母及弟弟給我ㄧ個幸福的家庭，讓我在外面累了總會有個棲身的地方，拋開外在紛擾得以重新獲得力量，面對未來的挑戰。

僅以此論文獻給所有關心我的長輩、親戚與朋友…

張哲瑋 2009 秋天於新竹交大

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LIST OF TABLES

2.1 Constraints for the Power Components. ... 15 4.1 Parameters of the Small-Signal DCM Switch Model... 29 5.1 Fundamental Components of the AC Input Currents of Three Basic

Topologies ... 52 5.2 Parameters of the Small-Signal AC Model Parameters ... 58

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LIST OF FIGURES

1.1 Extract the output voltage from the voltage across the switch. ... 2

1.2 Extract the output voltage from the auxiliary winding... 3

2.1 Procedure to derive a flyback converter from a buck-boost converter: (a) buck-boost converter referenced to the input ground, (b) buck-boost converter referenced to the input rail, (c) flyback converter. ...6

2.2 (a) During the on time, the output capacitor supplies the load on its own. (b) During the off time, the voltage across the switch is the input voltage plus the output voltage multiplied by the turns ratio nps. (c) When the magnetizing inductor is reset, the output capacitor supplies the load on its own. ... 8

2.3 Current waveforms of the flyback converter in DCM... 8

2.4 Circuit schematic with parasitic elements after the switch is turned off. ...12

2.5 Effect of the ESR and waveforms to estimate the value of the ESR...12

2.6 Typical waveforms of flyback converters in DCM with parasitic elements. ... 13

2.7 Typical clamping network made by RCD circuit. ... 14

3.1 Ideal flyback converter with PSS: (a) Schematic, (b) Waveforms... 17

3.2 (a) Proposed flyback converter with PSS. (b) Important waveforms through one switching period... 17

3.3 Equivalent circuits in interval (a)T1, (b)T2, (c)T3. ... 19

3.4 vaux to vo ratio versus Ks assuming Ns = Na. ... 21

3.5 Equivalent circuit in interval T3 considering the forward-biased voltage drop vD and the winding resistance Rs. ... 21

3.6 Simulation results of flyback converter to verify the relationship between the output voltage and the estimated output voltage. ... 22

3.7 Mechanism to set the sampling instant... 25

4.1 Procedure to define the continuous time equivalent block diagram... 27

4.2 Small-signal model of the DCM equivalent buck-boost converter from the flyback converter. ... 28

4.3 Frequency response of the control-to-output transfer function by simulation and calculation...31

4.4 Feedback path for PSS...32

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4.6 Frequency response of the exponential delay term in the DPWM model. ... 36

4.7 Analog PI and digital PI controllers. ... 38

4.8 Constant sampling instant makes the sensed voltages different between two different load conditions...40

4.9 Concept of sampling instant modulation. ... 41

4.10 Flowchart of main program. ... 42

4.11 Flowchart of interrupt service routine program... 42

4.12 Timing diagram of PSS algorithm in the DSP chip. ... 43

4.13 Timing diagram of PSS algorithm in the DSP chip. ... 43

4.13 Experimental setup for the DCM flyback converter with PSS... 44

4.14 Effective turns ratio from the auxiliary winding to the secondary winding... 45

4.15 Key waveforms with constant sampling instant (a) in full-load condition, (b) in light-load (20%) condition. ... 45

4.16 Key waveforms with sampling instant modulation (a) in full-load condition, (b) in light-load (20%) condition... 45

4.17 Comparisons of voltage regulation with and without sampling instant modulation. ... 46

4.18 Load transient response from 20 % to 100 % output power without sampling instant modulation. ... 48

4.19 Load transient response from 20 % to 100 % output power with sampling instant modulation. ... 48

4.20 (a) Experimental results of the output voltage and the sensed voltage by PSS. (b) Relation of the output voltage before the LC filter versus the sensed voltage. (c) Relation of the output voltage after the LC filter versus the sensed voltage...49

5.1 A flyback rectifier in DCM: (a) Schematic, (b) Waveforms... 52

5.2 System schematics of a DCM PFC flyback rectifier with PSS. ... 53

5.3 Loss-free resistor model for an ideal rectifier. ... 54

5.4 Steps in the derivation of dc and small-signal ac model, suitable for design of the output voltage feedback loop: (a) Basic loss-free resistor model, with switching harmonics removed, but 2ωline and dc components retained. (b) DC model, with 2ωline components removed. (c) Small-signal ac model. ...57

5.5 Timing plot of intervals T1, T2, T3, and the sampling instant. ... 61

5.6 Definition of multimode digital control. ... 61

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5.8 Voltage on the auxiliary winding: (a) when the ac line voltage is maximum, (b) when the ac line voltage is close to zero... 64 5.9 Simulation results to show the mode switching (a) in full-load condition, (b)

in half-load condition. ... 64 5.10 Experimental results to show the mode switching (a) in full-load condition,

(b) in half-load condition... 65 5.11 AC line voltage and current of the designed flyback rectifier (a) in full-load

condition, (b) in half-load condition...65 5.12 Simulation waveforms of load transient response of the designed PFC

flyback rectifier from half load to full load. ... 66 5.13 Experimental waveforms of load transient response of the designed PFC

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Chapter 1 Introduction

1.1 R

ESEARCH

B

ACKGROUND AND

R

ECENT

D

EVELOPMENT

Flyback converter topology gets its wide applications in low-power and low-cost isolated switching power supplies due to its low component counts without a secondary output filter inductor. Conventional flyback converters utilize an error amplifier and an opto-coupler to implement the voltage feedback compensation and galvanic isolation.

Low-cost opto-couplers suffer from the current transfer ratio (CTR) degradation due to temperature rise. This makes a serious limitation on operating temperature for flyback converters. The elimination of the opto-coupler provides significant advantages such as higher power density, cost down, and lower standby power. Therefore, primary-side sensing (PSS) technique, which senses the output voltage from the primary or auxiliary winding of the transformer without using the opto-coupling circuit, becomes an important issue for the development of more sophisticated flyback control ICs.

Another motivation to develop PSS technique is that there is a low frequency pole at 20-30 kHz from the opto-coupler. This pole complicates the feedback loop design and limits the crossover frequency. Recently, in order to get a higher bandwidth in voltage loop, engineers may implement secondary-side control, which places the controller at the secondary side and transmits the pulse-width-modulation (PWM) signal through a pulse transformer or a high-speed photodetector to eliminate the low frequency pole, but the start-up circuit for the controller at the secondary side needs the electrical isolation from the input power [1]. Hence,

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PSS technique combines the advantages of primary-side control and secondary-side control to become an attractive choice.

PSS technique can extract the output voltage from the primary side because the output voltage appears on the primary winding during the power switch off state [2]-[6].

. o s p in DS v N N v v = + (1-1)

The voltage across the switch contains the information of the output voltage during off state as shown in (1-1). With the AC line input, this method may require the implementation of high voltage sensing circuits and suffer from coupling noises due to primary leakage inductance. The schematic diagram to extract the output voltage from the voltage across the switch is shown in Fig. 1.1.

Another approach is to adopt an additional auxiliary winding to detect the output voltage [7]-[11]. . o s a aux v N N v = (1-2)

This auxiliary winding can be used for both power supplying and voltage sensing and it provides advantages such as low-voltage IC manufacturing process for the implementation of CMOS controller for cost reduction, better winding mechanism for the reduction of coupling noises, lower standby power consumption using the same IC manufacturing process. The schematic diagram to extract the output voltage from the auxiliary winding is shown in Fig. 1.2. This thesis focuses on the second approach which senses the output voltage from the auxiliary winding.

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o C_o C R_L v_o + − in v + − p N N_s s i p i DS v + − Signal Extraction and Control Algorithm o C_o C R_L v_o + − in v + − p N N_s s i p i DS v + − Signal Extraction and Control Algorithm

Fig. 1.1. Extract the output voltage from the voltage across the switch.

o C_o C R_L v_o Signal Extraction and Control Algorithm aux v + − + − in v + − p N N_s a N s i p i a i cc v + − o C_o C R_L v_o Signal Extraction and Control Algorithm aux v + − + − in v + − p N N_s a N s i p i a i cc v + −

Fig. 1.2. Extract the output voltage from the auxiliary winding.

1.2 R

ESEARCH

M

OTIVATION AND

O

BJECTIVES

The accuracy of sensing output voltage indirectly from the auxiliary winding will be influenced by practical factors, such as cross coupling effect, voltage drop across the secondary diode, and switching oscillations induced by leakage inductance, magnetization inductance, and the output junction capacitance of the switching device. Commercial flyback transformers must provide galvanic isolation between primary and secondary in accordance with the regulatory agencies of the intended market, such as IEC950 in Europe and UL1950

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in the U.S. Different approaches can be adopted to meet the required safety regulations. Cores and bobbins are usually selected large enough meet the creepage distance requirement as well as to maintain transformer coupling and reduce leakage inductance. Cross coupling between transformer windings will corrupt accuracy of the sensing voltage for output voltage detection. The cross regulation in multiple-output flyback converters is mainly affected by leakage inductances of the transformers and this effect can be reduced by proper winding arrangements of the transformers [12].

Analytical model and small-signal analysis for cross regulation of a flyback converter with multiple outputs have been developed in [13]-[14]. The auxiliary winding is identical to an output winding with very low power consumption and the analytical model can be used for the analysis of the coupling effect between the main output voltage and the voltage of the auxiliary winding. This thesis makes an error analysis of PSS technique due to the leakage inductance and other key parameters when applying to flyback converters, and presents the design and realization of PSS technique for discontinuous-conduction-mode (DCM) DC-DC flyback converters or flyback rectifiers with power factor correction (PFC).

1.3 T

HESIS

O

RGANIZATIONS

The thesis is organized as follows. The fundamentals of flyback converters are introduced in Chapter 2, and the effects with parasitic elements and the determination of components for flyback converters are also mentioned.

In Chapter 3, a proposed digital PSS technique is presented and the PSS error is analyzed in detail. In addition, the determination of the sampling instant is also described and implemented by a fixed-point digital-signal processor (DSP), TMS320F2812.

In Chapter 4, a DCM DC-DC flyback converter with the proposed PSS technique is developed to show the usability of PSS technique. The dynamic model of this system is

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derived to design the digital voltage controller, and PSS control algorithm is designed with sampling instant modulation to reduce the effect of the sensing error. The experimental results are also shown in this chapter to verify PSS technique for DCM DC-DC flyback converters.

In Chapter 5, the proposed PSS technique can be extended to control a DCM PFC flyback rectifier. At the beginning of this chapter, it explains the self PFC property for flyback rectifiers operating in DCM, and then, derives the dynamic model for DCM flyback rectifiers. The PSS control algorithm is modified to adapt the conditions with a rectified input voltage. The control algorithm is separated into two modes to overcome the problem for sampling the sensed voltage at the neighborhood of zero crossing. The experimental results are also shown in this chapter to verify PSS technique for DCM PFC flyback rectifiers. Finally, Some concluding remarks and suggested future works related to this research are summarized and discussed in Chapter 6.

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Chapter 2 Fundamentals of Flyback Converters

A flyback converter is also called “isolated buck-boost converter” because it is derived from a buck-boost converter. The buck-boost converter shown in Fig. 2.1(a) delivers a negative output voltage referenced to the input ground without isolation. A negative output voltage is inconvenient to implement some applications, but the property of buck-boost converters that the output voltage can be higher or lower than the input voltage is necessary to the applications which have wide input ranges. By swapping the positions of the inductor and the switch in Fig. 2.1(a), a similar arrangement is kept in Fig. 2.1(b), but the output voltage is referenced to the input rail. Then, replacing the inductor with an air-gapped transformer, we obtain an isolated flyback converter shown in Fig. 2.1(c). The flyback transformer configuration helps to adopt polarity by playing on the winding dot and the diode orientation, so the polarity of the output voltage on the flyback converter can be either positive or negative.

in v o v + − in v o v + − vin o v + − (a) (b) in v p N s N o v + − in v p N s N o v + − (c)

Fig. 2.1. Procedure to derive a flyback converter from a boost converter: (a) buck-boost converter referenced to the input ground, (b) buck-buck-boost converter referenced to the input rail, (c) flyback converter.

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2.1 O

PERATING

P

RINCIPLE OF

DCM

F

LYBACK

C

ONVERTERS

Fig. 2.2(a) portrays an ideal flyback converter without parasitic elements when the switch is closed. During this time, the voltage across the magnetizing inductance LM is equal to the input voltage vin (neglect the voltage drop across the switch). Then, the inductor current increases at a rate defined by

. M in on L v S = (2-1)

The peak inverse voltage (PIV) on the secondary diode during the on time is

o ps in v n v + = PIV (2-2)

where nps =Np/Ns. Np and Ns are the turns of the primary winding and the secondary winding, respectively. Fig. 2.2(b) portrays an ideal flyback converter when the switch is open. During this time, the voltage across the magnetizing inductance LM is equal to the output voltage vo multiplied by the turns ratio nps from the primary winding to the secondary winding. Then, the inductor current decreases at a rate defined by . M o ps off L v n S =− (2-3)

Fig. 2.2(c) portrays an ideal flyback converter when the switch is open and the magnetizing inductor is reset.

In this thesis, the flyback converter always operates in DCM, so the following discussion focuses on the properties of flyback converters in DCM. When the flyback converter operates in DCM, there are three states defined as on state, off state, and reset state. The energy stored in the flyback transformer is zero in reset state. The waveforms of the primary current ip, the secondary current is, and the magnetizing current iM are shown in Fig. 2.3. The property of

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voltage conversion is derived firstly, and the waveforms with parasitic elements in DCM are shown. Then, the peak value of the drain-to-source voltage of the switch during the off state is calculated, so a clamping network is necessary to protect the switch against the breakdown voltage. Finally, an RCD clamping network is designed.

(b) in v p N N_s o v + − M L o C R_L (c) in v p N N_s o v + − M L o C R_L (a) in v p N N_s o v + − M L o C R_L p i is i_p i_p s i s i M i iM iM

Fig. 2.2. (a) During the on time, the output capacitor supplies the load on its own. (b) During the off time, the voltage across the switch is the input voltage plus the output voltage multiplied by the turns ratio nps. (c) When the magnetizing inductor is reset, the output

capacitor supplies the load on its own.

p

i

s

i

M

i

s

DT

T

_s on

S

off

S

ˆ

M

i

M p

i

ˆ

=

ˆ

p ps s

n

i

ˆ

=

ˆ

on off reset

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2.1.1 Voltage Conversion Ratio in DCM

To derive the voltage conversion ratio in DCM, the procedure is easy with an assumption that the input power Pin is equal to the output power Po. The input power is derived from the primary current as s M in s p M in D T L v f i L P 2 2 2 2 ˆ 2 1 ₌ = (2-4)

where D is the duty ratio in steady state and Ts is the switching period. The output power can be expressed by the output voltage and the load resistance RL as

. 2 L o o R v P = (2-5)

Combining (2-4) and (2-5), the voltage conversion ratio in DCM is derived as

K D L T R D v v M s L in o = = 2 (2-6) where s L M T R L K = 2 .

From (2-6), it reveals a fact that the turns ratio nps does not affect the voltage conversion ratio when the flyback converter operates in DCM. However, the turns ratio nps actually affects the critical magnetizing inductance Lcrit, which determines the flyback converter operates in continuous-conduction mode (CCM) or DCM. The critical magnetizing inductance Lcrit is determined by

. 1 2 2 2 ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ + = in o ps ps s L crit v v n n T R L (2-7)

2.1.2 Effects of Parasitic Elements in DCM

In the previous section, the considered flyback converter is ideal. There are some important parasitic elements such as the leakage inductor in the primary winding, the junction capacitor of the switch, and the equivalent series resistor (ESR) of the output capacitor. The

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most important waveform is the voltage on the switch. Because of the leakage inductance in the primary winding and the junction capacitor of the switch, the voltage on the switch will oscillate in off state and may destroy the switch. The voltage on the switch in off state with parasitic elements can be derived by solving the differential equations as follows

) ( ) ( ) ( ) ( ) ( t v v v n v dt t di L t i dt t dv C DS D o ps in p lkp p DS DS − + + = = (2-8)

where CDS is the junction capacitance of the switch, Llkp is the leakage inductance in the primary winding, vD is the voltage drop of the secondary diode, and vDS is the voltage on the switch. The relative circuit schematic is shown in Fig. 2.4. To solve the ODE in (2-8), the initial conditions should be obtained, which are

. ˆ ) 0 ( ) 0 ( ) ( ) 0 ( DS p DS p DS D o ps in DS C i C i v v v n v v = = + + = (2-9)

The voltage on the switch in off state can be obtained from (2-8) with initial conditions in (2-9) as ) sin( ˆ ) ( ) (t v n v v i Z t vDS = in + ps o + D + p p ωlk (2-10)

where Zp is the characteristic impedance and ωlk is the resonant frequency of LlkpCDS circuit defined as . 1 DS lkp lk DS lkp p C L C L Z = = ω (2-11)

The peak value of the voltage on the switch is estimated from (2-10) as . ˆ ) ( max , in ps o D p p DS v n v v i Z v = + + + (2-12)

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when designing a flyback converter. The design of clamping network is discussed in section 2.2.

Another effect caused by the ESR of the output capacitor appears on the output voltage. If the converter operates in DCM, this effect is more obvious because the peak of the secondary current is generally higher than the condition in CCM. The AC component of the secondary current will flow through the output capacitor and cause a voltage ripple on the output voltage. The relative waveforms are shown in Fig. 2.5. The ESR rc of the output capacitor can be estimated as

o s esr c I i V r − = ˆ (2-13)

where Vesr is the peak-to-peak value observed on the output voltage ripple. The output voltage ripple has two components. One is caused by the discharge of the output capacitor and the other is caused by the ESR. The ripple caused by the ESR may be a problem to violet the specification although the output capacitor is selected very large. Therefore, in some cases, an output LC filter is necessary to improve the situation.

If more accurate values of the parasitic elements are needed to know, observing the drain-source waveforms of a flyback converter can teach designer a lot. A drain-drain-source waveform in DCM is shown in Fig. 2.6. To determine the parasitic elements, there are several equations to use such as lkp M in on L L v S + = (2-14) DS lkp lk C L f π 2 1 = (2-15) . ) ( 2 1 DS lkp M DCM C L L f + = π (2-16)

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Solving these equations gives the parasitic elements as 2 2 4 _in _DCMπ on DS f v S C = (2-17) DS lk lkp C f L ₂ ₂ 4 1 π = (2-18) . on lkp on in M S L S v L = − (2-19) in v M L p i lkp L DS C ( ) ps o D n v +v

Appears when the sec. diode conducts

Fig. 2.4. Circuit schematic with parasitic elements after the switch is turned off.

L R vo + − s N is c r o I s i s iˆ c i o s I iˆ − on off reset o I o C i_c esr V , o ripple v ( ) d t

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DS

v

p

i

d

on

S

lk

f

DCM

f

on off reset

Fig. 2.6. Typical waveforms of flyback converters in DCM with parasitic elements.

2.2 D

ETERMINATION OF

C

OMPONENTS FOR

F

LYBACK

C

ONVERTERS

2.2.1 Clamping Network

The clamping network role shown in Fig. 2.7 is to prevent the drain-to-source voltage exceeding the breakdown voltage of a given MOSFET. In general, the breakdown voltage is selected up to 600 V or higher in flyback applications. Firstly, we need to determine the clamping voltage by the equation as follows

in D DSS

c BV k v

v = − (2-20)

where BVDSS is the breakdown voltage of a given MOSFET and the parameter kD is a derating factor to reserve a safety margin for design. Moreover, the clamping voltage must be higher than the reflected voltage nps(vo + vD) to authorize the quick leakage term reset in the primary-side leakage inductor. Experience shows that a proper clamping voltage selected as

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o C_o C R_L v_o + − in v p N N_s s i p i lkp L M L + c v − M v + − Duty sn D sn R sn C Clamping network

Fig. 2.7. Typical clamping network made by RCD circuit.

) ( _o _D ps c c k n v v v = + (2-21)

where the parameter kc is good to be selected between 1.3 to 2. Then, the resistance Rsn and the capacitance Csn can be determined by

2 2 ( ) ˆ c c ps o D s sn lkp p v v n v v T R L i ⎡ − + ⎤ ⎣ ⎦ = (2-22) v R T v C sn s c sn Δ = (2-23)

where Δv is the voltage ripple on the clamping capacitor, which can be selected roughly 20% of the clamping voltage. A more detailed design analysis of the RCD snubber can be found in [15].

2.2.2 Power Stage

There are some important components to design for a flyback converter such as the turns ratio from the primary side to the secondary side, the magnetizing inductance, the output capacitance, the power switch, and the secondary diode. The turns ratio can be derived from (2-21) yielding . ) ( _o _D c c ps v v k v n + = (2-24)

The magnetizing inductance is determined by the operating mode and (2-7). For operating in DCM, the magnetizing should be lower than the value in (2-7). The other

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important constraints for the power switch, the output capacitor, and the secondary diode are shown in Table 2.1.

TABLE2.1

CONSTRAINTS FOR THE POWER COMPONENTS

MOSFET Breakdown voltage BVDSS >vin +nps(vo +vD)+vc RMS current in DCM 3 ˆ D i I_rms = _p Secondary diode Peak repetitive reverse voltage

ps in o RRM n v v V > +

Continuous current IF,avg =Io

Output capacitor Capacitance o s o o v T I C Δ =

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Chapter 3 Digital Primary-Side Sensing (PSS) Control

Technique

Fig. 3.1(a) shows the schematic of an ideal flyback converter with PSS, where vin is the input voltage, vo is the output voltage, vaux is the voltage on the auxiliary winding, and Np, Ns, and Na are the turns of each winding respectively.

For an ideal system, assume that all leakage inductances can be ignored and the forward-biased voltage drop of the secondary diode is much smaller than vo. vaux includes the information of vo when the power MOSFET is in its off state. If the controller samples vaux in off state before the current is decreases to zero, the relation between vo and vaux can be ideally expressed by . o s a aux v N N v = (3-1)

The waveform of vaux is shown in Fig. 3.1(b).

A Flyback converter stores energy in its transformer when the switch is on and releases this stored energy to its secondary winding and auxiliary winding when the switch is turned off. Because of very low power dissipation of the controller compared to the output load, it can be assumed that the current is flowing through the secondary diode is much higher than the current ia flowing through the auxiliary diode. Fig. 3.2(a) is the proposed system in this paper, where LM is the magnetizing inductance of the transformer and Llkp, Llks, Llka are corresponding to the leakage inductances in the primary winding, secondary winding and auxiliary winding, respectively. In practice, the voltage on the auxiliary winding imperfectly couples to the output voltage. It will be influenced by leakage inductances, voltage drop on

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the secondary diode, and the winding resistance in the secondary winding. o C_o C R_L v_o Signal Extraction And Control algorithm aux v + − + − in v + − p N N_s a N s i p i a i o C_o C R_L v_o Signal Extraction And Control algorithm aux v + − + − in v + − p N N_s a N s i p i a i

(a)

aux v p i s i a o s N v N a in p N v N − aux v p i s i a o s N v N a in p N v N −

(b)

Fig. 3.1. Ideal flyback converter with PSS (a) Schematic, (b) Waveforms.

o Co C RL vo + − aux v+ − in v + − p N N_s a N s i p i lks L lkp L M L lka L + c v − cc V M v + − d + − sense v + − 1 ac R 2 ac R a i A D − ( ) C z + − + − duty V delay V vref ADC V Gate Drive PWM Generator Sampling instant TMS320F2812 fb v M v M i c i a i′ s i′ 1 M v 2 M v 3 M v ˆ p i ˆ a i 1 ˆ s i 2 ˆ s i 1 t t₂ t₃ t₄ 1 T T₂ T₃ on off (a) (b) o Co C RL vo + − aux v+ − in v + − p N N_s a N s i p i lks L lkp L M L lka L + c v − cc V M v + − d + − sense v + − 1 ac R 2 ac R a i A D A D − ( ) C z + − + − duty V delay V vref ADC V Gate Drive PWM Generator Sampling instant TMS320F2812 fb v M v M i c i a i′ s i′ 1 M v 2 M v 3 M v ˆ p i ˆ a i 1 ˆ s i 2 ˆ s i 1 t t₂ t₃ t₄ 1 T T₂ T₃ on off M v M i c i a i′ s i′ 1 M v 2 M v 3 M v ˆ p i ˆ a i 1 ˆ s i 2 ˆ s i 1 t t₂ t₃ t₄ 1 T T₂ T₃ on off (a) (b)

Fig. 3.2. (a) Proposed flyback converter with PSS. (b) Important waveforms through one switching period.

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3.1 P

RIMARY

-S

IDE

S

ENSING

E

RROR

A

NALYSIS

In order to analyze the sensing error by primary-side sensing, according to [14], convert the components at the secondary side and the auxiliary side to the primary side of the transformer. All parameters converted to the primary side are noted with prime, x′. At the beginning of the error analysis, define three intervals T1, T2, and T3 which are shown in Fig. 3.2(b). The equivalent circuits are derived to match the conditions when the switch is turned off as shown in Fig. 3.3.

For simplicity, assume all capacitors are large enough so that the voltages on them are constant in each interval. When the switch is turned off at the beginning of interval T1, the equivalent circuit is shown as Fig. 3.3(a). By Kirchhoff’s current law (KCL), the sum of current at node M is zero,

. a s c M i i i i = + ′ + ′ (3-2) Differentiating of (3-2) yields . dt i d dt i d dt di dt di_M _c _s _a′ + ′ + = (3-3)

Substitution of the current changing rates of iM, ic, i′ , and s i′ into (3-3) gives a

. 1 1 1 1 lka aux M lks o M lkp c M M M L v v L v v L v v L v ′ ′ − + ′ ′ − + − = − (3-4)

Solving (3-4) for vM1 yields

a s p aux a o s c p M K K K v K v K v K v + + + ′ + ′ + = 1 1 (3-5)

where K_p =L_M L_lkp, K_s =L_M L_lks′ , and K_a = L_M L_lka′ . When the current ic flowing into the RCD snubber decreases to zero, the system enters into interval T2. The equivalent circuit is shown as Fig. 3.3(b). Then,

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lkp L lka L′ lks L′ M L v′o + − c v + − aux v′ + − 1 M v + − RCD snubber lka L′ lks L′ M L v′o + − aux v′ + − 2 M v + − lks L′ M L v′o + − 3 M v + − (a) (b) (c) s i′ a i′ c i M i s i′ a i′ M i s i′ lka L′ aux v′ + − a i′ M i M M M

Fig. 3.3. Equivalent circuits in interval (a)T1, (b)T2, (c)T3.

. 1 2 a s aux a o s M K K v K v K v + + ′ + ′ = (3-6)

When the auxiliary diode is off, the system enters into interval T3. The equivalent circuit is shown as Fig. 3.3(c). By the same procedure, solving vM3 yields

. 1 3 s o s M K v K v + ′ = (3-7)

Comparing with (3-5), (3-6), and (3-7), vM3 is a simple function of Ks and vaux couples to vM3 perfectly because ia is equal to zero in interval T3. If the controller samples the voltage on the auxiliary winding in interval T3, vaux can be expressed as

. 1 1 3 o s s s a s o s p a M p a aux p a aux v K K N N K v K N N v N N v N N v + = + ′ = = ′ = (3-8)

Ks is infinite for an ideal system, so that the above equation is identical to (3-1). From (3-8), it shows that the accuracy of primary-side sensing is only influenced by the leakage inductance in the secondary winding when the controller samples vaux in interval T3. Fig. 3.4 shows vaux to vo ratio versus Ks assuming Ns = Na, where circles are the results calculated by (3-8) and stars are the results simulated by PSIM 6.0 software. This figure

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indicates that vaux to vo ratio is relative to the leakage inductance in the secondary winding, so we define an effective turn ratio as follows

. 1 _s a s s eff N N K K n + = (3-9)

Equation (3-9) makes the relationship between vo and vaux simple. In order to modify the effect caused by the leakage inductance in the secondary winding, measuring the effective turn ratio is necessary when implementing a flyback converter with PSS.

For more detailed analysis, the forward-biased voltage drop of the secondary diode and the winding resistance in the secondary winding also affect the accuracy of output voltage sensing. Referring to Fig. 3.5, vaux can be re-derived below

. s M i i = (3-10) ′ Differentiating of (3-10) yields . dt i d dt di_M _s′ = (3-11)

Substitution of the current changing rates of iM and i′ into (3-11) gives s

. 3 3 lks s s D o M M M L R i v v v L v ′ ′ ′ − ′ − ′ − = − (3-12)

Solving (3-12) for vM3 yields

. 1 ) ( 3 s s s D o s M K R i v v K v + ′ ′ + ′ + ′ = (3-13)

Finally, vaux can be expressed as

). ( o D s s eff

aux n v v i R

v = + + (3-14)

Define that the sensing error Δv is

s s D o eff aux o est o R i v v n v v v v + = − = − = Δ , (3-15)

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is the real output voltage. The voltage drop of the secondary diode vD is almost constant, but in DCM, the current flowing through the secondary diode decreases violently in off state. If the sampling instants to sample vaux are different with the same load, the sensing error is also different because the term isRs is dependent on the sampling instant. This will be explained in section 4.2.2.

s

K

100 101 102 65 70 75 80 85 90 95 100 calculated by (5) simulated by PSIM (%) aux o v v ) 8 -3 (

Fig. 3.4. vaux to vo ratio versus Ks assuming Ns = Na.

lks

L′

M

L

v′

o

+

−

3 M

v

+

−

M s

i′

lka

L′

aux

v′

+

−

a

i′

M

i

+

−

D

v′

s

R′

Fig. 3.5. Equivalent circuit in interval T3 considering the forward-biased voltage drop vD and

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The simulation results are in Fig. 3.6. It can be recognized that when the switch is turned off, the system enters into interval T1. In interval T1, the magnetizing current iM decreases because of energy releasing and the diode in RCD snubber conducts. When the current ic decreases to zero, the system enters into interval T2. In interval T2, the energy transfers to the load and the primary-side controller with an assumption that the power dissipation of the controller is much smaller than the load. When the rectified diode at the auxiliary side is open, the system enters into interval T3. It is mentioned before that the good timing to sample vaux is in interval T3. The sensing error Δv calculated by (3-15) and the real error signal are plotted in the last subplot in Fig. 3.6. It is clear that the calculation result and the simulation result of the sensing error are matched each other (The curve of Δv is correct only in interval T3.).

9.004 9.005 9.006 9.007 9.008 9.009 9.01 9.011 9.012 x 10-3 35 36 37 time (sec) (V ) 9.004 9.005 9.006 9.007 9.008 9.009 9.01 9.011 9.012 x 10-3 0 2 4 time (sec) (A ) 9.004 9.005 9.006 9.007 9.008 9.009 9.01 9.011 9.012 x 10-3 0 20 40 time (sec) (V ) 9.004 9.005 9.006 9.007 9.008 9.009 9.01 9.011 9.012 x 10-3 -1 0 1 2 time (sec) (V ) o v , o est v o v a i ′ s i M i c i , o est o v −v Δv 2 T 1 T 3 T

Fig. 3.6. Simulation results of flyback converter to verify the relationship between the output voltage and the estimated output voltage.

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3.2 D

ETERMINATION OF THE

S

AMPLING

I

NSTANT

Based on the analysis above, the controller needs a mechanism to set the sampling instant in interval T3. In order to set the sampling instant correctly, we need to know the lengths of interval T1 and T2.

During interval T1, the current flowing into the RCD snubber is

p lkp c M c t i L v v t i ( )=( 1− ) +ˆ (3-16)

where iˆp is the peak value of the magnetizing current. Letting ic(t) = 0, the length

of interval T1 is obtained as . ) 1 ( 1 ˆ 1 aux a o s a s c a s p p p M v K v K K K v K K K K i L T ′ − ′ − + + + + + ⋅ = (3-17)

The currents i′s and i′a during interval T1 are

t L K v v t i M s o M s ) ( ) ( = 1 − ′ ′ (3-18) . ) ( ) ( 1 t L K v v t i M a aux M a ′ − = ′ (3-19)

At the end of interval T1, when the current flowing into the RCD snubber decreases to zero, the instantaneous current in the secondary winding at t2 is obtained by substitution of (3-17) into (3-18) . ) 1 ( ) )( 1 ( ˆ ˆ 1 1 aux a o s a s c o M a s p p p s s v K v K K K v v v K K K K i K i ′ − ′ − + + ′ − + + + ⋅ = (3-20)

In similar way, the peak current in the auxiliary winding can be derived as

. ) 1 ( ) )( 1 ( ˆ ˆ 1 aux a o s a s c aux M a s p p p a a v K v K K K v v v K K K K i K i ′ − ′ − + + ′ − + + + ⋅ = (3-21)

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. ˆ ) ( 2 a lka aux M a t i L v v t i + ′ ′ − = ′ (3-22)

The current i_a′(t) will decrease to zero before i_s′(t) does because the power dissipation in the auxiliary winding is much smaller than the power dissipation in the secondary winding, so that the length of interval T2 can be obtained by letting i′ ta( )=0 as

[

]

[

]

. ) ( ) 1 ( ) 1 ( ) 1 ( ˆ 2 o s s aux aux aux a o s a s c p s aux c p o s a s p p M v K K v v v K v K K K v K K v v K v K K K K i L T ′ − ′ + ′ ′ − ′ − + + + + ′ − + ′ + + ⋅ = (3-23)

The currents i′s during interval T2 is

. ˆ ) ( 2 ₁ s lks o M s t i L v v t i + ′ ′ − = ′ (3-24)

The instantaneous current in the secondary winding at t3 when the current ia′(t)

decreases to zero can be obtained by substitution of (3-23) into (3-24) as

. ) ( ) ( ˆ ˆ 2 o aux s aux o aux p s s v v K v v v i K i ′ − ′ + ′ ′ − ′ = (3-25)

After t3, only LM and L′lks have current, the equivalent circuit in interval T3 is shown in Fig.

3.3(c). The currents i′s during interval T3 is

. ˆ ) ( _s₂ lks M o s t i L L v t i + ′ + ′ − = ′ (3-26)

The length of interval T3 can be obtained by letting i′ ts( )=0 as

. ) ( ) 1 )( ( ˆ 3 o aux s aux s o aux o M p v v K v K v v v L i T ′ − ′ + ′ + ′ − ′ ′ = (3-27)

So far, the lengths of intervals T1, T2, and T3 can be estimated.

A well-known method to generate PWM signal is comparing a dc level with a sawtooth carrier. When the dc level is higher than the carrier, PWM signal is high. On the other hand, PWM signal is low when the carrier is higher than the dc level. The carrier generator for the digital PSS controller can be realized by using the programmable timer of a DSP controller.

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Define that Vduty is the dc level to generate PWM signal, Vdelay is an integer to set the delay time after the switch is turned off, and VADC, which is the sum of Vduty and Vdelay, is used to determine the sampling instant. The mechanism is shown in Fig. 3.7. In the DSP controller, the mode of analog-to-digital converters (ADCs) should be set as compare interrupt flag. When the value of the counter is equal to VADC, ADC starts to convert analog inputs to digital output values. The key factor is Vdelay. The delay time should be longer than interval T1 plus interval T2, so the value of Vdelay satisfies the following inequality:

3 2 1 2 1 T T V T T T T + < CLK⋅ delay < + + (3-28)

where TCLK is the period of the counter.

The lengths of interval T1 and T2 limit the maximum switching frequency. The switching period shorter than the sum of interval T1 plus T2 is impossible because it is unable to sample the correct signal representing the output voltage.

on off on off duty

V

ADC

V

Counter delay

V

aux

v

Sampling instant T3 T1+ T2 T3 T1+ T2

0

TCLK VdelayTCLK VdelayTCLK tri

V

( )

d t

on off on off duty

V

ADC

V

Counter delay

V

aux

v

Sampling instant T3 T1+ T2 T3 T1+ T2

0

TCLK VdelayTCLK VdelayTCLK tri

V

( )

d t

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Chapter 4 Analysis and Design of DCM DC-DC Flyback

Converters with PSS

At the beginning of designing a DCM DC-DC flyback converter with PSS shown in Fig. 3.2(a), a dynamic model of the overall system is needed. Operating in DCM is given some advantages such that the secondary diode will naturally turn off without significant losses, the control-to-output transfer function is approximated to a first-order system in voltage mode, there are no turn-on losses on the MOSFET, and a quasi-resonant (QR) flyback converter can be realized.

The design methods for analog controllers are well-known and easy to apply. To implement a digital controller, it can be quite convenient to derive a digital controller from an existing analog design by the backward Euler integration or the trapezoidal (Tustin) integration methods. The application of these methods implies some loss of precision due to the approximations involved in the discretization process, as compared to a direct digital design. For simplicity, a continuous time equivalent block diagram of the proposed system is obtained. The procedure to define the continuous time equivalent block diagram is shown in Fig. 4.1. Fig. 4.1(a) is the block diagram of the system shown in Fig. 3.2. All components and parameters in the shaded part are in discrete time domain. The ADC is divided into a sample-and-hold (S/H) block and a scaling factor KADC, C(z) is the digital controller, and the digital pulse-width-modulation (DPWM) block is cascaded with the digital controller. Because the scaling factor of the ADC is a constant value, it can be placed in continuous time domain with no differences. The S/H block is moved to the output of the adder shown in Fig. 4.1(b). Moreover, the digital controller C(z) is transformed into an analog controller C(s), so that Fig.

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4.1(c) is obtained. In this chapter, we base on Fig. 4.1(c) to analyze DCM DC-DC flyback converters with PSS and design the control algorithm. A prototype of DCM DC-DC flyback converters with PSS is realized to verify the feasibility of PSS.

( )

C z

DPWM

G

_vod

( )

s

T

−

ref

v

o

v

sense

v

ADC

K

duty

V

d

eff

n

ac

K

H

fb

v

ADC

( )

C z

DPWM

G

_vod

( )

s

T

−

ref

v

o

v

sense

v

ADC

K

duty

V

d

eff

n

ac

K

H

fb

v

ADC

(a)

( )

C z

DPWM

G

_vod

( )

s

T

−

ref

v

o

v

sense

v

ADC

K

duty

V

d

eff

n

ac

K

fb

v

H

( )

C z

DPWM

G

_vod

( )

s

T

−

ref

v

o

v

sense

v

ADC

K

duty

V

d

eff

n

ac

K

fb

v

H

(b)

( )

C s

DPWM

G

_vod

( )

s

T

−

ref

v

o

v

sense

v

ADC

K

duty

V

d

eff

n

ac

K

H

fb

v

( )

C s

DPWM

G

_vod

( )

s

T

−

ref

v

o

v

sense

v

ADC

K

duty

V

d

eff

n

ac

K

H

fb

v

(c)

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4.1 D

YNAMIC

M

ODEL OF

DCM

DC-DC

F

LYBACK

C

ONVERTERS WITH

PSS

In order to design the control algorithm, the control-to-output transfer function is derived firstly. Then, the feedback path constructed by the flyback transformer, the voltage divider, and the ADC is developed. Finally, the DPWM is considered with a delay model.

4.1.1 Control-to-Output Transfer Function

Although the controlled system is implemented with PSS, the small-signal model of the power stage is the same as the conventional flyback converter. As the mentioned process in Fig 2.1, a flyback converter can be converted into an equivalent buck-boost converter, so that the small-signal model of the DCM buck-boost converter can be utilized to derive the control-to-output transfer function of the flyback converter. Based on [16], Figure 4.2 is the small-signal model of the DCM equivalent buck-boost converter from the flyback converter, where the parameters noted with prime are converted from the secondary side to the primary side and the ones with tilde represent perturbations of themselves without DC operating points.

2 1

g v

2

r

2

j d

o

C′

L R′ 1 2

g v

1

r

1

j d

1

v

+

−

2

v

+

−

1

i

₂ M L in

v

o

v′

+

−

c r′ Switch network small-signal ac model

Fig. 4.2. Small-signal model of the DCM equivalent buck-boost converter from the flyback converter.

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The relative parameters in the small-signal model are shown in Table 4.1. Because the average voltage on the magnetizing inductance is zero, so V1 = Vin. Re is the effective

resistance defined as s M e T D L R = 2₂ (4-1)

where D means the duty ratio under steady state conditions, and M is the voltage conversion ratio defined as

. e L ps e L in o ps in o R R n R R V V n V V M = ′ = = ′ = (4-2)

When we derive the control-to-output transfer function, let the perturbations besides

d be zero. There are only two current sources reserved. Applying superposition principle, the procedure to derive the control-to-output transfer function is simple. Step 1 is letting j d₂=0 to obtain Gvod1(s):

(

)

2 1 1 1 ₀ 2 1 1 ( ) ( ) . 1 ( ) 1 c o M o vod _{j d} L ps c L c M o o r v s j r sL sC G s R n d s _R _r R r r r sL _sC sC = ′ + ′ − _′ = = ⎡ ⎛ ⎞⎤ ₊ ₊ _′ ′ + ′ + + ⎢ ⎜ _′ ⎟⎥ _′ ⎝ ⎠ ⎣ ⎦ & & & (4-3)

Step 2 is letting j d₁=0 to obtain Gvod2(s):

(

)

1 2 2 2 ₀ 2 1 1 ( ) ( ) . 1 ( ) ₁ c o o vod _{j d} L ps c L c M o o r v s j r sC G s R n d s _R _r R r r r sL _sC sC = ′ + ′ ′ = = ⎡ _′ ⎛ _′⎞⎤ ₊ ₊ _′ + + + ⎢ ⎜ _′ ⎟⎥ _′ ⎝ ⎠ ⎣ ⎦ & & (4-4) TABLE4.1

PARAMETERS OF THE SMALL-SIGNAL DCMSWITCH MODEL

g1 j1 r1 g2 j2 r2 0 e DR V₁ 2 e R e MR 2 e DMR V₁ 2 e R M2

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Finally, the control-to-output transfer function is obtained as follows ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ ′ + ′ + ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ ′ + ′ ′ + ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ ′ ′ + ≈ + = ) ( 1 ) 2 ( 2 1 1 1 ) ( ) ( ) ( 2 2 2 2 1 o in M o e c L o c o in vod vod vod V V L V R s r R C s r C s K V s G s G s G (4-5) where s L M T R L K = 2 .

The small-signal model is derived by the averaged switch modeling method, so it is only correct at the frequency range lower than the switching frequency. Actually, there are two zeros during the calculation process, but the second zero is higher than the switching frequency. It is negligible when the system is concerned at the frequency much lower than the switching frequency.

The DC gain G0 of the control-to-output transfer function is

. 0 K V G = in (4-6)

There are two poles as follows

) Hz ( 1 1 1 1 2 1 ) Hz ( ) 2 ( 1 2 2 2 2 1 ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ + = ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ + = + = M D f M L R f r R C f s M e p c L o p π π π (4-7)

where the second pole fp2 is close to the switching frequency depending on the duty ratio and the voltage conversion ratio.

There is only one zero we concerned as follows

(Hz). 2 1 1 c o z r C f π = (4-8)

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order to verify the derivation of the control-to-output transfer function, Fig. 4.3 shows the frequency response of the control-to-output transfer function by simulation and calculation.

4.1.2 Feedback Path

PSS technique utilizes the auxiliary winding to sense the output voltage. The sensing error is analyzed in chapter 3. In this section, we only consider the effective turns ratio neff in

the feedback path. The effect of the sensing error will be discussed in the next section. The feedback path shown in Fig. 4.4 is constructed by the flyback transformer through the auxiliary winding, the voltage divider, and the ADC.

101 102 103 104 105 -20 0 20 40 60 M a gni tu de ( d B ) 101 102 103 104 105 -100 -80 -60 -40 -20 0 Frequency (Hz) P h ase ( deg) simulation result transfer function simulation result transfer function

Fig. 4.3. Frequency response of the control-to-output transfer function by simulation and calculation.

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o

C

_o

C

R

_L

v

_o

+

−

s

N

a

N

s

i

lks

L

lka

L

sense

v

+

−

1 ac R 2 ac R a

i

sec

v

+

−

A D A D fb

v

Fig 4.4. Feedback path for PSS.

When the system is during interval T3, the voltage on the auxiliary winding contains the information of the output voltage. The relationship between these two voltages is mentioned in (3-14) where the effect of the voltage drop of the secondary diode and the winding resistance is neglected here, so the first block in the feedback path from vo node is the

effective turns ratio neff. Then, the voltage on the auxiliary winding is sent to a voltage divider.

The gain of the voltage divider constructed by two resistors Rac1 and Rac2 is Kac shown below

. 2 1 2 ac ac ac ac R R R K + = (4-9)

Combining the effect of the auxiliary winding and the voltage divider together, define a feedback gain H which is expressed by

. 2 1 2 ac ac ac eff R R R n H + = (4-10)

The final part of the feedback path is the ADC, which helps to convert the analog sensed voltage vsense into a digital parameter vfb for PSS algorithm. To avoid damaging the ADC, the

range of the sensed voltage must be limited lower than the maximum input voltage of the ADC by setting a proper feedback gain H. For instance, the range must be lower than 3 volts for TMS320F2812, a DSP model of Texas Instruments (TI). The conversion ratio KADC of the

返馳式轉換器之數位式初級側感測控制

國 立 交 通 大 學

電 控 工 程 研 究 所

碩 士 論 文

返馳式轉換器之數位式初級側感測控制

Digital Primary-Side Sensing Control for Flyback

Converters

研 究 生：張哲瑋

指導教授：鄒應嶼 博士

返馳式轉換器之數位式初級側感測控制

Digital Primary-Side Sensing Control for Flyback

Converters

國立交通大學

電控工程研究所

碩士論文

返 馳 式 轉 換 器 之 數 位 式 初 級 側 感 測 控 制

Digital Primary-Side Sensing Control for Flyback Converters

誌 謝

僅以此論文獻給所有關心我的長輩、親戚與朋友…

TABLE OF CONTENTS

LIST OF TABLES

LIST OF FIGURES

Chapter 1

Introduction

1.1

R

B

R

D

1.2

R

M

O

1.3

T

O

Chapter 2

Fundamentals of Flyback Converters

2.1

O

P

DCM

F

C

i

i

i

DT

T

S

S

ˆ

i

i

i

ˆ

=

ˆ

n

i

i

ˆ

=

ˆ

v

i

d

S

f

f

2.2

D

C

F

C

Chapter 3

Digital Primary-Side Sensing (PSS) Control

Technique

(a)

(b)

國立交通大學

電控工程研究所

碩士論文

研究生：張哲瑋

指導教授：鄒應嶼博士

返馳式轉換器之數位式初級側感測控制

誌謝