A Physical Model for Hole Direct Tunneling Current
in P
+
Poly-Gate PMOSFETs with Ultrathin Gate
Oxides
Kuo-Nan Yang, Huan-Tsung Huang, Student Member, IEEE, Ming-Chin Chang, Che-Min Chu, Yuh-Shu Chen,
Ming-Jer Chen, Senior Member, IEEE, Yeou-Ming Lin, Mo-Chiun Yu, Simon M. Jang, Douglas C. H. Yu, and
M. S. Liang
Abstract—A model of the hole direct tunneling gate current accounting for heavy and light hole’s subbands in the quantized inversion layer is built explicitly. This model comprises four key physical parameters: inversion layer charge density, hole impact frequency on SiO2/Si interface, WKB transmission probability, and reflection correction factor. With the effective hole mass = 0 51 for parabolic dispersion relationship in the oxide, experimental reproduction without any parameter adjustment is consistently achieved in p+poly-gate pMOSFETs with 1.23, 1.85, and 2.16 nm gate oxide thicknesses. The proposed model can thereby serve as a promising characterization means of direct tunnel oxides. In particular, it is calculated that the secondary subbands and beyond, although occupying few holes, indeed contribute substantially to the direct tunneling conduction due to effective lower barrier heights, and are prevailing over the first subbands for reducing oxide field down below 1 MV/cm.
I. INTRODUCTION
T
HE MOSFET gate oxide thickness is rapidly approaching the direct tunneling limit that ultimately leads to intoler-ably increased standby power [1] and/or impractical applica-tions [2]. Thus, accurate characterization and modeling of ultra-thin oxides in the direct tunneling regime is essential and crucial. A series of models have recently been published concerning the electron direct tunneling in n poly-gate nMOSFETs: a self-consistent numerical method of solving Schrödinger’s and Poisson’s equations [1] and computationally efficient models [3], [4]. The latter can provide more transparent understandings since it is made up of four key physical parameters: accumula-tion or inversion layer charge density, electron impact frequency on interface, WKB transmission probability, and specially, the reflection correction factor [3], [4]. As to another complemen-tary devices, namely, p poly-gate pMOSFETs, the hole direct tunneling under channel inversion condition was found to dom-inate over valence electron direct tunneling [5], followed byManuscript received March 8, 2000. This work was supported by the National Science Council under the Contract NSC88-2215-E-009-047. The review of this paper was arranged by Editor C.-Y. Lu.
K.-N. Yang, H.-T. Huang, M.-J. Chang, C.-M. Chu, Y.-S. Chen, and M.-J Chen are with the Reliability Physics Laboratory and Institute of Electronics, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C. (e-mail: [email protected])
Y.-M. Lin, M.-C. Yu, S. M. Jang, D. C. H. Yu, and M. S. Liang are with the R&D Department, Taiwan Semiconductor Manufacturing Company, Hsinchu 300, Taiwan, R.O.C.
Publisher Item Identifier S 0018-9383(00)09621-0.
more evidences [6], [7]. In this paper, we present a model of the hole direct tunneling current featuring the above four sim-ilar physical parameters. This model can serve as a promising means of sensitively characterizing direct tunnel oxides and can enable in-depth understandings of the roles of the subbands in the quantized inversion layer.
II. CHARACTERIZATION ANDPARAMETEREXTRACTION The p poly-gate pMOSFETs were fabricated by a 0.18-m process technology [8] with gate oxides grown in diluted wet oxygen ambient to three different thicknesses. The gate dimension was drawn to 100 100 m . Accurate determi-nation of ultrathin oxide thickness is strongly demanded. Three techniques in terms of high resolution TEM(HRTEM), polysilicon depletion and quantum mechanics corrected capac-itance–voltage (C–V) [9]–[11], and direct tunneling (DT) I–V [3] were adopted as shown in Fig. 1, through which consis-tent results were achieved as compared in Fig. 2. Fig. 1(a) just shows highly-localized HRTEM cross section while the vari-ation across the wafer is depicted in Fig. 2 in terms of a bar. Our C–V data in Fig. 1(b) was measured in parallel mode with 1-MHz AC frequency. QM corrected C–V fitting based on van Dort’s model for surface quantization [9], [10] was carried out to extract physical . In particular, the singular point problem encountered around the flat-band voltage was eliminated by adopting a modified version [11]. In Fig. 1(b), C–V fitting for
nm is limited to nondistorted range, 0.6 V
0.6 V, where the tunneling current effect or others can be ne-glected. C–V fitting in Fig. 1(b) also produced the p
polysil-icon dopant concentration cm and the
effective channel dopant concentration cm , all being found to be consistent with the SIMS doping profile. In Fig. 1(c), the devices were biased in channel accumulation (pos-itive gate voltage) with source, drain, and -well tied to ground, and the oxide field strength was get in advance by means of the well-known C–V integration technique. With the effective electron mass for Franz-type dispersion rela-tionship in the oxide, the conduction electron DT I–V fitting in Fig. 1(c) extracted , 1.85, and 2.16 nm from three samples. Note that as all data go closer to the straight line with the unity slope in Fig. 2, more confidence for DT I–V extracted , as well as its subsequent applications in consistently cal-culating the DT hole current, can all be ensured.
(a)
(b)
(c)
Fig. 1. (a) HRTEM images of three pMOSFET gate stacks. T values extracted from the canvases correspond to 2.25, 1.89, and 1.32 nm, respectively. (b) The oxide thickness extraction using C–V method was based on van Dort’s model [9] and successive researchers [10], [11]. Best fitting produces T of 2.0, 1.75, and 1.3 nm, respectively. (c) I–V fitting to findT . T values extracted by electron direct tunneling model [3], including quantization effect in accumulation layer underV > V , are 2.16, 1.85, and 1.23 nm, respectively.
Fig. 2. ComparingT extracted from several techniques.
(a)
(b)
(c)
Fig. 3. (a) Measured hole direct tunneling current I (' I ) and valence electron tunneling currentI (' I ) of three different T under
V < 0V . (b) The carrier separation configuration and (c) band diagram
representation are schematically drawn.
With source, drain, and n-well tied to ground, the source/drain current ( ), bulk current ( ), and gate current ( ) mea-sured in inversion are plotted in Fig. 3(a) versus gate voltage ( ). The corresponding carrier separation configuration and the band diagram representation are schematically drawn in Fig. 3(b) and (c), respectively. It can be identified that the hole direct tunneling is responsible for source/drain current while the valence electron direct tunneling constitutes bulk current. It is seen from Fig. 3 that the hole direct tunneling dominates over the valence-band electron direct tunneling in gate voltage of 0 V to certain crossover point, which is consistent with [5]–[7]; however, the magnitude of this crossover gate voltage increases with decreasing oxide thickness, a phenomenon not mentioned before. A specific criterion of 1 A/cm at gate voltage of 1 V sets an ultimate limit of slightly thicker than 1.23 nm, again consistent with [2]. The impact of hole direct tunneling on normal device operation can be found in Fig. 4, revealing that the hole direct tunneling from inverted channel can reverse the polarity of the linear drain current. The similar drain current degradations for the n-channel counterpart have been reported
Fig. 4. Measured outputI–V characteristics with W=L = 10 m/50 m andT = 1:23 nm. I reverses its polarity at small jV j due to direct hole tunneling.
Fig. 5. Physical picture of valence hole quantized phenomenon alongh100i direction.G (E) indicates density of states relative to hole’s energy. F (E) represents Fermi–Dirac distribution function of hole and E means the quantized extremity energy of thejth subband.
previously [12], [13]. The impact of hole DT as outlined in Fig. 4 is one of the primary motivations of the underlying study. To clarify the essential mechanisms, however, the work focuses on the case of tying source and drain to a common potential.
III. PHYSICALMODEL
The two valence bands (heavy and light band), which are de-generate at ( point), have the form of warped spheres; therefore, the method concerning degenerate perturbation is necessary for the valence band [14]:
Fig. 5 schematically shows the physical picture of the va-lence-band hole tunneling from the silicon inversion layer. In Fig. 5, a table lists the effective mass ( ) along direction and density of states mass ( ) of each type of hole as cited in [15]. The direct tunneling hole current from each subbands can be formulated in analogy with the mathematical treatment of
electron direct tunneling in [3]. Hole current density contributed by th subband with energy to can be written as
(1) where
elemental charge;
impact frequency of hole’s wave packet on interface;
inversion layer charge density per unit area and mag-nitude of associated with th subband;
transmission probability through layer. Denoting as the classical turning point at the th subband
edge and as the velocity of
wave packet
(2) Triangle-like electrostatic potential is a good approximation for . Using Sommerfeld-Wilson’s quantization rule, we are able to get quantized energy along -direction or direction in reciprocal space
For inversion charge increment
(3) In (3), density of states per unit area for two-dimensional hole gas (2DHG), , is equal to and Fermi–Dirac distri-bution function associated with valence holes is
. is the quasi–Fermi level and is Boltzmann’s constant. Under the inversion condition, it is easy
to build that . means the
potential drop on the p -poly gate, and signifies that on the n-well. Considering the poly-depletion effect, we know that
can be expressed as . Note that the values
of oxide field strength are obtained by the C–V integra-tion technique so that the surface potential, , can be com-puted directly. Thus, is equal to . Here
is the potential difference between the quasi–Fermi level ( ) and valence band ( ) in the charge neutrality region of n-well.
Following [3], can be modeled by
(4) where
is the barrier height of tunneling hole with total energy at cathode side or p -poly gate/ interface, and is
that at anode side or /n-well interface.
and . In our work, the
barrier height is 4.7 eV for both heavy and light hole. The total energy, , consists of the transversal and longitudinal en-ergies
where is the transversal mass. On the other hand, is a jus-tified factor concerning wavefunction’s reflection phenomenon occurring at interfaces as discussed in [3] and [4], as follows:
where and are the group
ve-locities of the holes incident and leaving the oxide, respectively. The group velocity of hole with energy along direction within the th subband at interfaces is independent of
with the following expression:
Besides, and are the magnitudes of the
purely imaginary group velocities of holes at the cathode and anode side within the oxide, respectively. Parabolic dispersion
relation, , is
adopted to gauge the tunneling hole’s behavior within the oxide film. Consequently, the imaginary group velocity which is de-pendent on within oxide can be described by
This factor could not be neglected when electrostatic potential changes acutely with respect to position or the intensity of incident wave cannot be treated to being equal to that of re-flection wave.
Recalling (1)–(4), the tunneling current density contributed by the th subband with energy ranging from , the subband extremity, to infinity can be shown below:
An explicit model of hole direct tunneling current from all heavy and light holes, subbands is readily built as follows:
Fig. 6. Simulated results (lines) and experimental data (symbols) for pMOSFET direct tunneling hole current of three differentT under V < 0 V.V can be related to E by means of the C–V integration technique.
(5) Index and mean heavy and light holes, respectively.
IV. CALCULATION ANDDISCUSSION
Essentially, there are three input parameters to the model: the oxide field , the effective hole mass for para-bolic relationship in the oxide, and the oxide thickness . The other physical parameter values are unique and cannot be ar-bitrarily adjusted when fitting data. Fortunately, the well-rec-ognized integration technique carried out directly on the C–V curves in Fig. 1(b) can easily quantify . An effective hole mass for heavy and light hole was found to be capable of modeling reasonably well the hole direct tunneling
I–V characteristics as plotted in Fig. 6 for three different oxide
thicknesses. The corresponding oxide thicknesses were consis-tently identical to those involved with conduction-band electron tunneling in Fig. 1(c) due to the same samples used. Excellent reproduction in Fig. 6 can lead to one argument that the pro-posed model can find its potential applications in terms of a sen-sitive means of characterizing direct tunnel oxides.
Ten subbands for heavy hole and six subbands for light hole were used in above modeling. Based on the simplified method to calculate the subband energies [16], in-depth understandings concerning the roles of different subbands in the quantized inver-sion layer can be created fully. First of all, the occupation ratio, defined as , of the subbands was calculated versus oxide field as shown in Fig. 7. It can be seen that the heavy hole lowest (first) subband occupies most (90%) of all inversion holes and this ratio drops with lowering . However, the light hole first subband, which occupies considerably 10%, exhibits opposite trend. Fig. 7 also reveals that the remaining subbands get few due to their higher quantized states whereas as we go to-ward lower , more and more holes are filling the secondary subbands and beyond. Although higher energy states share far less carriers, the other factor such as the transmission probability can be much larger than the ground state due to effective lower barrier heights for tunneling. The resulting tunneling current thus contains a substantial component from the secondary subbands
Fig. 7. Occupation ratioN = N of all the subbands versus oxide field.N = 4 2 10 cm .
Fig. 8. Partial fractionJ = J of direct tunneling hole current contributed by two lowest subbands versus oxide field.T = 1:85 nm; N = 4210 cm ;N = 4:2 2 10 cm .
and beyond. This is valid, in particular, under the condition of small as clearly depicted in Fig. 8 in terms of the partial fraction defined as . For the first time, this figure points out that the hole direct tunneling from the secondary subbands and beyond prevails over the first subbands for reducing oxide field down below around 1 MV/cm.
V. CONCLUSION
A physical model of the hole direct tunneling through ultra-thin oxides has been built and experimental reproduction has been consistently achieved in p poly-gate pMOSFETs for dif-ferent oxide thicknesses. This model has evidenced its potential applications in sensitively characterizing direct tunnel oxides as well as enabling in-depth understandings of the role of the dif-ferent subbands in affecting hole direct tunneling conduction.
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Kuo-Nan Yang was born in Yuen-Lien, Taiwan,
R.O.C. He received the B.S. and M.S. degrees in electronics engineering from National Chiao-Tung University (NCTU), Taiwan, in 1998 and 1999, respectively. he is currently pursuing the Ph.D. degree in electronics engineering with the research group of Prof. M.-J. Chen at the Department of Electronics, NCTU.
His interests include modeling and reliability physics of MOSFETs structure.
Huan-Tsung Huang (S’98) received the B.E.
degree in electrical engineering from the National Cheng-Kung University, Taiwan, R.O.C., and the M.S. and Ph.D. degrees in electronics engineering from the National Chiao-Tung University, Hsinchu, Taiwan, in 1988, 1990, and 2000, respectively.
From 1990 to 1992, he served in the Chinese army as a Tactical Control Officer. Since 1992, he has been with Ta-Hua Institute of Technology, Chung-li, Taiwan. His research interests are currently the reliability issues such as TDDB, soft breakdown, trap-assisted tunneling leakage, etc., in deep submicron CMOS.
Ming-Chin Chang was born in Yuen-Lien, Taiwan,
R.O.C., in 1975. She received the B.S. and M.S. de-grees in electronics engineering from National Chiao Tung University (NCTU), Hsinchu, Taiwan, respec-tively, in 1998 and 2000.
Her primary research interest is gate dielectric re-liability.
Che-Min Chu was born in Taiwan, R.O.C., on
September 14, 1976. He received the B.S. degree in electrical engineering from the National Chiao-Tung University, Hsinchu, Taiwan, in 1999. He is currently pursuing the M.S. degree and engages in modeling and physics of submicron MOSFET reliability.
Yuh-Shu Chen was born in Kaoshiung, Taiwan,
R.O.C., on January 6, 1974. He received the B.S. degree in electronic engineering from the National Chung Hsing University in 1996, and the M.S. degree from the Institute of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan, in 1999.
His research interests include C–V simulation and analysis in MOSFETs, and quantum-mechanical ef-fects in deep submicron MOS structure.
Ming-Jer Chen (S’78–M’79–S’80–M’84–SM’98)
received the B.S. degree in electrical engineering with highest honors from National Cheng-Kung University, Taiwan, R.O.C., in 1977, and the Ph.D. in electrical engineering form National Chiao-Tung University (NCTU), Hsinchu, Taiwan, in 1985. Since 1985, he has been with the Department of Electronics Engineering, NCTU, where he is Professor. From 1987 to 1992, he was a Principal Consultant sy TSMC, where he led a team to build process window and design rule. In 1996 and 1997, he enabled the ERSO/ITRI video A/D converters and the TSMC mixed-mode CMOS processes, respectively. His current areas are nanoscale reliability physics and next-generations electronics. He has graduated six Ph.D. students and has been granted four U.S. patents and six Taiwan patents.
Professor Chen is a Co-Winner of the 1992 and 1993 Chinese Young En-gineer Paper Award, and a Co-Winner of the 1996 Acer Distinguished Ph.D. Dissertation Award. He is a Member of Phi Tau Phi.
Yeou-Ming Lin was born in Taipei, Taiwan, R.O.C.,
in 1968. He received the B.S. degree in electrical engineering from the Tatung Institute of Technology in 1991, the M.S. degree in electrical engineering from the National Hsin-Hua University in 1993, and Ph.D. degree in electronic engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 1997. His Ph.D. dissertation focused on process issues of interpoly-silicon dielectric and intermetal dielectric and their impacts on device reliability.
From 1994 to 1995, he worked on intermetal di-electric development for 0.35-m CMOS at Taiwan Semiconductor Manufac-turing Company (TSMC), Hsinchu. Since September 1999, he is responsible for gate quality silicon and high-k gate dielectric for 0.1-m CMOS at TSMC. He nis now with Sematech for process development and reliability of gate quality silicon.
Mo-Chiun Yu was born in Hsinchu, Taiwan, R.O.C.,
in 1968. He received the B.S. degree in electrical engineering from National Tsing-Hua University, Hsinchu, in 1991, and the M.S. degree in electrical engineering from Tohoku University, Sendai, Japan in 1997, under the sponsorship of the Ministry of Education of Taiwan.
In 1997, he joined Taiwan Semiconductor Manu-facturing Company Ltd., Hsinchu, where he has been engaging in research and development for ultrathin gate dielectric process and characterization.
Simon M. Jang received the B.S. and M.S. degrees
from the National Tsing-Hua University, Hsinchu, Taiwan, R.O.C., in 1985 and 1987, and the Ph.D. de-gree from the Massachusetts Institute of Technology (MIT), Cambridge, in 1993, all in materials science and engineering. His dissertation work included SiGe CVD technology, kinetics, and thermal stability for HBT application. Sponsored by IBM and SRC, his research was conducted in the Microsystems Technology Laboratories, MIT, under the guidance of Prof. R. Reif in electrical engineering.
He joined Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu Taiwan, in 1993. He has successfully developed ozone-TEOS, spin-on coating, HDPCVD dielectrics, PECVD SiON anti-reflection layer, and CMP processes for 0.5–0.18 m CMOS technologies. He is now the Manager of Dielectric/CMP/Diffusion Projects in the Advanced Module Technology Division, R&D, responsible for the modules of shallow trench isolation, gate stack, ultrashallow junction, interpoly-metal dielectric, low-dielectric-constant intermetal dielectric, and oxide, tungsten, and copper CMP for 0.13 m generation and beyond. He has authored or co-authored more than 40 technical papers and received 48 U.S. patents and 50 Taiwanese patents.
Dr. Jang is a Member of Phi Tau Phi.
Douglas C.H. Yu received the Ph.D. degree from the
Material Engineering Department, Georgia Institute of Technology, Atlanta.
He was with AT&T Bell Laboratories, Allentown, PA. The projects he involved include PECVD thin film processing, 256 k/1 Mb SRAM process integration and yield improvement, 0.35/0.25m ultrahigh performance logic device development, modular BiCMOS and MiM process integration. He later joined Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, Taiwan, R.O.C., where he lead a module team to successfully develop TSMC 0.5m, 0.35 m, and 0.18
m core logic technologies. He performed yield improvement and transferred
the process to manufacturing. He also managed an advanced technology team to develop and qualify TSMC 1st Cu technology for 0.18m technology. Currently he manages a module team to develop TSMC Cu/low-k interconnect, gate stack, salicide, and shallow-trench-isolation, etc. He has been awarded 91 U.S. patents with another 90 patent applications pending. Also, he has numerous publications in technical journals and conferences, all in VLSI processing/device/integration area.
