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Flexible One Diode–One Resistor Crossbar Resistive-Switching Memory
View the table of contents for this issue, or go to the journal homepage for more 2012 Jpn. J. Appl. Phys. 51 04DD09
(http://iopscience.iop.org/1347-4065/51/4S/04DD09)
Flexible One Diode–One Resistor Crossbar Resistive-Switching Memory
Jiun-Jia Huang, Tuo-Hung Hou, Chung-Wei Hsu, Yi-Ming Tseng, Wen-Hsiung Chang1, Wen-Yueh Jang1, and Chen-Hsi Lin1
Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan 1Winbond Electronics Corporation, Taichung 428, Taiwan
Received September 26, 2011; revised December 2, 2011; accepted December 24, 2011; published online April 20, 2012
We report the first demonstration of a flexible one diode–one resistor (1D1R) resistive-switching (RS) memory cell capable of high-density crossbar array implementation at an extremely low cost. A Ti/TiO2/Pt diode with a large rectifying ratio and a stable Ni/HfO2/Pt unipolar RS memory element have been fabricated on a polyimide substrate using only room-temperature processes. No significant degradation of the rectifying ratio of the TiO2diode and the cycling variations, retention, and read disturb immunity of the HfO2memory was observed in the bending state. The series 1D1R cell shows highly reproducible unipolar RS because of the low reset current of the HfO2memory, which greatly mitigates the adverse effect of diode series resistance. Furthermore, the 1D1R cell can effectively suppress read interference and realize a crossbar array as large as 512 kbit. # 2012 The Japan Society of Applied Physics
1. Introduction
Flexible electronics have received increasing attention because of their advantages of low cost, light weight, flexibility, and capability of large-area process. However, traditional Si technology requiring high-temperature proc-esses is incompatible with the low glass transition temperature of flexible substrates. In contrast, oxide-based materials deposited at a low temperature have shown promising characteristics for flexible electronics applica-tions, such as indium–gallium–zinc oxide for thin-film transistors in the flexible active matrix backplane.1) To realize another fundamental building block of flexible electronics, namely, nonvolatile memory, considerable efforts are being made to develop resistive-switching random access memory (RRAM) on flexible substrates, exploiting the nonvolatile variable resistance in transition metal oxides.2–4) In addition to its superior memory characteristics, RRAM is highly attractive for flexible nonvolatile memory because of its simple crossbar archi-tecture and low-temperature fabrication.5) However, a passive crossbar array is known to suffer from the so-called sneak current problem, and thus it is difficult to scale up beyond 64 bits because of severe read interference.6,7) The development of low-temperature selection devices in series with resistive-switching (RS) memory elements on flexible substrates is critical, but significantly less emphasized. Recently, we have successfully demonstrated the fabrication of both RS memories and rectifying oxide diodes on Si substrates at room temperature.8,9)The TiO2-based metal– insulator–metal (MIM) devices with a Pt bottom electrode exhibited excellent rectifying, bipolar RS, and unipolar RS characteristics, which were realized by choosing appropriate top-electrode materials. The rectifying oxide diode is applicable to the compact one diode–one resistor (1D1R) crossbar architecture, which suppresses read interference in high-density memory arrays.10–12) In comparison with the conventional one transistor–one resistor (1T1R) architecture, 1D1R with a 4F2 unit cell size not only significantly increases bit density, but also enables a simple implementa-tion of the low-temperature and low-cost flexible memory.
In this study, we fabricated 1D1R memory cells, consisting of a Ti/TiO2/Pt diode element and two different
types of RS memory elements, namely, Pt/TiO2/Pt and Ni/HfO2/Pt. The TiO2-based diode and RS element are interesting because of their potential for a monolithic TiO2 1D1R cell, but a high reset current (IRESET) of the TiO2 RS element (over 10 mA) led to unstable unipolar RS in the 1D1R cell. On the other hand, when the TiO2-based diode was integrated with the HfO2RS element with a lowIRESET (less than 1 mA), stable unipolar RS characteristics can be realized. Additionally, the excellent rectifying characteris-tics with a high resistance ratio at reverse and forward biases enabled the realization of a compact 512 kilobit (kb) crossbar memory array with an at least 10% readout margin. Because the entire device fabrication was completed at room temperature, the proposed 1D1R cell was successfully fabricated on a polyimide (PI) substrate and was found to be promising for flexible and high-density memory applica-tions using roll-to-roll processing at an extremely low cost in the future.
2. Experimental Procedure
Prior to the device fabrication, 75-m-thick KaptonÒ polyimide (PI) substrates were cut and ultrasonically cleaned in acetone for 10 min to remove particles and contamination, followed by baking at 100C for 30 min. The cleaned PI substrates were then electrostatically attached to silicon wafers. Because the PI substrate is susceptible to water absorption, a buffer layer of SiO2with a thickness of 300 nm was deposited by plasma-enhanced chemical vapor deposi-tion (PECVD). Platinum bottom electrodes of 80 nm with a thin Ti adhesion layer were deposited onto substrates by electron beam evaporation. To fabricate the TiO2 oxide diode and RS memory element, the TiO2 active layers with a thickness of 50 nm were deposited by electron beam evaporation at room temperature, and then 100-nm-thick Ti and Pt top electrodes with an area of 104m2 were patterned using a shadow-mask technique for the Ti/TiO2/ Pt diode and the Pt/TiO2/Pt RS element, respectively. To fabricate the HfO2 RS memory element, HfO2 active layers with a thickness of 80 nm were prepared by dc magnetron reactive sputtering using a Hf target (99.5%) in a mixture of Ar and O2 at room temperature, and then 100-nm-thick Ni top electrodes with an area of104m2were patterned using a shadow-mask technique for the Ni/HfO2/ Pt RS element. All devices reported in this study were fabricated completely at room temperature without any
E-mail address: [email protected] DOI: 10.1143/JJAP.51.04DD09
additional thermal treatment. In addition to the flexible devices, conventional devices on silicon substrates were also prepared using the same process. The detailed process flow is shown in Fig. 1. Figure 2(a) shows a photograph of a fabricated flexible device that was highly robust under mechanical strain. Figure 2(b) shows the measurement setup using a concave stage with a radius of 30 mm to characterize
devices in the bending state. All electrical measurements were performed using a HP-4156B semiconductor analyzer. The 1D1R cells were externally connected and voltage was applied to the Ni or Pt top electrode of the RS memory element while the Ti top electrode of the TiO2diode element was grounded.
3. Results and Discussion 3.1 Ti/TiO2/Pt diode
Figure 3 shows the rectifying characteristics of the Ti/TiO2/ Pt diode under both flat and bending conditions. Even though fabricated on the flexible substrate, Ti/TiO2/Pt diodes exhibit a large rectifying ratio of 106 at 1 V, an ideality factor of 1.2, and a robust endurance up to hundreds of successive DC sweeps without dielectric breakdown. The results are comparable with those of the diodes fabricated on Si,9)showing a minimal substrate effect. A rectifying ratio of more than 105 at 1 V can be maintained in the bended devices, indicating negligible degradation of the diode characteristics under bending condition. The asymmetry of current–voltage (I–V) curves was explained by the different Schottky barrier heights at the Ti/TiO2 and the TiO2/Pt interfaces.9) When applying a negative voltage to the Pt electrode, electrons were injected from Pt to TiO2, but encountered a substantial Schottky barrier. When applying a positive voltage to Pt, electrons were injected from Ti to TiO2. Current increased exponentially with bias voltage and was eventually limited by the smaller barrier at the Ti/TiO2 interface and parasitic series resistance.
Ar 100sccm O2 30sccm HfO2 5m Torr Flexible PI Buffer Layer Pt TiO2 Diode element
Active layers deposition
RS element
TiO2
Top electrode deposition and patterning
Pt Substrate preparation Ni HfO2 Pt O2 Hf O2 Hf O2 TiO2 TiO2 TiO2
V Si Sub.
Buffer Layer Pt
TiO2
TiO2 TiO2 TiO2
TiO2 Pt Ti Ti TiO2 Pt Pt
Fig. 1. (Color online) Fabrication of Ti/TiO2/Pt, Pt/TiO2/Pt, and Ni/HfO2/Pt devices on PI and silicon substrates.
(a)
(b)
R
Fig. 2. (Color online) (a) Photograph of a fabricated flexible device under bending condition. The insert shows the microscope image of the device on the PI substrate. (b) Measurement setup using a concave stage with a radius of 30 mm to characterize devices in the bending state.
-2 -1 0 1 2 10-10 10-8 10-6 10-4 10-2 Current (A) Voltage (V) TiO2 Pt Ti (a) Bending V Flat 101 103 105 107 109 0.51 10 40 70 95 99.5 flat bending Percentile (%) Resistance (Ω) (b) RDiode_F@1V RDiode_R@-1V
Fig. 3. (Color online) (a) 100 successive2 V dc sweeps, and (b) cumulative plot of forward/reverse resistances at 1 V/1 V of the flexible Ti/TiO2/Pt diodes in both flat and bending states.
J.-J. Huang et al. Jpn. J. Appl. Phys. 51 (2012) 04DD09
3.2 Pt/TiO2/Pt RS memory element and monolithic TiO2 1D1R cell
In contrast to the Ti/TiO2/Pt bipolar RS memory element,9) the Pt/TiO2/Pt RS memory was nonpolar after the initial forming process and applicable to the 1D1R crossbar array utilizing unipolar RS. The oxygen-deficient filament was believed to be responsible for the observed RS.8)Figure 4 shows the typical unipolar RS curves of the Pt/TiO2/Pt RS memory for positive SET (VSET) and RESET (VRESET) voltages. Although the unipolar RS was stable, the IRESET was over 10 mA, comparable to the maximum current a TiO2 diode can provide. The highIRESET not only resulted in excessive switching power undesirable for low-power operation, but also deteriorated the stability of RS in a 1D1R cell. Because of the comparable currents in the diode and RS element, the diode series resistance was not negligible in the 1D1R cell when the RS element was in the low resistance state (LRS). Hence, VRESET significantly increased. In contrast,VSETwas less sensitive to diode series resistance because of the considerably larger resistance of the RS element in the high resistance state (HRS). As a result, the programming margin between unipolar VSETand VRESET diminished and unipolar RS became less stable, as shown in Fig. 5, that the TiO21D1R cell exhibits only a few stable switching cycles without programming error. Figure 6 further shows the predicted programming margin as a function of IRESET at a fixed diode on-current of 10 mA. For a RS memory element with VRESET of 0.5 V andVSET between 2 to 4 V considering cycling variations, IRESET below 1 mA would be required for a stable unipolar RS in the 1D1R cells.
3.3 Ni/HfO2/Pt RS memory element and heterogeneous HfO2–TiO2 1D1R cell
The RS in the Ni/HfO2/Pt memory fabricated on the flexible PI substrate was also nonpolar after the initial forming process. The RS may be attributed to the formation of Ni filaments through HfO2 by Ni ion migration from the top electrode after electrical forming, and rupture and connection of Ni filaments by Joule heating and ion migration.13,14) Other studies suggested a different mechan-ism by Joule-heat-induced redox of NiOxat the interface of Ni and HfO2.15,16)Further studies in the future are required
to clarify the origin of the RS in more detail. The unipolar RS with positiveVSETandVRESET was highly reproducible, as shown in Fig. 7(a), with a resistance ratio of HRS to LRS (RHRS=RLRS) of approximately 102 and IRESET less than 1 mA even under bending condition. Figure 7(b) shows the cumulative plot of HRS and LRS resistance in both the flat and bending states with markedly tight distributions. Figure 8 shows superior immunity to read disturb and retention characteristics of the HfO2 RS element regardless of whether the substrate was flat or bended. The reproducible and reliable unipolar RS in the bending state demonstrates
0 1 2 3 4 10-9 10-7 10-5 10-3 10-1 Current (A) Voltage (V) 0 1 2 3 4 5 6 10-10 10-8 10-6 10-4 Current (A) Voltage (V)
Fig. 4. Typical unipolar RS characteristics of the Pt/TiO2/Pt memory element withIRESETover 10 mA. Inset shows the typical formingI–V curve
with a forming voltage of approximately 5 V.
-1 0 1 2 3 4 10-9 10-7 10-5 10-3 -1 10 Diode 1D1R Current (A) Voltage (V) TiO2 Pt Ti TiO2 Pt Pt V RS element Diode element Small window
Fig. 5. Unstable unipolar RS in the monolithic TiO21D1R cell because of the small programming margin.
10-4 10-3 10-2 0 1 2 3 4 V oltage(V) Current (A) VRESET ΔVSET (a) Programming margin -1 0 1 2 3 4 10-9 10-7 10-5 10-3 10-1 Current (A) Voltage (V) IRESET=10-4 A IRESET=10-2 A VRESET VSET (b)
Fig. 6. (Color online) (a) Programming margin of a 1D1R cell as a function ofIRESET. The diode on-current was fixed at 10 mA. ARHRS=RLRS
ratio of 100,VRESETof 0.5 V, andVSETbetween 2 to 4 V considering cycling
variations were assumed for the RS element. (b) Simulated 1D1R unipolar switching curves for RS elements withIRESETof 0.1 and 10 mA,
the feasibility of RS memory for flexible electronics applications. In Fig. 9, by connecting the HfO2 RS memory with low IRESET and the TiO2 diode in series, a highly reproducible unipolar RS with a substantialRHRS=RLRSratio was realized at a positive bias, whereas the current at a negative bias remained extremely low owing to the reverse-biased diode even when the RS memory was in LRS. The high rectifying ratio shown here is among the best ever
reported for 1D1R cells, including those fabricated on Si substrates.10–12)
3.4 Prediction of read margin in 1D1R crossbar array In this section, the prediction on the read margin of 1D1R crossbar array is explained using the device parameters extracted from the standalone 1D1R cell in Fig. 9. Figure 10 depicts the equivalent circuit of anN N crossbar memory array in the worse-case scenario of read interference where all unselected cells are in LRS.6,17)Considering a one bit-line pull-up read scheme,6) the sneak current can flow through the unselected cells, represented by the parallel resistor networks of R1, R2, and R3 in Fig. 10, which leads to read error when the selected cell is in HRS (Rselected¼ RHRS). In the 1D1R crossbar array as shown in Fig. 11, R2 contributed by all unselected cells at unselected word/bit lines in parallel is considerably larger than the sum of R1 and R3 because of the reverse biased diodes. Therefore, the resistance in the sneak current path can be approximated by RLRS R=ðN 1Þ2, where RLRS R is the resistance of the standalone 1D1R cell in LRS dominated by the reverse biased diode at the negative read voltageVread, as shown in Fig. 11. RLRS F andRHRS F are also defined as the resistances of the standalone 1D1R cell in LRS and HRS, respectively, when read at Vread. When RLRS R=ðN 1Þ2 decreases as N increases and eventually becomes compar-able toRLRS Fof the selected bit, the sneak current begins to 10-8 10-6 10-4 10-2 Current (A) 0.5 1.0 1.5 2.0 10-8 10-6 10-4 10-2 Current (A) Voltage (V)
flat
bending
(a) 0 1 2 3 4 5 6 10-9 10-7 10-5 10-3 Current (A) Voltage (V) 0.5 HRS LRS [email protected] (b) 102 103 104 105 106 0.51 10 40 70 95 99.5 Resistance (Ω) Percentile (%) flat bendingFig. 7. (a) 100 successive unipolar RS cycles withIRESETless than 1 mA,
and (b) cumulative plot of HRS and LRS resistance at 0.2 V of the flexible Ni/HfO2/Pt memory element in both flat and bending states. Inset in (a) shows the typical formingI–V curve with a forming voltage of approximately 5 V. 101 102 103 103 104 105 106 Resistance ( Ω ) Stress time (s) 102 103 104 Retention time (s) HRS Vstress@0.2V V [email protected] LRS HRS LRS bending flat bending flat
Fig. 8. Read disturb and retention characteristics of the flexible Ni/HfO2/ Pt memory element in both flat and bending states.
-2 -1 0 1 2 3 4 10-9 10-7 10-5 10-3 Current (A) Voltage (V) Ni HfO2 Pt TiO2 Pt Ti V Vread -Vread
Fig. 9. (Color online) More than 200 successive unipolar RS cycles with a high rectifying ratio at1 V in the heterogonous TiO2–HfO21D1R cell.
.
.
.
.
.
.
. . .
..
.
Voltage Swing W o rd Line DecoderBit Line Decoder
Region 1 (R1) Region 2 (R2) GND GND Region 3 (R 3)
=
Vpu Rpu Rselected Isneak R3 R2 R1 Rpu Vpu Voltage Sense AmplifierFig. 10. (Color online) Schematic of anN N crossbar memory array and its equivalent circuit in the worse-case read scenario where all unselected cells are in LRS. The sneak current through R1, R2, and R3
results in severe read interference.
J.-J. Huang et al. Jpn. J. Appl. Phys. 51 (2012) 04DD09
interfere with the read process in the large 1D1R array. Thus, the ratio ofRLRS RtoRLRS F is a good measure of the maximum crossbar array size with a tolerable read margin.
The readout voltage on the pull-up resistor Rpu can be calculated when Rselected¼ RLRS F and Rselected¼ RHRS F, using an equivalent circuit method similar to that applied for a complementary resistive switch (CRS) crossbar array18) and a one selector–one resistor (1S1R) crossbar array.19) When R1and R3 are omitted in Fig. 11, the readout voltage swing V normalized to the pull-up voltage Vpu can be quantitatively estimated using the resistor voltage divider equation as follows: V Vpu ¼ Rpu RLRS F k R LRS R ðN 1Þ2 þ Rpu Rpu RHRS Fk RLRS R ðN 1Þ2 þ Rpu ; ð1Þ
where Rpu is set to RLRS F for the maximum read margin. For a 10% readout margin, Fig. 12 shows that the maximum allowed word lines in a square crossbar array increased dramatically from 2 in a passive array to 750, which is equivalent to approximately 512 kb, in a 1D1R array utilizing the parameters extracted from Fig. 9. The 1D1R array can be further scaled up to 1 Gb with an improved RLRS R=RLRS F ratio of109.
4. Conclusions
A rectifying Ti/TiO2/Pt oxide diode and a unipolar RS Ni/ HfO2/Pt memory element have been fabricated on a flexible PI substrate with excellent characteristics using only room-temperature processes. No significant device degradation was found in the bending state. Additionally, the impact of IRESET on the programming margin of unipolar RS has been examined. The heterogeneous TiO2–HfO2 1D1R cell not only demonstrates a more stable unipolar RS than a monolithic TiO2 1D1R cell because of the lowerIRESET in the HfO2 memory element, but also effectively suppresses the sneak current. The maximum allowed array size with an at least 10% read margin is predicted to exceed 512 kb using a simple equivalent circuit model. Therefore, the proposed 1D1R cell is extremely attractive for implementing high-density nonvolatile memory in future low-cost flexible electronics.
Acknowledgments
This work was supported by the National Science Council of Taiwan, Republic of China, under grant NSC 97-2218-E009-039-MY3, 99RB08, and 100RB13. The authors would like to thank the Nano Facility Center at National Chiao Tung University and National Nano Device Laboratories, where the experiments in this study were performed.
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512 Kb 1 Gb 21 23 25 27 29 211 213 215 217 219 0 10 20 30 40 50 Δ V/V pu (%)
Number of Word/Bit Line (N)
1R
1D1R (this work) 1D1R (projection)
512 Kb 1 Gb
10% Read margin
Fig. 12. (Color online) Normalized readout marginV=Vpuas a function
of the number of word/bit lines in anN N crossbar array. The maximum allowed array size with an at least 10% readout margin can be markedly increased in 1D1R arrays compared with 1R passive arrays.
