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太陽能追日系統之設計與製作

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The Design and Implementation of Solar Tracking System

作者:吳宗樺、劉書榮、黃秋福、劉彥廷、賴穎儒 系級:電機工程學系 二乙 學號:D0073926 D0041614 D0075000 D0073885 D0073960 開課老師:何子儀 課程名稱:微處理機系統實習 開課系所:電機工程學系 開課學年:101 學年度 第 2 學期

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20 AT89S52 AT89S52 關鍵字 關鍵字關鍵字 關鍵字::::

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Abstract

The impact of global warming and the lack of materials and oil resources. The world began efforts to develop alternative energy sources and actively develop green energy to replace the use of fossil fuels to generate electricity. Solar energy is currently the most widely used today. The solar power generation equipment can be used more than twenty years and less polluting to the environment.

Solar tracking system is primarily designed to improve energy conversion efficiency of the solar panels. Initially, solar cells based on a fixed direction to generate electricity from sunlight, it is called passive solar power. With the advancement of technology, the passive solar power becomes to automatic solar power. The automatic solar power can be divided into single-axis tracking system and two-axis tracking system.

The main purpose of this project is to design a light-sensing control circuit that can transform the light source signal to the electric analog signal. Consequently, the analog signal is converted to the digital signal via the ADC converted and fed to the microcontroller. The AT89S52 microcontroller will receive and analyze the data and change the motor drives signal. Finally, the motor driving signal to be fed to the motor drive circuit, in order to promote the rotation of the motor and achieve the effect of two-axis tracking system.

Keyword KeywordKeyword Keyword::::

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... i Abstract ... ii ... iii ... 1 ... 3 ... 6 ... 14 ... 16 ... 18 ... 19 ... 20 ... 23

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Silicon-base Solar Cells

1. 2. 3. 4.

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1.1 1887

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AT89S52 2.1.X D D C AT89S52 C D E A B Y X 2.1 2.1

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C D AT89S52 C D E A B Y X 2.2 2.2 2.2.Y X A B AT89S52 A B E Y

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2.3 2.3 B A AT89S52 A B E Y 2.4 2.4

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A. (1)AT89S52 (2)ADC0804 (3)74244 (4)74138 (5) (6) (7) (8) (9) 3.1 3.1 3.1.AT89S52 AT89S52 40 3.3

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3.3 AT89S52

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Analog to Digital Converter ADC

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3.1 ADC0804 VREF=2.560 F 1111 15/16 15/256 4.800 0.300 E 1110 14/16 14/256 4.480 0.280 D 1101 13/16 13/256 4.160 0.260 C 1100 12/16 12/256 3.840 0.240 B 1011 11/16 11/256 3.520 0.220 A 1010 10/16 10/256 3.200 0.200 9 1001 9/16 9/256 2.880 0.180 8 1000 8/16 8/256 2.560 0.160 7 0111 7/16 7/256 2.240 0.140 6 0110 6/16 6/256 1.920 0.120 5 0101 5/16 5/256 1.600 0.100 4 0100 4/16 4/256 1.280 0.080 3 0011 3/16 3/256 0.960 0.060 2 0010 2/16 2/256 0.640 0.040 1 0001 1/16 1/256 0.320 0.020 0 0000 0 0 ADC0804 AT89S52 0 5 V 5 V AT89S52 12v 3.3.74138 74LS138 3 8 3 8 1 74LS138 32

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4

3.5 74138 AT89S52 2x4

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3.4.74LS244 74LS244 3.6 74244 AT89S52 0 1 AT89S52 3.3 74244

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3.5. R3 R2 470 340 1.4v R2 R2 3.7

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B.

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4.1 1. 2. 3. 5V AT89S52 4. AT89S52 5. 4.2 1. 2. 3. AT89S52 12v AT89S52 4. 5.

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5.1 1. 2. 3. LCD 4. 5. 6. 7. 8. 9.

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Layout Layout

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5 14 5 15 5 18 5 21

5 22 5 24 5 25 5 26

Layout Layout Layout

5 28 5 30 5 31 6 1

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Timer Duty JB

AT89S52

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BJT

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Layout

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ASM ORG 0000H MOV TMOD,#01H START: ACALL PLANE JB P3.3,A1 JB P3.4,A2 JB P3.5,PLANE02 JB P3.6,PLANE02 AJMP START A1: ACALL RIGHT MOV P0,#00000000B ACALL DELAY JNB P3.7,A1 HOLD: MOV P0,#00000000B JB P3.7,HOLD AJMP START A2: ACALL LEFT MOV P0,#00000000B ACALL DELAY JNB P3.7,A2 HOLD1: MOV P0,#00000000B JB P3.7,HOLD1 AJMP START PLANE: MOV P0,#00000000B ACALL DELAY1

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MOV R1,#5 PLANE1: MOV R2,#100 PLANE2: MOV P0,#10010000B MOV TL0,#0F1H MOV TH0,#0FFH SETB TR0 BACKP1: JNB TF0,BACKP1 CLR TR0 CLR TF0 MOV P0,#10000000B MOV TL0,#0DDH MOV TH0,#0FFH SETB TR0 BACKP2: JNB TF0,BACKP2 CLR TR0 CLR TF0 DJNZ R2,PLANE2 DJNZ R1,PLANE1 RET PLANE02: MOV P0,#00000000B ACALL DELAY1 MOV R1,#5 PLANE21: MOV R2,#100 PLANE22: MOV P0,#10010000B MOV TL0,#0F1H MOV TH0,#0FFH SETB TR0 BACKP21: JNB TF0,BACKP21 CLR TR0

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CLR TF0 MOV P0,#10000000B MOV TL0,#0DDH MOV TH0,#0FFH SETB TR0 BACKP22: JNB TF0,BACKP22 CLR TR0 CLR TF0 DJNZ R2,PLANE22 DJNZ R1,PLANE21 AJMP START RIGHT: MOV R1,#15 RIGHT1: MOV R2,#100 RIGHT2: MOV P0,#00001001B MOV TL0,#0F1H MOV TH0,#0FFH SETB TR0 BACKR1: JNB TF0,BACKR1 CLR TR0 CLR TF0 MOV P0,#00001000B MOV TL0,#0DDH MOV TH0,#0FFH SETB TR0 BACKR2: JNB TF0,BACKR2 CLR TR0 CLR TF0 DJNZ R2,RIGHT2 DJNZ R1,RIGHT1 RET

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LEFT: MOV R1,#15 LEFT1: MOV R2,#100 LEFT2: MOV P0,#00000110B MOV TL0,#0F1H MOV TH0,#0FFH SETB TR0 BACKL1: JNB TF0,BACKL1 CLR TR0 CLR TF0 MOV P0,#00000010B MOV TL0,#0DDH MOV TH0,#0FFH SETB TR0 BACKL2: JNB TF0,BACKL2 CLR TR0 CLR TF0 DJNZ R2,LEFT2 DJNZ R1,LEFT1 RET DELAY: MOV R7,#3 DL1:MOV R6,#200 DL2:MOV R5,#250 DL3:DJNZ R5,DL3 DJNZ R6,DL2 DJNZ R7,DL1 RET DELAY1: MOV R7,#10 DLL1:MOV R6,#200

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DLL2:MOV R5,#250 DLL3:DJNZ R5,DLL3 DJNZ R6,DLL2 DJNZ R7,DLL1 RET END

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LAYOUT

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[1]. AT89S52/8951 2006 6 [2]. [3]. [4].

參考文獻

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